From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5352036E1; Mon, 3 Feb 2025 13:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588512; cv=none; b=LFnp4sr5wBsGj/0BdopiMknQO8ycHAluz5pDUDsglplpi0CJp7mVjnr9hYNVhfB56EGGIcBjQ2AJCeZwcQhBojGxiLuCu1Efd2yvIiZPKhUwBhW11YQFWl0izCPHexfwezZVgtxG8V06ZnlYkkSV6tD8fWNCr68jPxHVIZ1/nuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588512; c=relaxed/simple; bh=qdhAxd1SxrCHuOZUxamDhWd3yhc2qTWzYWxEB7vVBHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QqTETrWw+uYDeblITY7jdSqBUGZ7Zyfi8zK74FWeeZ7d3zz4yMZbUFhUYypUDxCmmetMJD793MqPvQ7pg0FNO16Yeu8ptMFPD1B6dViKpjPf3+YF+DirjY+sZXG8qCISK/TkJfVF6OuwSoG3cKSYNhye3EnC5mlMtDeW0yxTgXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y9TnG7eu; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y9TnG7eu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588511; x=1770124511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qdhAxd1SxrCHuOZUxamDhWd3yhc2qTWzYWxEB7vVBHM=; b=Y9TnG7euhFJ/kvYbVCvq+QsQkOYstKojDshkwuWUtIenMSDpu992SSD/ 5Qd1Ttpl8PUMDRiJZzXs/mlHI6oofQ/pI0cKK69ccBr6UFnQ935FcN2nM 0X8CRpLjB13e/GsRtHbnBp5hAgp2/Lg53TsJQjZxJYeWZaMUA9zfKOb2Y Ss6g1id0xVZEf6eSC9naGIQQov4mhUkB6or1pGZSUgKJEEvfdvIkOIE8b jmcDjNaophmOyMIv2+o906fj/zhLt7RrMlBEBYLZT7xTEFDshYdF5gl0j GIvSakGdWJ789prDLZ5MM2Qd0kXzFhHrLkUbtexLcSKqnDGuKC93EaIkG A==; X-CSE-ConnectionGUID: 1ZLXNL1LRSSgUxNiiPHtsA== X-CSE-MsgGUID: siuPeR9kQWeOlanY+qmINw== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="56615939" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="56615939" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:10 -0800 X-CSE-ConnectionGUID: TvbQ+AgkTWCB7f7WakKKnw== X-CSE-MsgGUID: LPn3M4xJQpWhmsFKI9BXDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="110854188" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:09 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id AC8F0214; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 01/14] pinctrl: cy8c95x0: Fix off-by-one in the regmap range settings Date: Mon, 3 Feb 2025 15:10:27 +0200 Message-ID: <20250203131506.3318201-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The range_max is inclusive, so we need to use the number of the last accessible register address. Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 825bd1e528b5..cda9e1b6fed6 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1438,15 +1438,15 @@ static int cy8c95x0_probe(struct i2c_client *client) switch (chip->tpin) { case 20: strscpy(chip->name, cy8c95x0_id[0].name); - regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE; + regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; break; case 40: strscpy(chip->name, cy8c95x0_id[1].name); - regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE; + regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; break; case 60: strscpy(chip->name, cy8c95x0_id[2].name); - regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE; + regmap_range_conf.range_max =3D CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; break; default: return -ENODEV; --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD9D3201002; Mon, 3 Feb 2025 13:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588512; cv=none; b=QPY0P/4SHN2MdjSudZNkGUlE5LT49Wksy3RhzdPsWRiPBZS2vYjJ7hR5YAkH2oa1Nf2WfEThsS+Q3H1vU+P+uiXLPxycGdR+nPOg91VWb12DziIMtfCa2eGoUwaOgSt6YFNFGfiePKKwV+LsmAHb/6YjESkUuclLptWZRXC5PLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588512; c=relaxed/simple; bh=gs4Zt0xEqSo1Z8vwU6FIloykVDGXSg9fCQEbpQ8eQ6A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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03 Feb 2025 05:15:09 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id BAA05399; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 02/14] pinctrl: cy8c95x0: Avoid accessing reserved registers Date: Mon, 3 Feb 2025 15:10:28 +0200 Message-ID: <20250203131506.3318201-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The checks for vrtual registers in the cy8c95x0_readable_register() and cy8c95x0_writeable_register() are not aligned and broken. Fix that by explicitly avoiding reserved registers to be accessed. Fixes: 71e4001a0455 ("pinctrl: pinctrl-cy8c95x0: Fix regcache") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index cda9e1b6fed6..192a37c28a1d 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -328,14 +328,14 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinct= rl *chip, unsigned int pin) static bool cy8c95x0_readable_register(struct device *dev, unsigned int re= g) { /* - * Only 12 registers are present per port (see Table 6 in the - * datasheet). + * Only 12 registers are present per port (see Table 6 in the datasheet). */ - if (reg >=3D CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12) - return true; + if (reg >=3D CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >=3D 12) + return false; =20 switch (reg) { case 0x24 ... 0x27: + case 0x31 ... 0x3f: return false; default: return true; @@ -344,8 +344,11 @@ static bool cy8c95x0_readable_register(struct device *= dev, unsigned int reg) =20 static bool cy8c95x0_writeable_register(struct device *dev, unsigned int r= eg) { - if (reg >=3D CY8C95X0_VIRTUAL) - return true; + /* + * Only 12 registers are present per port (see Table 6 in the datasheet). + */ + if (reg >=3D CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >=3D 12) + return false; =20 switch (reg) { case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): @@ -353,6 +356,7 @@ static bool cy8c95x0_writeable_register(struct device *= dev, unsigned int reg) case CY8C95X0_DEVID: return false; case 0x24 ... 0x27: + case 0x31 ... 0x3f: return false; default: return true; --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6287204F63; Mon, 3 Feb 2025 13:15:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588514; cv=none; b=c2SAtGutfKX2L37lRdN6eVE7epZfa72fV4Nzo7b13OV/qMXNyyb7dtYg57zIy7hOPffLlg2myHHfD6hQCnkUldsiAt8654N8gI7Z7ikPIM72x/Jg/0jWMTY8zjpiCJouqm7EWrXmoqPByToX4w7S8LLKN7k5knbMvnBTnKVJW00= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588514; c=relaxed/simple; bh=gXwz5Ujw6IWP5uaIKaqjpo3prwTqc/XmNMiFvq5Esi8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r3f9V5iHrqOBFlj67Ll/NnumCPXxU3elGoq0cXjkVnf8JOeCbFHlspOKwaOHKb+0cCBhE+IEcvub6A4JwvTAPf63bERzT/X8QpQ+5hlFtz2KRZRoVfMdP+0wyI1XIPgZE33XnDsqb2oOahL9F7UAVRg+RfIYEHMllLPNTvrZ5+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HoEqkTVm; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HoEqkTVm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588513; x=1770124513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gXwz5Ujw6IWP5uaIKaqjpo3prwTqc/XmNMiFvq5Esi8=; b=HoEqkTVm7WCcdiTZbLwzNjTcLRndL2BXhXXZaeezBwJLUGBF40nGkY7+ +LL7xgO0LBrYHEjlwtOfVRT3GmV8RUJrDL9zX43IX3sJlEJKiTaZnlrHI V8csFdmV8fnAvR9OgJTLSP3A1wMnxKoOXHq+4LX0HwWmI2ho2XxAemWJj 0xjTWl3v2yfM9WkU8WB95U4MBqD2WQ1GMJTY7kUIunGYnhfJglkVMerNA QBZSpRYKPTbyp8coAvyELHlHMBcbhqMiB2DETm/Yuy30kQjhDT9yqZid3 x3KjwFqi5WNGFrYqKWi97puna7gfYa2/awSVMKv1SZeERPHQWEoXIGxjh w==; X-CSE-ConnectionGUID: 2OFxr12/QyimnIzpVi3Fvg== X-CSE-MsgGUID: zV0g/XRrRBq3vlwp65wdrw== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="56615947" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="56615947" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:10 -0800 X-CSE-ConnectionGUID: AEK6G9XaRTST1hQWO6A4hA== X-CSE-MsgGUID: 2ewiZXqGTvS8wgdLUOUOcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="110854190" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:09 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id BFB5F353; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 03/14] pinctrl: cy8c95x0: Enable regmap locking for debug Date: Mon, 3 Feb 2025 15:10:29 +0200 Message-ID: <20250203131506.3318201-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When regmap locking is disabled, debugfs is also disabled. Enable locking for debug when CONFIG_DEBUG_PINCTRL is set. Fixes: f71aba339a66 ("pinctrl: cy8c95x0: Use single I2C lock") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 192a37c28a1d..0bcecebb1c0c 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -470,7 +470,11 @@ static const struct regmap_config cy8c9520_i2c_regmap = =3D { .max_register =3D 0, /* Updated at runtime */ .num_reg_defaults_raw =3D 0, /* Updated at runtime */ .use_single_read =3D true, /* Workaround for regcache bug */ +#if IS_ENABLED(CONFIG_DEBUG_PINCTRL) + .disable_locking =3D false, +#else .disable_locking =3D true, +#endif }; =20 static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl= *chip, --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8BD8205503; Mon, 3 Feb 2025 13:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588516; cv=none; b=qbyf8GqJTmpjnOCSkQTUyP/U8pptuN0/E1WYl7xhV0WZF2tbL6nV2kRnH/rzVQRQZNOmyq+uLSNBWhOeyHs0YlzT137Ih8TYSyQf4EswbxInUk9RGT7mLVkKiskUeUSoaekxcnS1z6xup6yQ1TXz96f1UNDZjt8g0VbcKpSnQjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588516; c=relaxed/simple; bh=2hAKTMMqjEXGla9aasq+OrZMKP1a3APtYe0wzu7JSCM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XRGGBp/fOLPNdYN/nb/yVk67VS6dOuEK6TQwapyQNGJOmDR2LLwhRe1cmA1mz4ieMcKMgpAZj0ACcux6xdfTfbC2++sQ5Lq/Xg6PLl5lDhCvVecFAcjo8UjLldOW0QXufImpy6+Kvyv4fo7telEZqnSiPi3FRq/T2b3EbiLUekg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=I3Vt8VUC; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="I3Vt8VUC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588515; x=1770124515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2hAKTMMqjEXGla9aasq+OrZMKP1a3APtYe0wzu7JSCM=; b=I3Vt8VUCC/lbv4H4Ry6lGiLzPobC8fmcOZceqSeb/c0+B7soj0TwyV4V LDmuSjItYg0ww/TSGl69U9twQgmVMth9Hv8/LdIuVRV1ln+np0CLhRL2w 6tGBGrPnKzoXz0A9afDQOdVe2+h/yQUTvv3ZF3G3okxAXrVCl3nyOhDeS UdYufV2zDdnLQ1MySTJkzKGvmavEj6eGKaF4RuqC0ljQry51qo8X05eed em0IroYfgka5ibzZBsIOW7m5w0osXWo2MEBYZ8wq7TGMbdYnrp9CL8oKN x+y9oZcNqnJUkGeawU8m+kx0p8C/hp62WvlQgbjORdYqHfLYrQf3+9vxm A==; X-CSE-ConnectionGUID: 7CXEF6XnTsilYw+vrE4tFg== X-CSE-MsgGUID: DGnCjxbBQGSv5GDMOlzBNw== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="56615951" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="56615951" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:11 -0800 X-CSE-ConnectionGUID: qC1FDvEnSzmuaPDebLCUpA== X-CSE-MsgGUID: duZsFJkEQqaRwuqOWXxBqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="110854192" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:09 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id CD92F3B1; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 04/14] pinctrl: cy8c95x0: Rename PWMSEL to SELPWM Date: Mon, 3 Feb 2025 15:10:30 +0200 Message-ID: <20250203131506.3318201-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are two registers in the hardware, one, "Select PWM", is per-port configuration enabling PWM function instead of GPIO. The other one is "PWM Select" is per-PWM selector to configure PWM itself. Original code uses abbreviation of the latter to describe the former. Rename it to follow the datasheet. Fixes: e6cbbe42944d ("pinctrl: Add Cypress cy8c95x0 support") Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 0bcecebb1c0c..d73004b4a45e 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -42,7 +42,7 @@ #define CY8C95X0_PORTSEL 0x18 /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK 0x19 -#define CY8C95X0_PWMSEL 0x1A +#define CY8C95X0_SELPWM 0x1A #define CY8C95X0_INVERT 0x1B #define CY8C95X0_DIRECTION 0x1C /* Drive mode register change state on writing '1' */ @@ -369,8 +369,8 @@ static bool cy8c95x0_volatile_register(struct device *d= ev, unsigned int reg) case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): case CY8C95X0_INTMASK: + case CY8C95X0_SELPWM: case CY8C95X0_INVERT: - case CY8C95X0_PWMSEL: case CY8C95X0_DIRECTION: case CY8C95X0_DRV_PU: case CY8C95X0_DRV_PD: @@ -399,7 +399,7 @@ static bool cy8c95x0_muxed_register(unsigned int reg) { switch (reg) { case CY8C95X0_INTMASK: - case CY8C95X0_PWMSEL: + case CY8C95X0_SELPWM: case CY8C95X0_INVERT: case CY8C95X0_DIRECTION: case CY8C95X0_DRV_PU: @@ -797,7 +797,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pin= ctrl *chip, reg =3D CY8C95X0_DIRECTION; break; case PIN_CONFIG_MODE_PWM: - reg =3D CY8C95X0_PWMSEL; + reg =3D CY8C95X0_SELPWM; break; case PIN_CONFIG_OUTPUT: reg =3D CY8C95X0_OUTPUT; @@ -876,7 +876,7 @@ static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pin= ctrl *chip, reg =3D CY8C95X0_DRV_PP_FAST; break; case PIN_CONFIG_MODE_PWM: - reg =3D CY8C95X0_PWMSEL; + reg =3D CY8C95X0_SELPWM; break; case PIN_CONFIG_OUTPUT_ENABLE: return cy8c95x0_pinmux_direction(chip, off, !arg); @@ -1161,7 +1161,7 @@ static void cy8c95x0_pin_dbg_show(struct pinctrl_dev = *pctldev, struct seq_file * bitmap_zero(mask, MAX_LINE); __set_bit(pin, mask); =20 - if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) { + if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { seq_puts(s, "not available"); return; } @@ -1206,7 +1206,7 @@ static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl = *chip, unsigned int off, bo u8 port =3D cypress_get_port(chip, off); u8 bit =3D cypress_get_pin_mask(chip, off); =20 - return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, bit, mode = ? bit : 0); + return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode = ? bit : 0); } =20 static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40A5A205519; Mon, 3 Feb 2025 13:15:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588517; cv=none; b=X6rLJZb5fOXhmfeFb0njD9uTbNHkxJ4fDgIrvcoTu+WSXecB4ekAx8KPVKBBYchhrfA5O35kK0NqD4XYv506pVQN2GqrD58qsH3JIVHvxaRn3Uu3Vxyvb+UUXbyMXDK2AzqDxr0U+0beJ+KNJL2Ir52J82VLVxgNcaZqtbII30Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588517; c=relaxed/simple; bh=9hbhJ/OGcbx2u5M6L6AVNb9EanjkqtbRFH64m31jAH8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TlaZ4lhKdAdOjU8laaKz9NhTsMOFr7hy1Lqex/stQmQ7s+M6nlB3vm5NNwksf3vXJgxj5OOL6wqcCouhZSsuZxK2a0AZTcBEahBI7DFqLbFcOmHvezE5cdf1owwTh9sAaBO0h48Nbakh1UOjyNM3iRa1QLAgT0Z/MVoixSZYY2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L6blbxl4; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L6blbxl4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588515; x=1770124515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9hbhJ/OGcbx2u5M6L6AVNb9EanjkqtbRFH64m31jAH8=; b=L6blbxl4rzWKdPAdquqKHzQFfmOW8iGncJzoQ9+DgD7hnfvL+NNx7+r5 j09C07VGV8Zdy7eWpMQ7euNUaMUQS1IEnobuy69iXdF6AJUwPTghjc8Qe F+zwGjqnFNvkpzdEoQ32UZ9u9PTGOOjtaT1wNMDBcSX24TgVqWI5bSg0Q DN12nRaDGqFRUkuFR7CjsCr5Le8LNU2iqoswKiJXtLtqyE6zeY2n42eMM rrHV0zxwC17S7nq05Wl2XDq9RS2hqBOte9wXYaouFOqC1t2NQ7uqEcRwa qC9498aBVzFYcocFwC8hZeYQiE7VuvkA+UHZCsgga8neWJRXjRIT5BzD9 A==; X-CSE-ConnectionGUID: tUXKU0MBTT2gW6oMej7RTA== X-CSE-MsgGUID: wjDAOAIvT+ewtDEemFg4RQ== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="39217692" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="39217692" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:12 -0800 X-CSE-ConnectionGUID: yNs2vvw9RwyGpCQN1sIZFA== X-CSE-MsgGUID: 0k4aAtZYSjyQ9uPqA1+y+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="115287398" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 03 Feb 2025 05:15:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id D73983A7; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 05/14] pinctrl: cy8c95x0: Use better bitmap APIs where appropriate Date: Mon, 3 Feb 2025 15:10:31 +0200 Message-ID: <20250203131506.3318201-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are bitmap_gather() and bitmap_scatter() that are factually reimplemented in the driver. Use better bitmap APIs where appropriate. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 33 +++++++++++------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index d73004b4a45e..52d8a44bb44e 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -137,7 +137,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq= _info[] =3D { * @irq_trig_low: I/O bits affected by a low voltage level * @irq_trig_high: I/O bits affected by a high voltage level * @push_pull: I/O bits configured as push pull driver - * @shiftmask: Mask used to compensate for Gport2 width + * @map: Mask used to compensate for Gport2 width * @nport: Number of Gports in this chip * @gpio_chip: gpiolib chip * @driver_data: private driver data @@ -158,7 +158,7 @@ struct cy8c95x0_pinctrl { DECLARE_BITMAP(irq_trig_low, MAX_LINE); DECLARE_BITMAP(irq_trig_high, MAX_LINE); DECLARE_BITMAP(push_pull, MAX_LINE); - DECLARE_BITMAP(shiftmask, MAX_LINE); + DECLARE_BITMAP(map, MAX_LINE); unsigned int nport; struct gpio_chip gpio_chip; unsigned long driver_data; @@ -622,13 +622,8 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pi= nctrl *chip, int reg, int ret; =20 /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); =20 for (unsigned int i =3D 0; i < chip->nport; i++) { /* Skip over unused banks */ @@ -653,19 +648,13 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pi= nctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); - DECLARE_BITMAP(tmp, MAX_LINE); int read_val; u8 bits; int ret; =20 /* Add the 4 bit gap of Gport2 */ - bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tmask, tmask, 4, MAX_LINE); - bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3); - - bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE); - bitmap_shift_left(tval, tval, 4, MAX_LINE); - bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3); + bitmap_scatter(tmask, mask, chip->map, MAX_LINE); + bitmap_scatter(tval, val, chip->map, MAX_LINE); =20 for (unsigned int i =3D 0; i < chip->nport; i++) { /* Skip over unused banks */ @@ -685,8 +674,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinc= trl *chip, int reg, } =20 /* Fill the 4 bit gap of Gport2 */ - bitmap_shift_right(tmp, tval, 4, MAX_LINE); - bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE); + bitmap_gather(tval, val, chip->map, MAX_LINE); =20 return 0; } @@ -1486,8 +1474,11 @@ static int cy8c95x0_probe(struct i2c_client *client) return PTR_ERR(chip->regmap); =20 bitmap_zero(chip->push_pull, MAX_LINE); - bitmap_zero(chip->shiftmask, MAX_LINE); - bitmap_set(chip->shiftmask, 0, 20); + + /* Setup HW pins mapping */ + bitmap_fill(chip->map, MAX_LINE); + bitmap_clear(chip->map, 20, 4); + mutex_init(&chip->i2c_lock); =20 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12BDE204F8B; Mon, 3 Feb 2025 13:15:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588514; cv=none; b=iBI4yI97gZHHIvwwvzPb4/UEJ+X92ivgwOd3sIeAHoShT4dssyhgpsvzbUIHNxkcxrb/RwxN8wEHcYfWPn3uWh7zQFFC6aQJTwQfvecStE1OZ+IDzJ0quZxxox2LpBv+QxYxQCkurLzvzFWCybSxeB4fW3OyH4EQM4vF9NKeoYU= ARC-Message-Signature: i=1; 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d="scan'208";a="115287397" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 03 Feb 2025 05:15:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id E16A849A; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 06/14] pinctrl: cy8c95x0; Switch to use for_each_set_clump8() Date: Mon, 3 Feb 2025 15:10:32 +0200 Message-ID: <20250203131506.3318201-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" for_each_set_clump8() has embedded check for unset clump to skip. Switch driver to use for_each_set_clump8(). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 52d8a44bb44e..93fb8afab643 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -617,21 +617,18 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_p= inctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); + unsigned long bits, offset; int write_val; - u8 bits; int ret; =20 /* Add the 4 bit gap of Gport2 */ bitmap_scatter(tmask, mask, chip->map, MAX_LINE); bitmap_scatter(tval, val, chip->map, MAX_LINE); =20 - for (unsigned int i =3D 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits =3D bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i =3D offset / 8; =20 - write_val =3D bitmap_get_value8(tval, i * BANK_SZ); + write_val =3D bitmap_get_value8(tval, offset); =20 ret =3D cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); if (ret < 0) { @@ -648,19 +645,16 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pi= nctrl *chip, int reg, { DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); + unsigned long bits, offset; int read_val; - u8 bits; int ret; =20 /* Add the 4 bit gap of Gport2 */ bitmap_scatter(tmask, mask, chip->map, MAX_LINE); bitmap_scatter(tval, val, chip->map, MAX_LINE); =20 - for (unsigned int i =3D 0; i < chip->nport; i++) { - /* Skip over unused banks */ - bits =3D bitmap_get_value8(tmask, i * BANK_SZ); - if (!bits) - continue; + for_each_set_clump8(offset, bits, tmask, chip->tpin) { + unsigned int i =3D offset / 8; =20 ret =3D cy8c95x0_regmap_read(chip, reg, i, &read_val); if (ret < 0) { @@ -669,8 +663,8 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinc= trl *chip, int reg, } =20 read_val &=3D bits; - read_val |=3D bitmap_get_value8(tval, i * BANK_SZ) & ~bits; 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d="scan'208";a="110854205" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id EB9C34F0; Mon, 03 Feb 2025 15:15:07 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 07/14] pinctrl: cy8c95x0: Transform to cy8c95x0_regmap_read_bits() Date: Mon, 3 Feb 2025 15:10:33 +0200 Message-ID: <20250203131506.3318201-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The returned value of cy8c95x0_regmap_read() is used always with a bitmask being applied. Move that bitmasking code into the function. At the same time transform it to cy8c95x0_regmap_read_bits() which will be in align with the write and update counterparts. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 45 +++++++++++++++++------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 93fb8afab643..02b692118cb2 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -575,12 +575,13 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x= 0_pinctrl *chip, unsigned i } =20 /** - * cy8c95x0_regmap_read() - reads a register using the regmap cache + * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache * @chip: The pinctrl to work on * @reg: The register to read from. Can be direct access or muxed register. * @port: The port to be used for muxed registers or quick path direct acc= ess * registers. Otherwise unused. - * @read_val: Value read from hardware or cache + * @mask: Bitmask to apply + * @val: Value read from hardware or cache * * This function handles the register reads from the direct access registe= rs and * the muxed registers while caching all register accesses, internally han= dling @@ -590,10 +591,12 @@ static int cy8c95x0_regmap_update_bits(struct cy8c95x= 0_pinctrl *chip, unsigned i * * Return: 0 for successful request, else a corresponding error value */ -static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned in= t reg, - unsigned int port, unsigned int *read_val) +static int cy8c95x0_regmap_read_bits(struct cy8c95x0_pinctrl *chip, unsign= ed int reg, + unsigned int port, unsigned int mask, unsigned int *val) { - int off, ret; + unsigned int off; + unsigned int tmp; + int ret; =20 /* Registers behind the PORTSEL mux have their own range in regmap */ if (cy8c95x0_muxed_register(reg)) { @@ -605,11 +608,14 @@ static int cy8c95x0_regmap_read(struct cy8c95x0_pinct= rl *chip, unsigned int reg, else off =3D reg; } - guard(mutex)(&chip->i2c_lock); =20 - ret =3D regmap_read(chip->regmap, off, read_val); + scoped_guard(mutex, &chip->i2c_lock) + ret =3D regmap_read(chip->regmap, off, &tmp); + if (ret) + return ret; =20 - return ret; + *val =3D tmp & mask; + return 0; } =20 static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, @@ -646,7 +652,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinc= trl *chip, int reg, DECLARE_BITMAP(tmask, MAX_LINE); DECLARE_BITMAP(tval, MAX_LINE); unsigned long bits, offset; - int read_val; + unsigned int read_val; int ret; =20 /* Add the 4 bit gap of Gport2 */ @@ -656,13 +662,12 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pi= nctrl *chip, int reg, for_each_set_clump8(offset, bits, tmask, chip->tpin) { unsigned int i =3D offset / 8; =20 - ret =3D cy8c95x0_regmap_read(chip, reg, i, &read_val); + ret =3D cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val); if (ret < 0) { dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg= , i, ret); return ret; } =20 - read_val &=3D bits; read_val |=3D bitmap_get_value8(tval, offset) & ~bits; bitmap_set_value8(tval, read_val, offset); } @@ -699,10 +704,10 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *= gc, unsigned int off) struct cy8c95x0_pinctrl *chip =3D gpiochip_get_data(gc); u8 port =3D cypress_get_port(chip, off); u8 bit =3D cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; =20 - ret =3D cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, ®_val); + ret =3D cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_v= al); if (ret < 0) { /* * NOTE: @@ -713,7 +718,7 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc= , unsigned int off) return 0; } =20 - return !!(reg_val & bit); + return reg_val ? 1 : 0; } =20 static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, @@ -731,14 +736,14 @@ static int cy8c95x0_gpio_get_direction(struct gpio_ch= ip *gc, unsigned int off) struct cy8c95x0_pinctrl *chip =3D gpiochip_get_data(gc); u8 port =3D cypress_get_port(chip, off); u8 bit =3D cypress_get_pin_mask(chip, off); - u32 reg_val; + unsigned int reg_val; int ret; =20 - ret =3D cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, ®_val); + ret =3D cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, &r= eg_val); if (ret < 0) return ret; =20 - if (reg_val & bit) + if (reg_val) return GPIO_LINE_DIRECTION_IN; =20 return GPIO_LINE_DIRECTION_OUT; @@ -751,8 +756,8 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pin= ctrl *chip, enum pin_config_param param =3D pinconf_to_config_param(*config); u8 port =3D cypress_get_port(chip, off); u8 bit =3D cypress_get_pin_mask(chip, off); + unsigned int reg_val; unsigned int reg; - u32 reg_val; u16 arg =3D 0; int ret; =20 @@ -809,11 +814,11 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_p= inctrl *chip, * Writing 1 to one of the drive mode registers will automatically * clear conflicting set bits in the other drive mode registers. */ - ret =3D cy8c95x0_regmap_read(chip, reg, port, ®_val); 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charset="utf-8" The function is never called with the PORTSEL register in the argument. Drop unneeded check, but rescue a comment. While at it, drop inline and allow any compiler to choose better stragy (note, that inline in C code is only a recomendation to most of the modern compilers anyway). Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 02b692118cb2..cd191cb1101e 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -477,20 +477,14 @@ static const struct regmap_config cy8c9520_i2c_regmap= =3D { #endif }; =20 -static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl= *chip, - unsigned int reg, - unsigned int port, - unsigned int mask, - unsigned int val, - bool *change, bool async, - bool force) +/* Caller should never modify PORTSEL directly */ +static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, + unsigned int reg, unsigned int port, + unsigned int mask, unsigned int val, + bool *change, bool async, bool force) { int ret, off, i; =20 - /* Caller should never modify PORTSEL directly */ - if (reg =3D=3D CY8C95X0_PORTSEL) - return -EINVAL; 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03 Feb 2025 05:15:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 0F4FD5E3; Mon, 03 Feb 2025 15:15:08 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 09/14] pinctrl: cy8c95x0: Replace 'return ret' by 'return 0' in some cases Date: Mon, 3 Feb 2025 15:10:35 +0200 Message-ID: <20250203131506.3318201-10-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When it's known that the returned value can't be non-zero, use 'return 0' explicitly. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index cd191cb1101e..e02cab05cbfc 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -517,7 +517,7 @@ static int cy8c95x0_regmap_update_bits_base(struct cy8c= 95x0_pinctrl *chip, regcache_cache_only(chip->regmap, false); } =20 - return ret; + return 0; } =20 /** @@ -1286,7 +1286,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *p= ctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { struct cy8c95x0_pinctrl *chip =3D pinctrl_dev_get_drvdata(pctldev); - int ret =3D 0; + int ret; int i; =20 for (i =3D 0; i < num_configs; i++) { @@ -1295,7 +1295,7 @@ static int cy8c95x0_pinconf_set(struct pinctrl_dev *p= ctldev, unsigned int pin, return ret; } =20 - return ret; + return 0; } =20 static const struct pinconf_ops cy8c95x0_pinconf_ops =3D { --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C92C204F92; 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charset="utf-8" The 'ret' variable in cy8c95x0_irq_handler() is defined as bool, but is intialised with integers. Avoid implicit castings and initialise boolean variable with boolean values. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index e02cab05cbfc..0aad4ed79699 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1076,7 +1076,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void= *devid) if (!ret) return IRQ_RETVAL(0); =20 - ret =3D 0; + ret =3D false; for_each_set_bit(level, pending, MAX_LINE) { /* Already accounted for 4bit gap in GPort2 */ nested_irq =3D irq_find_mapping(gc->irq.domain, level); @@ -1095,7 +1095,7 @@ static irqreturn_t cy8c95x0_irq_handler(int irq, void= *devid) else handle_nested_irq(nested_irq); =20 - ret =3D 1; + ret =3D true; } =20 return IRQ_RETVAL(ret); --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D42D201009; Mon, 3 Feb 2025 13:15:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588517; cv=none; b=cO/FkAuLDS+x+Eltkic6uo+Q2I6suziUc2ClTJ4C51hAAZQkeeQsLwoIaHGglh+NueZ15SlOo6nZ7wsz+jGSzTXFcbvt1jLePmeBuYqxvUfbPPbk9l3Vb1iwW74KUPTLCqmCbCeidb2q4YVtw7E4HQk2jQzML63AzrKNiXrcC9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588517; c=relaxed/simple; bh=JQ0rNWoHugO8PQxdBUOFs2VhxzGvM6HnIwqk++NLNmo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GtC8JOewgHjKIzkmLoV/H4Pd6obH5OgKlg/qfDba1Rxne+gRkt9nyNqGZxGmJrsLhxw8fAkSBDCoipii+V1nrPeRWTNEwZ+MUkiW3C96eluWeSzaMHQrsuGyrMtpjI5uU/NqJTAoAlG0/iWLurVyCXf+MoITarXeZ8GwB9Ok7lQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aCsc68D2; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aCsc68D2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588515; x=1770124515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JQ0rNWoHugO8PQxdBUOFs2VhxzGvM6HnIwqk++NLNmo=; b=aCsc68D2g81WiXL4Pkc9FsglAKxh8oqP2JqHiE6lKmLw1iEy9Kbz9PIS UtxL1hEwOQ2zrOJB/b8m4ogbOQ/UeDarXdLIKy7qKGtQfWnPGFUzbj7af uBP6B/ufK/NHqPzTRmgl5yjvxRd8e7fZuQW6lBvLSJeHcSq9IffjfTMZz fUo2L7PDB2jTX7jFN92VC3DJDJtagm7zI8PUDQ0tN21qC6U3s6Iq9wKYm Npbu51kShY1TxriXUufnPqSYHfZtW62Xb30yGaHPzH8eSe32T4y8xrHxp jTYHTQMxpPEkbKLGYJvezo4i+IPt0O8ZqMecuwR1RyXYrRfVvMgonveMH A==; X-CSE-ConnectionGUID: kw7vFXS/STW+E3eY6C6F7A== X-CSE-MsgGUID: yKmcSY86TF6OC+brYS5ojA== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="56615963" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="56615963" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:12 -0800 X-CSE-ConnectionGUID: zLsDOUakTdGa4M+r3m858g== X-CSE-MsgGUID: txpfJLVISWaH07+vZwrnnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="110854206" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 21FF6627; Mon, 03 Feb 2025 15:15:08 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 11/14] pinctrl: cy8c95x0: Get rid of cy8c95x0_pinmux_direction() forward declaration Date: Mon, 3 Feb 2025 15:10:37 +0200 Message-ID: <20250203131506.3318201-12-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function is used before being defined. Just move it up enough to get rid of forward declaration. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 54 ++++++++++++++---------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 0aad4ed79699..a83a1b13a97f 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -310,9 +310,6 @@ static const char * const cy8c95x0_groups[] =3D { "gp77", }; =20 -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input); - static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned = int pin) { /* Account for GPORT2 which only has 4 bits */ @@ -672,6 +669,31 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pin= ctrl *chip, int reg, return 0; } =20 +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsign= ed int pin, bool input) +{ + u8 port =3D cypress_get_port(chip, pin); + u8 bit =3D cypress_get_pin_mask(chip, pin); + int ret; + + ret =3D cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, i= nput ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret =3D cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bi= t); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } + + return 0; +} + static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned in= t off) { return pinctrl_gpio_direction_input(gc, off); @@ -1229,32 +1251,6 @@ static int cy8c95x0_gpio_request_enable(struct pinct= rl_dev *pctldev, return cy8c95x0_set_mode(chip, pin, false); } =20 -static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, - unsigned int pin, bool input) -{ - u8 port =3D cypress_get_port(chip, pin); - u8 bit =3D cypress_get_pin_mask(chip, pin); - int ret; - - ret =3D cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, i= nput ? bit : 0); - if (ret) - return ret; - - /* - * Disable driving the pin by forcing it to HighZ. Only setting - * the direction register isn't sufficient in Push-Pull mode. - */ - if (input && test_bit(pin, chip->push_pull)) { - ret =3D cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bi= t); - if (ret) - return ret; - - __clear_bit(pin, chip->push_pull); - } - - return 0; -} - static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin, bool input) --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8138A205AD8; Mon, 3 Feb 2025 13:15:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; cv=none; b=O3UxNgJ6yWw0pKGWCfJVb5NVF5bNR2QPZY2ot3/uIpajaumCNuisK8Q61JX0GiImA0I7Pz0zbxov5s9zLA7g/JjpH/jl+i5u7gfPNxi3bMtU6SkJU+15eYTosvZppL+GC2yEWiIx+QoXSgHA6k/MyjW3jWHZhsJjqvdhjHQt6Yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; c=relaxed/simple; bh=dlhC7rJ9n0lI/L8+C6wSGYuSzKu7DPQBQfwHK8wMcwQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iQbIOAR0P49NMn/PhDuSuKvm/ACYzvECp8Hmd+/NZwq0T5yjsxwyGoG5u3omRmKvSO8BwliJFwTn5a90twAx3b6+Pbw/nHhw32ceDyS7dfO70X9+hOPo/sN2xlIZeM7CBjZ/K5eLTLOXGI6HpFAb5uLrkjm4+vHrp9RMGF7+r2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=m6wS6G45; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="m6wS6G45" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588516; x=1770124516; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dlhC7rJ9n0lI/L8+C6wSGYuSzKu7DPQBQfwHK8wMcwQ=; b=m6wS6G45VXJC3G9/pewhKjh82p8huAZYByBy1CTmmpex5RryJ3Cxo3LD 7/VY0xHcj8Rs0Vew+/IaYTwHfFvc6214qLZ7uBDNC9BigPZ+2la8PxPKX Wsz9EPTU99SQoyJyXRMS+n1isVEpmMwzxFqYW1aMPVUDj4mW7DbvDArNS oAu0nNbSB7yESym1ycpEyhei1jUANDt9bzNorF7+K/ZBDHTxVY5M+DVnb SKRFAlIL2ABFznrBjKND2XeIxl2AAfduNQo8vzs9425MHPjWGvDy/XoV0 42QSXCU0UVBgSUoak4fGbh8v/fUTO7wNKSzLP5CZRfUeY73LX+bUtVayv w==; X-CSE-ConnectionGUID: TbF0+YEvSuioQ/8hibbQUg== X-CSE-MsgGUID: FOys3ILMTFyJv+a+i20+Vw== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="56615967" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="56615967" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:12 -0800 X-CSE-ConnectionGUID: RwfInn77Ql2jIXx/KRQh2Q== X-CSE-MsgGUID: FVc0M7a0R7qOCfkSutp3/g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="110854207" Received: from black.fi.intel.com ([10.237.72.28]) by fmviesa009.fm.intel.com with ESMTP; 03 Feb 2025 05:15:11 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2FB67775; Mon, 03 Feb 2025 15:15:08 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 12/14] pinctrl: cy8c95x0: Drop unneeded casting Date: Mon, 3 Feb 2025 15:10:38 +0200 Message-ID: <20250203131506.3318201-13-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'arg' variable in cy8c95x0_gpio_get_pincfg() is already type of u16. No need to cast it, so drop unneeded casting. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index a83a1b13a97f..28374490d47d 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -839,7 +839,7 @@ static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pin= ctrl *chip, if (param =3D=3D PIN_CONFIG_OUTPUT_ENABLE) arg =3D !arg; =20 - *config =3D pinconf_to_config_packed(param, (u16)arg); + *config =3D pinconf_to_config_packed(param, arg); return 0; } =20 --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B256F205E02; Mon, 3 Feb 2025 13:15:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; cv=none; b=JJLlOIopAvwNc23B026tO8RyUHQpH5XmF+kmtiXjKreeRvIytlm65lB9YzA/HiGbtaaeCR+Ijg+CikXiwt2BixzYOIMetB4uv3DMOZjecBZuUp5f1AmUiAaVkaNI1f3CvFFdSmcHdYlx5nfiTlf8c6X/MGIgUYY5QXjVVZVEti4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; c=relaxed/simple; bh=LUJpClbX7oMeUIh098wHjPAs78Ycm8E1WEHScS2ZJfM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kx0Yz9XnK94NXyE6gPP87xtYIQ/HJlujiYCnyCGZKPEorKsJiklJTBcnUnqD6ElQuzYIFUoI0zzRRKM8pS/vVEz6IOo9eSlI0/VCTP3ibCOkDhibMIRZfJZNmiZAavf8RWwNUYBBORtMTluVAWQLfHVOy1K/DprWklV4neq++HE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QxH/TW3p; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QxH/TW3p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588516; x=1770124516; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LUJpClbX7oMeUIh098wHjPAs78Ycm8E1WEHScS2ZJfM=; b=QxH/TW3pOThWLmFIqipjUtooVb6kfBhtYjFFWpwLhT4Q24o45DJ3uuQo LM4hTRQ51KX8WFvnh4HnHLmqRCa8QedT4+HlFajo75QXDrBFLjL++wejb GsOuza3VZG0UOqM4zINoo0T6lWaSEVADZKCTeYCaJxtpwtIY12ML+ZL5g Xl2c8nwRmGaAYomKtXII6Iqejzm3svym6dzsdzW6mB1lZXQSu7VPZkZbh tXocRBnmMKDnHsecEkHb8eVtXTee5LvI7Hs2UU+12LAeH3LOvDilmUYHa H4vw/Asps8Zxpzm5hiWggQjw2c9ZF3STrmDGr6EINFpzH/nzu4H6HskmR w==; X-CSE-ConnectionGUID: +g8Jy1sdSlWUb2n4DX4oWg== X-CSE-MsgGUID: zWrEatxaSVSG3Co6JlLvqA== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="39217695" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="39217695" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:13 -0800 X-CSE-ConnectionGUID: M8cdY6WARtKAza77qY8N3A== X-CSE-MsgGUID: ggyzJbBtSy6Jy8DKAdIE2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="115287404" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 03 Feb 2025 05:15:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 3509F63F; Mon, 03 Feb 2025 15:15:08 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 13/14] pinctrl: cy8c95x0: Separate EEPROM related register definitios Date: Mon, 3 Feb 2025 15:10:39 +0200 Message-ID: <20250203131506.3318201-14-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently it's not easy to see at a glance the group of the registers that are per port. Add a blank line and a comment to make it better. Also add a missing definition for one of the EEPROM related registers. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index 28374490d47d..f03775341b60 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -40,6 +40,7 @@ =20 /* Port Select configures the port */ #define CY8C95X0_PORTSEL 0x18 + /* Port settings, write PORTSEL first */ #define CY8C95X0_INTMASK 0x19 #define CY8C95X0_SELPWM 0x1A @@ -53,6 +54,9 @@ #define CY8C95X0_DRV_PP_FAST 0x21 #define CY8C95X0_DRV_PP_SLOW 0x22 #define CY8C95X0_DRV_HIZ 0x23 + +/* Internal device configuration */ +#define CY8C95X0_ENABLE_WDE 0x2D #define CY8C95X0_DEVID 0x2E #define CY8C95X0_WATCHDOG 0x2F #define CY8C95X0_COMMAND 0x30 --=20 2.43.0.rc1.1336.g36b5255a03ac From nobody Sun Feb 8 05:59:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21D22205E1C; Mon, 3 Feb 2025 13:15:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; cv=none; b=qrq4THYv+13WjQxT4Uuzs+tCImYxRwD3lITYK77Fn3o31/KsxzGDhGzG762AJCF3q3vBnEdtiI6m5xizs35FaY9/zOwZpkNZACAIRBmK2jDuhTEhcLXUe2ZZDtotNsMRNavdqkiHR5DBWAawpAqIS1XhDY7gcDKPkmb1to2doYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738588518; c=relaxed/simple; bh=YTFqR0EQoACqXNuAPbiycPs8gfcRkIcqcIwXkdJK0ro=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KN1k6xmm8Lah+swXgz9omXccofGes0J37gyR75El5MjjG2JjVijtnaEAHBMDdJcetVQuim9RLmjwAUHs4xuOmSEJZ5C8XGyh8Xdxd9O2FiEWQLvZbL+zemVWpW9uFySAW8tUKoxoa3Ax1QK9GYGbTVNYpF+jvCu1dU36VuhzSRw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FiKRW/l9; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FiKRW/l9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738588517; x=1770124517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YTFqR0EQoACqXNuAPbiycPs8gfcRkIcqcIwXkdJK0ro=; b=FiKRW/l96sutMtxkG+TB9vKg2bdglOEEWWUkFEo2lD1B/cjGZBSx9u69 fk3Ffo8/UapfphTm1wrlkgnsXX1AEm1MHL3E6MqsrMzLKWR97lekeL4NI +mUeKr0sPmohjwYFJb/6P5rUKDaDVZFf8+YcsNSSMa6Q3BmqOyig2HxNO wtPjEe2RjoKHvJxMYAibRquN3R+XV16z8CSjkRg6dgjtMnu/4ucNSn2NK 2EYDMwAC8NZoJ9zqD/K0re4ttXtvF8Y3HPre8dB9USgSBonvqinF5K6S/ PPIByC+kigpaDWTah4i/u0rDXzyeVG22I0LGc+vs8yrhOHaa8wlM8sc0c g==; X-CSE-ConnectionGUID: noG5CmAfR9acs0Pa4HFNbw== X-CSE-MsgGUID: pS+mzCTiTUanOLLWABQ5IA== X-IronPort-AV: E=McAfee;i="6700,10204,11335"; a="39217699" X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="39217699" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2025 05:15:13 -0800 X-CSE-ConnectionGUID: y2XlsW9BTRGcOJMR5rkV9w== X-CSE-MsgGUID: 4SKSjhtOSV22Q2W6rNW2Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,255,1732608000"; d="scan'208";a="115287403" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa004.jf.intel.com with ESMTP; 03 Feb 2025 05:15:12 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 438567DD; Mon, 03 Feb 2025 15:15:08 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Patrick Rudolph , Linus Walleij Subject: [PATCH v2 14/14] pinctrl: cy8c95x0: Fix comment style Date: Mon, 3 Feb 2025 15:10:40 +0200 Message-ID: <20250203131506.3318201-15-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1336.g36b5255a03ac In-Reply-To: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> References: <20250203131506.3318201-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" One comment style is not aligned with the rest. Fix that. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-c= y8c95x0.c index f03775341b60..96e34b9eba4a 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -502,7 +502,8 @@ static int cy8c95x0_regmap_update_bits_base(struct cy8c= 95x0_pinctrl *chip, if (ret < 0) return ret; =20 - /* Mimic what hardware does and update the cache when a WC bit is written. + /* + * Mimic what hardware does and update the cache when a WC bit is written. * Allows to mark the registers as non-volatile and reduces I/O cycles. */ if (cy8c95x0_wc_register(reg) && (mask & val)) { --=20 2.43.0.rc1.1336.g36b5255a03ac