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Wysocki" , Mika Westerberg , Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Palmer Dabbelt , Paul Walmsley , Len Brown , Sunil V L , Rahul Pathak , Leyfoon Tan , Atish Patra , Andrew Jones , Samuel Holland , Anup Patel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [RFC PATCH v2 02/17] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Date: Mon, 3 Feb 2025 14:18:51 +0530 Message-ID: <20250203084906.681418-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250203084906.681418-1-apatel@ventanamicro.com> References: <20250203084906.681418-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for the common RISC-V Platform Management Interface (RPMI) shared memory transport as a mailbox controller. Signed-off-by: Anup Patel --- .../mailbox/riscv,rpmi-shmem-mbox.yaml | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/riscv,rpmi-sh= mem-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbo= x.yaml b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.ya= ml new file mode 100644 index 000000000000..c339df5d9e24 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/riscv,rpmi-shmem-mbox.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/riscv,rpmi-shmem-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Platform Management Interface (RPMI) shared memory mailbox + +maintainers: + - Anup Patel + +description: | + The RISC-V Platform Management Interface (RPMI) [1] defines a common sha= red + memory based RPMI transport. This RPMI shared memory transport integrate= s as + mailbox controller in the SBI implementation or supervisor software wher= eas + each RPMI service group is mailbox client in the SBI implementation and + supervisor software. + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + References + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + [1] RISC-V Platform Management Interface (RPMI) + https://github.com/riscv-non-isa/riscv-rpmi/releases + +properties: + compatible: + const: riscv,rpmi-shmem-mbox + + reg: + oneOf: + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - description: A2P doorbell address + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: P2A request queue base address + - description: A2P acknowledgment queue base address + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + - description: A2P doorbell address + - items: + - description: A2P request queue base address + - description: P2A acknowledgment queue base address + + reg-names: + oneOf: + - items: + - const: a2p-req + - const: p2a-ack + - const: p2a-req + - const: a2p-ack + - const: doorbell + - items: + - const: a2p-req + - const: p2a-ack + - const: p2a-req + - const: a2p-ack + - items: + - const: a2p-req + - const: p2a-ack + - const: doorbell + - items: + - const: a2p-req + - const: p2a-ack + + interrupts: + maxItems: 1 + description: + The RPMI shared memory transport supports wired interrupt specified = by + this property as the P2A doorbell. + + msi-parent: + description: + The RPMI shared memory transport supports MSI as P2A doorbell and th= is + property specifies the target MSI controller. + + riscv,slot-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + description: + Power-of-2 RPMI slot size of the RPMI shared memory transport. + + riscv,doorbell-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0xffffffff + description: + Update only the register bits of doorbell defined by the mask (32 bi= t). + + riscv,doorbell-value: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x1 + description: + Value written to the doorbell register bits (32-bit access) specified + by the riscv,db-mask property. + + "#mbox-cells": + const: 1 + description: + The first cell specifies RPMI service group ID. + +required: + - compatible + - reg + - reg-names + - riscv,slot-size + - "#mbox-cells" + +anyOf: + - required: + - interrupts + - required: + - msi-parent + +additionalProperties: false + +examples: + - | + // Example 1 (RPMI shared memory with only 2 queues): + mailbox@10080000 { + compatible =3D "riscv,rpmi-shmem-mbox"; + reg =3D <0x10080000 0x10000>, + <0x10090000 0x10000>, + <0x100a0000 0x4>; + reg-names =3D "a2p-req", "p2a-ack", "doorbell"; + msi-parent =3D <&imsic_mlevel>; + riscv,slot-size =3D <64>; + #mbox-cells =3D <1>; + }; + - | + // Example 2 (RPMI shared memory with only 4 queues): + mailbox@10001000 { + compatible =3D "riscv,rpmi-shmem-mbox"; + reg =3D <0x10001000 0x800>, + <0x10001800 0x800>, + <0x10002000 0x800>, + <0x10002800 0x800>, + <0x10003000 0x4>; + reg-names =3D "a2p-req", "p2a-ack", "p2a-req", "a2p-ack", "doorbel= l"; + msi-parent =3D <&imsic_mlevel>; + riscv,slot-size =3D <64>; + riscv,doorbell-mask =3D <0x00008000>; + riscv,doorbell-value =3D <0x00008000>; + #mbox-cells =3D <1>; + }; --=20 2.43.0