From nobody Tue Feb 10 05:26:49 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B09341CD1E0; Sun, 2 Feb 2025 09:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738489024; cv=none; b=YnQynNfMm3BK6jjTe6QPZbqsqVQx1kX2ZkAdbLhtuaWHEkLG2Gs0H4aKcSqd7lZypxzGd+/rPw3EtQt10V682nf8Tx/YKpgxOrFVK4IdYzQ04pJC2C+s+UZRiNysmn5Ql/dMrq1GN/o3CDVKjNxqskneAX+uTv92mwg5Ki8AKfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738489024; c=relaxed/simple; bh=y2NbpMddv8E4OW5a/0B9zSB/pKJSS3Q71HivbITbEzA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OAkCVd6F99US26H2b3MZftI2/gIHFJHk9MofOaSS/GOCd85o/1U1vNk4DyTyAIYnj5uk4u9YUw/ekMo/58CkbnTtBQkADWWzRCrhfp5TLtEymvfdPlLTNtlIfjkeOaA62wTmfpmVN3ClibcQDjm3/qJTSONuwZjgdXRTvta8dVI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dxbdfuM0; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dxbdfuM0" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5129aisb2003156 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 2 Feb 2025 03:36:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1738489004; bh=uu6pwTr8um6zloS0puaTgLu6wot0WWHBiYu4ErKdFXc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dxbdfuM0NndDvVKMAJq4dotF6kRJ/azWZD3rTcKmu6G5bYJCgrA+urNdVW+OLqQg3 z6fkPrtA/bedclJ/wmfysmlo2ulE6tz8yCeDkfhS95ZDteG3U1oCSheXsxGWkTpAPJ nE8O3cGrecqpNSUMiGrKYSFJ3USwi6ZqHIPhbzZA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5129aifr019662 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 2 Feb 2025 03:36:44 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 2 Feb 2025 03:36:44 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 2 Feb 2025 03:36:44 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.104]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5129abbj119794; Sun, 2 Feb 2025 03:36:41 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j721e-evm: Add overlay for PCIe NTB functionality Date: Sun, 2 Feb 2025 15:06:28 +0530 Message-ID: <20250202093636.2699064-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250202093636.2699064-1-s-vadapalli@ti.com> References: <20250202093636.2699064-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" PCIe NTB (Non-Transparent-Bridge) allows connecting the memory of multiple PCIe Hosts (Root-Complex). The number of such hosts is determined by the number of PCIe instances configured for NTB operation on the device which intends to enable NTB functionality. Add a device-tree overlay to configure PCIE0 and PCIE1 instances of PCIe on J721E EVM for NTB operation. This shall allow connecting the memory of two PCIe Hosts via PCIE0 and PCIE1 on J721E EVM. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 4 + .../boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso | 91 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 8a4bdf87e2d4..1097ab30f5a9 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-common-proc-board-infotainment.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-gesi-exp-board.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie-ntb.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb @@ -201,6 +202,8 @@ k3-j7200-evm-pcie1-ep-dtbs :=3D k3-j7200-common-proc-bo= ard.dtb \ k3-j7200-evm-pcie1-ep.dtbo k3-j721e-common-proc-board-infotainment-dtbs :=3D k3-j721e-common-proc-boa= rd.dtb \ k3-j721e-common-proc-board-infotainment.dtbo +k3-j721e-evm-pcie-ntb-dtbs :=3D k3-j721e-common-proc-board.dtb \ + k3-j721e-evm-pcie-ntb.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721e-evm-pcie1-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ @@ -239,6 +242,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am69-sk-pcie0-ep.dtb \ k3-j7200-evm-pcie1-ep.dtb \ k3-j721e-common-proc-board-infotainment.dtb \ + k3-j721e-evm-pcie-ntb.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso new file mode 100644 index 000000000000..4601bc8cd52f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie-ntb.dtso @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling NTB functionality using PCIE0 and PCIE1 instanc= es of + * PCIe on the J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXC= PXEVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + epf_bus { + compatible =3D "pci-epf-bus"; + + ntb { + compatible =3D "pci-epf-ntb"; + epcs =3D <&pcie0_ep>, <&pcie1_ep>; + epc-names =3D "primary", "secondary"; + vendor-id =3D /bits/ 16 <0x104c>; + device-id =3D /bits/ 16 <0xb00d>; + num-mws =3D <4>; + mws-size =3D <0x100000>, <0x100000>, <0x100000>, <0x100000>; + }; + }; +}; + +&pcie0_rc { + status =3D "disabled"; +}; + +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible =3D "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <1>; + power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 239 1>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 240 1>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + }; +}; --=20 2.43.0