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charset="utf-8" Use the CCI register access helpers instead of regmap's. Signed-off-by: Laurentiu Palcu --- drivers/staging/media/max96712/max96712.c | 126 +++++++++------------- 1 file changed, 51 insertions(+), 75 deletions(-) diff --git a/drivers/staging/media/max96712/max96712.c b/drivers/staging/me= dia/max96712/max96712.c index 47842facec125..cf39f5243cd6d 100644 --- a/drivers/staging/media/max96712/max96712.c +++ b/drivers/staging/media/max96712/max96712.c @@ -12,24 +12,25 @@ #include #include =20 +#include #include #include #include =20 /* TOP_CTRL */ -#define MAX96712_DEBUG_EXTRA_REG 0x0009 +#define MAX96712_DEBUG_EXTRA_REG CCI_REG8(0x0009) #define DEBUG_EXTRA_PCLK_25MHZ 0x00 #define DEBUG_EXTRA_PCLK_75MHZ 0x01 -#define MAX96724_TOP_CTRL_PWR1 0x0013 +#define MAX96724_TOP_CTRL_PWR1 CCI_REG8(0x0013) #define RESET_ALL BIT(6) =20 /* BACKTOP0 */ -#define MAX96712_BACKTOP0_12 0x040b +#define MAX96712_BACKTOP0_12 CCI_REG8(0x040b) #define CSI_OUT_EN BIT(1) #define SOFT_BPP_0_MASK GENMASK(7, 3) #define SOFT_BPP_0_SHIFT 3 -#define MAX96712_BACKTOP0_22 0x0415 -#define MAX96712_BACKTOP0_25 0x0418 +#define MAX96712_BACKTOP0_22 CCI_REG8(0x0415) +#define MAX96712_BACKTOP0_25 CCI_REG8(0x0418) #define PHY_CSI_TX_DPLL_PREDEF_FREQ_MASK GENMASK(4, 0) #define PHY_CSI_TX_DPLL_PREDEF_FREQ_SHIFT 0 #define PHY_CSI_TX_DPLL_FB_FRACTION_PREDEF_EN BIT(5) @@ -37,7 +38,7 @@ #define OVERRIDE_BPP_VC_DT_1_3 BIT(7) =20 /* MIPI_PHY */ -#define MAX96712_MIPI_PHY_0 0x08a0 +#define MAX96712_MIPI_PHY_0 CCI_REG8(0x08a0) #define PHY_4X2 BIT(0) #define PHY_2X4 BIT(2) #define PHY_1X4A_22 BIT(3) @@ -45,7 +46,7 @@ #define FORCE_CLK0_EN BIT(5) #define FORCE_CLK3_EN BIT(6) #define FORCE_CSI_OUT_EN BIT(7) -#define MAX96712_MIPI_PHY_2 0x08a2 +#define MAX96712_MIPI_PHY_2 CCI_REG8(0x08a2) #define T_HS_TRAIL_MASK GENMASK(1, 0) #define T_HS_TRAIL_SHIFT 0 #define T_LPX_MASK GENMASK(3, 2) @@ -56,22 +57,22 @@ #define PHY1_EN BIT(5) #define PHY2_EN BIT(6) #define PHY3_EN BIT(7) -#define MAX96712_MIPI_PHY_3 0x08a3 +#define MAX96712_MIPI_PHY_3 CCI_REG8(0x08a3) #define PHY0_LANE_MAP_MASK GENMASK(3, 0) #define PHY0_LANE_MAP_SHIFT 0 #define PHY1_LANE_MAP_MASK GENMASK(7, 4) #define PHY1_LANE_MAP_SHIFT 4 -#define MAX96712_MIPI_PHY_5 0x08a5 +#define MAX96712_MIPI_PHY_5 CCI_REG8(0x08a5) #define PHY0_POL_MAP_MASK GENMASK(2, 0) #define PHY0_POL_MAP_SHIFT 0 #define PHY1_POL_MAP_MASK GENMASK(5, 3) #define PHY1_POL_MAP_SHIFT 3 #define T_CLK_PREP_MASK GENMASK(7, 6) #define T_CLK_PREP_SHIFT 6 -#define MAX96712_MIPI_PHY_13 0x08ad +#define MAX96712_MIPI_PHY_13 CCI_REG8(0x08ad) #define T_T3_PREBEGIN_MASK GENMASK(5, 0) #define T_T3_PREBEGIN_SHIFT 0 -#define MAX96712_MIPI_PHY_14 0x08ae +#define MAX96712_MIPI_PHY_14 CCI_REG8(0x08ae) #define T_T3_PREP_MASK GENMASK(1, 0) #define T_T3_PREP_SHIFT 0 #define T_T3_PREP_40NS 0 @@ -82,7 +83,7 @@ #define T_T3_POST_SHIFT 2 =20 /* MIPI_TX: 0 <=3D phy < 4 */ -#define MAX96712_MIPI_TX_10(phy) (0x090a + (phy) * 0x40) +#define MAX96712_MIPI_TX_10(phy) CCI_REG8(0x090a + (phy) * 0x40) #define CSI2_TWAKEUP_H_MASK GENMASK(2, 0) #define CSI2_TWAKEUP_H_SHIFT 0 #define CSI2_VCX_EN BIT(4) @@ -91,7 +92,7 @@ #define CSI2_LANE_CNT_SHIFT 6 =20 /* VRX_PATGEN */ -#define MAX96712_VRX_PATGEN_0 0x1050 +#define MAX96712_VRX_PATGEN_0 CCI_REG8(0x1050) #define VTG_MODE_MASK GENMASK(1, 0) #define VTG_MODE_SHIFT 0 #define VTG_MODE_VS_TRACKING 0 @@ -104,30 +105,30 @@ #define GEN_DE BIT(5) #define GEN_HS BIT(6) #define GEN_VS BIT(7) -#define MAX96712_VRX_PATGEN_1 0x1051 +#define MAX96712_VRX_PATGEN_1 CCI_REG8(0x1051) #define VS_TRIG BIT(0) #define PATGEN_MODE_MASK GENMASK(5, 4) #define PATGEN_MODE_SHIFT 4 #define PATGEN_MODE_CHECKERBOARD (1 << PATGEN_MODE_SHIFT) #define PATGEN_MODE_GRADIENT (2 << PATGEN_MODE_SHIFT) #define GRAD_MODE BIT(7) -#define MAX96712_VRX_PATGEN_VS_DLY 0x1052 -#define MAX96712_VRX_PATGEN_VS_HIGH 0x1055 -#define MAX96712_VRX_PATGEN_VS_LOW 0x1058 -#define MAX96712_VRX_PATGEN_V2H 0x105b -#define MAX96712_VRX_PATGEN_HS_HIGH 0x105e -#define MAX96712_VRX_PATGEN_HS_LOW 0x1060 -#define MAX96712_VRX_PATGEN_HS_CNT 0x1062 -#define MAX96712_VRX_PATGEN_V2D 0x1064 -#define MAX96712_VRX_PATGEN_DE_HIGH 0x1067 -#define MAX96712_VRX_PATGEN_DE_LOW 0x1069 -#define MAX96712_VRX_PATGEN_DE_CNT 0x106b -#define MAX96712_VRX_PATGEN_GRAD_INCR 0x106d -#define MAX96712_VRX_PATGEN_CHKR_COLOR_A 0x106e -#define MAX96712_VRX_PATGEN_CHKR_COLOR_B 0x1071 -#define MAX96712_VRX_PATGEN_CHKR_RPT_A 0x1074 -#define MAX96712_VRX_PATGEN_CHKR_RPT_B 0x1075 -#define MAX96712_VRX_PATGEN_CHKR_ALT 0x1076 +#define MAX96712_VRX_PATGEN_VS_DLY CCI_REG24(0x1052) +#define MAX96712_VRX_PATGEN_VS_HIGH CCI_REG24(0x1055) +#define MAX96712_VRX_PATGEN_VS_LOW CCI_REG24(0x1058) +#define MAX96712_VRX_PATGEN_V2H CCI_REG16(0x105b) +#define MAX96712_VRX_PATGEN_HS_HIGH CCI_REG16(0x105e) +#define MAX96712_VRX_PATGEN_HS_LOW CCI_REG16(0x1060) +#define MAX96712_VRX_PATGEN_HS_CNT CCI_REG16(0x1062) +#define MAX96712_VRX_PATGEN_V2D CCI_REG24(0x1064) +#define MAX96712_VRX_PATGEN_DE_HIGH CCI_REG16(0x1067) +#define MAX96712_VRX_PATGEN_DE_LOW CCI_REG16(0x1069) +#define MAX96712_VRX_PATGEN_DE_CNT CCI_REG16(0x106b) +#define MAX96712_VRX_PATGEN_GRAD_INCR CCI_REG8(0x106d) +#define MAX96712_VRX_PATGEN_CHKR_COLOR_A CCI_REG24(0x106e) +#define MAX96712_VRX_PATGEN_CHKR_COLOR_B CCI_REG24(0x1071) +#define MAX96712_VRX_PATGEN_CHKR_RPT_A CCI_REG8(0x1074) +#define MAX96712_VRX_PATGEN_CHKR_RPT_B CCI_REG8(0x1075) +#define MAX96712_VRX_PATGEN_CHKR_ALT CCI_REG8(0x1076) =20 enum max96712_pattern { MAX96712_PATTERN_CHECKERBOARD =3D 0, @@ -155,11 +156,11 @@ struct max96712_priv { enum max96712_pattern pattern; }; =20 -static int max96712_write(struct max96712_priv *priv, unsigned int reg, u8= val) +static int max96712_write(struct max96712_priv *priv, unsigned int reg, u6= 4 val) { int ret; =20 - ret =3D regmap_write(priv->regmap, reg, val); + ret =3D cci_write(priv->regmap, reg, val, NULL); if (ret) dev_err(&priv->client->dev, "write 0x%04x failed\n", reg); =20 @@ -167,42 +168,17 @@ static int max96712_write(struct max96712_priv *priv,= unsigned int reg, u8 val) } =20 static int max96712_update_bits(struct max96712_priv *priv, unsigned int r= eg, - u8 mask, u8 val) + u64 mask, u64 val) { int ret; =20 - ret =3D regmap_update_bits(priv->regmap, reg, mask, val); + ret =3D cci_update_bits(priv->regmap, reg, mask, val, NULL); if (ret) dev_err(&priv->client->dev, "update 0x%04x failed\n", reg); =20 return ret; } =20 -static int max96712_write_bulk(struct max96712_priv *priv, unsigned int re= g, - const void *val, size_t val_count) -{ - int ret; - - ret =3D regmap_bulk_write(priv->regmap, reg, val, val_count); - if (ret) - dev_err(&priv->client->dev, "bulk write 0x%04x failed\n", reg); - - return ret; -} - -static int max96712_write_bulk_value(struct max96712_priv *priv, - unsigned int reg, unsigned int val, - size_t val_count) -{ - unsigned int i; - u8 values[4]; - - for (i =3D 1; i <=3D val_count; i++) - values[i - 1] =3D (val >> ((val_count - i) * 8)) & 0xff; - - return max96712_write_bulk(priv, reg, &values, val_count); -} - static void max96712_reset(struct max96712_priv *priv) { max96712_update_bits(priv, MAX96724_TOP_CTRL_PWR1, RESET_ALL, RESET_ALL); @@ -293,19 +269,19 @@ static void max96712_pattern_enable(struct max96712_p= riv *priv, bool enable) max96712_write(priv, MAX96712_DEBUG_EXTRA_REG, DEBUG_EXTRA_PCLK_75MHZ); =20 /* Configure Video Timing Generator for 1920x1080 @ 30 fps. */ - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_VS_DLY, 0, 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_VS_HIGH, v_sw * h_tot= , 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_VS_LOW, - (v_active + v_fp + v_bp) * h_tot, 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_V2H, 0, 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_HS_HIGH, h_sw, 2); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_HS_LOW, h_active + h_= fp + h_bp, 2); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_HS_CNT, v_tot, 2); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_V2D, - h_tot * (v_sw + v_bp) + (h_sw + h_bp), 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_DE_HIGH, h_active, 2); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_DE_LOW, h_fp + h_sw += h_bp, 2); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_DE_CNT, v_active, 2); + max96712_write(priv, MAX96712_VRX_PATGEN_VS_DLY, 0); + max96712_write(priv, MAX96712_VRX_PATGEN_VS_HIGH, v_sw * h_tot); + max96712_write(priv, MAX96712_VRX_PATGEN_VS_LOW, + (v_active + v_fp + v_bp) * h_tot); + max96712_write(priv, MAX96712_VRX_PATGEN_V2H, 0); + max96712_write(priv, MAX96712_VRX_PATGEN_HS_HIGH, h_sw); + max96712_write(priv, MAX96712_VRX_PATGEN_HS_LOW, h_active + h_fp + h_bp); + max96712_write(priv, MAX96712_VRX_PATGEN_HS_CNT, v_tot); + max96712_write(priv, MAX96712_VRX_PATGEN_V2D, + h_tot * (v_sw + v_bp) + (h_sw + h_bp)); + max96712_write(priv, MAX96712_VRX_PATGEN_DE_HIGH, h_active); + max96712_write(priv, MAX96712_VRX_PATGEN_DE_LOW, h_fp + h_sw + h_bp); + max96712_write(priv, MAX96712_VRX_PATGEN_DE_CNT, v_active); =20 /* Generate VS, HS and DE in free-running mode. */ max96712_write(priv, MAX96712_VRX_PATGEN_0, @@ -320,8 +296,8 @@ static void max96712_pattern_enable(struct max96712_pri= v *priv, bool enable) max96712_write(priv, MAX96712_VRX_PATGEN_CHKR_ALT, 0x3c); =20 /* Set checkerboard pattern colors. */ - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_CHKR_COLOR_A, 0xfecc= 00, 3); - max96712_write_bulk_value(priv, MAX96712_VRX_PATGEN_CHKR_COLOR_B, 0x006a= a7, 3); + max96712_write(priv, MAX96712_VRX_PATGEN_CHKR_COLOR_A, 0xfecc00); + max96712_write(priv, MAX96712_VRX_PATGEN_CHKR_COLOR_B, 0x006aa7); =20 /* Generate checkerboard pattern. */ max96712_write(priv, MAX96712_VRX_PATGEN_1, PATGEN_MODE_CHECKERBOARD); --=20 2.44.1