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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBD.mail.protection.outlook.com (10.167.243.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8398.14 via Frontend Transport; Thu, 30 Jan 2025 19:49:30 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 30 Jan 2025 13:49:29 -0600 From: Yazen Ghannam Date: Thu, 30 Jan 2025 19:48:55 +0000 Subject: [PATCH v4 1/3] x86/amd_node, platform/x86/amd/hsmp: Have HSMP use SMN through AMD_NODE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250130-wip-x86-amd-nb-cleanup-v4-1-b5cc997e471b@amd.com> References: <20250130-wip-x86-amd-nb-cleanup-v4-0-b5cc997e471b@amd.com> In-Reply-To: <20250130-wip-x86-amd-nb-cleanup-v4-0-b5cc997e471b@amd.com> To: , Mario Limonciello , "Yazen Ghannam" , Suma Hegde , "Naveen Krishna Chatradhi" , Carlos Bilbao , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , X-Mailer: b4 0.15-dev-d23a9 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBD:EE_|LV8PR12MB9184:EE_ X-MS-Office365-Filtering-Correlation-Id: 8eb9ca76-7dda-4eee-245d-08dd41673612 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 19:49:30.0449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8eb9ca76-7dda-4eee-245d-08dd41673612 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9184 The HSMP interface is just an SMN interface with different offsets. Define an HSMP wrapper in the SMN code and have the HSMP platform driver use that rather than a local solution. Also, remove the "root" member from AMD_NB, since there are no more users of it. Signed-off-by: Yazen Ghannam Acked-by: Ilpo J=C3=A4rvinen Reviewed-by: Carlos Bilbao --- Notes: Link: https://lore.kernel.org/20241213152206.385573-1-yazen.ghannam@amd.com =20 v2.2->v4 * Was left out of v3 set. * Fix build issue for amd_smn_hsmp_rdwr(). =20 v2.1-v2.2: * Include for static_assert() =20 v2->v2.1: * Include static_assert() and comment for sysfs attributes. =20 v1->v2: * Rebase on recent HSMP rework. arch/x86/include/asm/amd_nb.h | 1 - arch/x86/include/asm/amd_node.h | 13 +++++++++++++ arch/x86/kernel/amd_nb.c | 1 - arch/x86/kernel/amd_node.c | 9 +++++++++ drivers/platform/x86/amd/hsmp/Kconfig | 2 +- drivers/platform/x86/amd/hsmp/acpi.c | 7 ++++--- drivers/platform/x86/amd/hsmp/hsmp.c | 1 - drivers/platform/x86/amd/hsmp/hsmp.h | 3 --- drivers/platform/x86/amd/hsmp/plat.c | 36 ++++++++++++-------------------= ---- 9 files changed, 39 insertions(+), 34 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 4c4efb93045e..adfa0854cf2d 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -27,7 +27,6 @@ struct amd_l3_cache { }; =20 struct amd_northbridge { - struct pci_dev *root; struct pci_dev *misc; struct pci_dev *link; struct amd_l3_cache l3_cache; diff --git a/arch/x86/include/asm/amd_node.h b/arch/x86/include/asm/amd_nod= e.h index 113ad3e8ee40..002c3afbd30f 100644 --- a/arch/x86/include/asm/amd_node.h +++ b/arch/x86/include/asm/amd_node.h @@ -30,7 +30,20 @@ static inline u16 amd_num_nodes(void) return topology_amd_nodes_per_pkg() * topology_max_packages(); } =20 +#ifdef CONFIG_AMD_NODE int __must_check amd_smn_read(u16 node, u32 address, u32 *value); int __must_check amd_smn_write(u16 node, u32 address, u32 value); =20 +/* Should only be used by the HSMP driver. */ +int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool= write); +#else +static inline int __must_check amd_smn_read(u16 node, u32 address, u32 *va= lue) { return -ENODEV; } +static inline int __must_check amd_smn_write(u16 node, u32 address, u32 va= lue) { return -ENODEV; } + +static inline int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u3= 2 *value, bool write) +{ + return -ENODEV; +} +#endif /* CONFIG_AMD_NODE */ + #endif /*_ASM_X86_AMD_NODE_H_*/ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 11fac09e3a8c..24d7a87edf9c 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -73,7 +73,6 @@ static int amd_cache_northbridges(void) amd_northbridges.nb =3D nb; =20 for (i =3D 0; i < amd_northbridges.num; i++) { - node_to_amd_nb(i)->root =3D amd_node_get_root(i); node_to_amd_nb(i)->misc =3D amd_node_get_func(i, 3); =20 /* diff --git a/arch/x86/kernel/amd_node.c b/arch/x86/kernel/amd_node.c index d2ec7fd555c5..65045f223c10 100644 --- a/arch/x86/kernel/amd_node.c +++ b/arch/x86/kernel/amd_node.c @@ -97,6 +97,9 @@ static DEFINE_MUTEX(smn_mutex); #define SMN_INDEX_OFFSET 0x60 #define SMN_DATA_OFFSET 0x64 =20 +#define HSMP_INDEX_OFFSET 0xc4 +#define HSMP_DATA_OFFSET 0xc8 + /* * SMN accesses may fail in ways that are difficult to detect here in the = called * functions amd_smn_read() and amd_smn_write(). Therefore, callers must do @@ -179,6 +182,12 @@ int __must_check amd_smn_write(u16 node, u32 address, = u32 value) } EXPORT_SYMBOL_GPL(amd_smn_write); =20 +int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool= write) +{ + return __amd_smn_rw(HSMP_INDEX_OFFSET, HSMP_DATA_OFFSET, node, address, v= alue, write); +} +EXPORT_SYMBOL_GPL(amd_smn_hsmp_rdwr); + static int amd_cache_roots(void) { u16 node, num_nodes =3D amd_num_nodes(); diff --git a/drivers/platform/x86/amd/hsmp/Kconfig b/drivers/platform/x86/a= md/hsmp/Kconfig index 7d10d4462a45..d6f7a62d55b5 100644 --- a/drivers/platform/x86/amd/hsmp/Kconfig +++ b/drivers/platform/x86/amd/hsmp/Kconfig @@ -7,7 +7,7 @@ config AMD_HSMP tristate =20 menu "AMD HSMP Driver" - depends on AMD_NB || COMPILE_TEST + depends on AMD_NODE || COMPILE_TEST =20 config AMD_HSMP_ACPI tristate "AMD HSMP ACPI device driver" diff --git a/drivers/platform/x86/amd/hsmp/acpi.c b/drivers/platform/x86/am= d/hsmp/acpi.c index 444b43be35a2..c1eccb3c80c5 100644 --- a/drivers/platform/x86/amd/hsmp/acpi.c +++ b/drivers/platform/x86/amd/hsmp/acpi.c @@ -10,7 +10,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include -#include =20 #include #include @@ -24,6 +23,8 @@ =20 #include =20 +#include + #include "hsmp.h" =20 #define DRIVER_NAME "amd_hsmp" @@ -321,8 +322,8 @@ static int hsmp_acpi_probe(struct platform_device *pdev) return -ENOMEM; =20 if (!hsmp_pdev->is_probed) { - hsmp_pdev->num_sockets =3D amd_nb_num(); - if (hsmp_pdev->num_sockets =3D=3D 0 || hsmp_pdev->num_sockets > MAX_AMD_= SOCKETS) + hsmp_pdev->num_sockets =3D amd_num_nodes(); + if (hsmp_pdev->num_sockets =3D=3D 0 || hsmp_pdev->num_sockets > MAX_AMD_= NUM_NODES) return -ENODEV; =20 hsmp_pdev->sock =3D devm_kcalloc(&pdev->dev, hsmp_pdev->num_sockets, diff --git a/drivers/platform/x86/amd/hsmp/hsmp.c b/drivers/platform/x86/am= d/hsmp/hsmp.c index 03164e30b3a5..a3ac09a90de4 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.c +++ b/drivers/platform/x86/amd/hsmp/hsmp.c @@ -8,7 +8,6 @@ */ =20 #include -#include =20 #include #include diff --git a/drivers/platform/x86/amd/hsmp/hsmp.h b/drivers/platform/x86/am= d/hsmp/hsmp.h index e852f0a947e4..af8b21f821d6 100644 --- a/drivers/platform/x86/amd/hsmp/hsmp.h +++ b/drivers/platform/x86/amd/hsmp/hsmp.h @@ -21,8 +21,6 @@ =20 #define HSMP_ATTR_GRP_NAME_SIZE 10 =20 -#define MAX_AMD_SOCKETS 8 - #define HSMP_CDEV_NAME "hsmp_cdev" #define HSMP_DEVNODE_NAME "hsmp" =20 @@ -41,7 +39,6 @@ struct hsmp_socket { void __iomem *virt_base_addr; struct semaphore hsmp_sem; char name[HSMP_ATTR_GRP_NAME_SIZE]; - struct pci_dev *root; struct device *dev; u16 sock_ind; int (*amd_hsmp_rdwr)(struct hsmp_socket *sock, u32 off, u32 *val, bool rw= ); diff --git a/drivers/platform/x86/amd/hsmp/plat.c b/drivers/platform/x86/am= d/hsmp/plat.c index 02ca85762b68..b9782a078dbd 100644 --- a/drivers/platform/x86/amd/hsmp/plat.c +++ b/drivers/platform/x86/amd/hsmp/plat.c @@ -10,14 +10,16 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include -#include =20 +#include #include #include #include #include #include =20 +#include + #include "hsmp.h" =20 #define DRIVER_NAME "amd_hsmp" @@ -34,28 +36,12 @@ #define SMN_HSMP_MSG_RESP 0x0010980 #define SMN_HSMP_MSG_DATA 0x00109E0 =20 -#define HSMP_INDEX_REG 0xc4 -#define HSMP_DATA_REG 0xc8 - static struct hsmp_plat_device *hsmp_pdev; =20 static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset, u32 *value, bool write) { - int ret; - - if (!sock->root) - return -ENODEV; - - ret =3D pci_write_config_dword(sock->root, HSMP_INDEX_REG, - sock->mbinfo.base_addr + offset); - if (ret) - return ret; - - ret =3D (write ? pci_write_config_dword(sock->root, HSMP_DATA_REG, *value) - : pci_read_config_dword(sock->root, HSMP_DATA_REG, value)); - - return ret; + return amd_smn_hsmp_rdwr(sock->sock_ind, sock->mbinfo.base_addr + offset,= value, write); } =20 static ssize_t hsmp_metric_tbl_plat_read(struct file *filp, struct kobject= *kobj, @@ -95,7 +81,12 @@ static umode_t hsmp_is_sock_attr_visible(struct kobject = *kobj, * Static array of 8 + 1(for NULL) elements is created below * to create sysfs groups for sockets. * is_bin_visible function is used to show / hide the necessary groups. + * + * Validate the maximum number against MAX_AMD_NUM_NODES. If this changes, + * then the attributes and groups below must be adjusted. */ +static_assert(MAX_AMD_NUM_NODES =3D=3D 8); + #define HSMP_BIN_ATTR(index, _list) \ static const struct bin_attribute attr##index =3D { \ .attr =3D { .name =3D HSMP_METRICS_TABLE_NAME, .mode =3D 0444}, \ @@ -159,10 +150,7 @@ static int init_platform_device(struct device *dev) int ret, i; =20 for (i =3D 0; i < hsmp_pdev->num_sockets; i++) { - if (!node_to_amd_nb(i)) - return -ENODEV; sock =3D &hsmp_pdev->sock[i]; - sock->root =3D node_to_amd_nb(i)->root; sock->sock_ind =3D i; sock->dev =3D dev; sock->mbinfo.base_addr =3D SMN_HSMP_BASE; @@ -305,11 +293,11 @@ static int __init hsmp_plt_init(void) return -ENOMEM; =20 /* - * amd_nb_num() returns number of SMN/DF interfaces present in the system + * amd_num_nodes() returns number of SMN/DF interfaces present in the sys= tem * if we have N SMN/DF interfaces that ideally means N sockets */ - hsmp_pdev->num_sockets =3D amd_nb_num(); - if (hsmp_pdev->num_sockets =3D=3D 0 || hsmp_pdev->num_sockets > MAX_AMD_S= OCKETS) + hsmp_pdev->num_sockets =3D amd_num_nodes(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 19:49:30.3574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 447f7ffd-a5dc-4565-5cc4-08dd4167364b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4362 From: Mario Limonciello Offsets 0x60 and 0x64 are used internally by kernel drivers that call the amd_smn_read() and amd_smn_write() functions. If userspace accesses the regions at the same time as the kernel it may cause malfunctions in drivers using the offsets. Add these offsets to the exclusions so that the kernel is tainted if a non locked down userspace tries to access them. Signed-off-by: Mario Limonciello Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/20241206161210.163701-16-yazen.ghannam@amd.com =20 v2->v4: * Was left out of v3. * No change. =20 v1->v2: * No change. arch/x86/kernel/amd_node.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/x86/kernel/amd_node.c b/arch/x86/kernel/amd_node.c index 65045f223c10..ac571948cb35 100644 --- a/arch/x86/kernel/amd_node.c +++ b/arch/x86/kernel/amd_node.c @@ -93,6 +93,7 @@ static struct pci_dev **amd_roots; =20 /* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); +static bool smn_exclusive; =20 #define SMN_INDEX_OFFSET 0x60 #define SMN_DATA_OFFSET 0x64 @@ -149,6 +150,9 @@ static int __amd_smn_rw(u8 i_off, u8 d_off, u16 node, u= 32 address, u32 *value, b if (!root) return err; =20 + if (!smn_exclusive) + return err; + guard(mutex)(&smn_mutex); =20 err =3D pci_write_config_dword(root, i_off, address); @@ -202,6 +206,39 @@ static int amd_cache_roots(void) return 0; } =20 +static int reserve_root_config_spaces(void) +{ + struct pci_dev *root =3D NULL; + struct pci_bus *bus =3D NULL; + + while ((bus =3D pci_find_next_bus(bus))) { + /* Root device is Device 0 Function 0 on each Primary Bus. */ + root =3D pci_get_slot(bus, 0); + if (!root) + continue; + + if (root->vendor !=3D PCI_VENDOR_ID_AMD && + root->vendor !=3D PCI_VENDOR_ID_HYGON) + continue; + + pci_dbg(root, "Reserving PCI config space\n"); + + /* + * There are a few SMN index/data pairs and other registers + * that shouldn't be accessed by user space. + * So reserve the entire PCI config space for simplicity rather + * than covering specific registers piecemeal. + */ + if (!pci_request_config_region_exclusive(root, 0, PCI_CFG_SPACE_SIZE, NU= LL)) { + pci_err(root, "Failed to reserve config space\n"); + return -EEXIST; + } + } + + smn_exclusive =3D true; + return 0; +} + static int __init amd_smn_init(void) { int err; @@ -218,6 +255,10 @@ static int __init amd_smn_init(void) if (err) return err; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN2PEPF00004FBD.mail.protection.outlook.com (10.167.243.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8398.14 via Frontend Transport; Thu, 30 Jan 2025 19:49:31 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 30 Jan 2025 13:49:30 -0600 From: Yazen Ghannam Date: Thu, 30 Jan 2025 19:48:57 +0000 Subject: [PATCH v4 3/3] x86/amd_node: Add support for debugfs access to SMN registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250130-wip-x86-amd-nb-cleanup-v4-3-b5cc997e471b@amd.com> References: <20250130-wip-x86-amd-nb-cleanup-v4-0-b5cc997e471b@amd.com> In-Reply-To: <20250130-wip-x86-amd-nb-cleanup-v4-0-b5cc997e471b@amd.com> To: , Mario Limonciello , "Yazen Ghannam" , Suma Hegde , "Naveen Krishna Chatradhi" , Carlos Bilbao , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: , X-Mailer: b4 0.15-dev-d23a9 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBD:EE_|SA0PR12MB7004:EE_ X-MS-Office365-Filtering-Correlation-Id: 80691a9b-99e1-43c6-90ee-08dd416736e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 19:49:31.3886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80691a9b-99e1-43c6-90ee-08dd416736e1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7004 From: Mario Limonciello There are certain registers on AMD Zen systems that can only be accessed through SMN. Introduce a new interface that provides debugfs files for accessing SMN. As this introduces the capability for userspace to manipulate the hardware in unpredictable ways, taint the kernel when writing. Include a kernel parameter to enable the debugfs interface. This is intentionally left undocumented to discourage use of the interface. Signed-off-by: Mario Limonciello Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/20241206161210.163701-17-yazen.ghannam@amd.com =20 v2->v4: * Was left out of v3. * No change. =20 v1->v2: * Use TAINT_CPU_OUT_OF_SPEC. * Add parameter to enable debugfs interface. * Validate node input from user. arch/x86/kernel/amd_node.c | 99 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/arch/x86/kernel/amd_node.c b/arch/x86/kernel/amd_node.c index ac571948cb35..b670fa85c61b 100644 --- a/arch/x86/kernel/amd_node.c +++ b/arch/x86/kernel/amd_node.c @@ -8,6 +8,7 @@ * Author: Yazen Ghannam */ =20 +#include #include =20 /* @@ -192,6 +193,87 @@ int __must_check amd_smn_hsmp_rdwr(u16 node, u32 addre= ss, u32 *value, bool write } EXPORT_SYMBOL_GPL(amd_smn_hsmp_rdwr); =20 +static struct dentry *debugfs_dir; +static u16 debug_node; +static u32 debug_address; + +static ssize_t smn_node_write(struct file *file, const char __user *userbu= f, + size_t count, loff_t *ppos) +{ + u16 node; + int ret; + + ret =3D kstrtou16_from_user(userbuf, count, 0, &node); + if (ret) + return ret; + + if (node >=3D amd_num_nodes()) + return -ENODEV; + + debug_node =3D node; + return count; +} + +static int smn_node_show(struct seq_file *m, void *v) +{ + seq_printf(m, "0x%08x\n", debug_node); + return 0; +} + +static ssize_t smn_address_write(struct file *file, const char __user *use= rbuf, + size_t count, loff_t *ppos) +{ + int ret; + + ret =3D kstrtouint_from_user(userbuf, count, 0, &debug_address); + if (ret) + return ret; + + return count; +} + +static int smn_address_show(struct seq_file *m, void *v) +{ + seq_printf(m, "0x%08x\n", debug_address); + return 0; +} + +static int smn_value_show(struct seq_file *m, void *v) +{ + u32 val; + int ret; + + ret =3D amd_smn_read(debug_node, debug_address, &val); + if (ret) + return ret; + + seq_printf(m, "0x%08x\n", val); + return 0; +} + +static ssize_t smn_value_write(struct file *file, const char __user *userb= uf, + size_t count, loff_t *ppos) +{ + u32 val; + int ret; + + ret =3D kstrtouint_from_user(userbuf, count, 0, &val); + if (ret) + return ret; + + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + + ret =3D amd_smn_write(debug_node, debug_address, val); + if (ret) + return ret; + + return count; +} + +DEFINE_SHOW_STORE_ATTRIBUTE(smn_node); +DEFINE_SHOW_STORE_ATTRIBUTE(smn_address); +DEFINE_SHOW_STORE_ATTRIBUTE(smn_value); + static int amd_cache_roots(void) { u16 node, num_nodes =3D amd_num_nodes(); @@ -239,6 +321,15 @@ static int reserve_root_config_spaces(void) return 0; } =20 +static bool enable_dfs; + +static int __init amd_smn_enable_dfs(char *str) +{ + enable_dfs =3D true; + return 1; +} +__setup("amd_smn_debugfs_enable", amd_smn_enable_dfs); + static int __init amd_smn_init(void) { int err; @@ -259,6 +350,14 @@ static int __init amd_smn_init(void) if (err) return err; =20 + if (enable_dfs) { + debugfs_dir =3D debugfs_create_dir("amd_smn", arch_debugfs_dir); + + debugfs_create_file("node", 0600, debugfs_dir, NULL, &smn_node_fops); + debugfs_create_file("address", 0600, debugfs_dir, NULL, &smn_address_fop= s); + debugfs_create_file("value", 0600, debugfs_dir, NULL, &smn_value_fops); + } + return 0; } =20 --=20 2.43.0