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Thu, 30 Jan 2025 03:08:49 -0800 (PST) From: Esteban Blanc Date: Thu, 30 Jan 2025 12:08:25 +0100 Subject: [PATCH v3 1/6] dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250130-eblanc-ad4630_v1-v3-1-052e8c2d897d@baylibre.com> References: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> In-Reply-To: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Esteban Blanc , Conor Dooley X-Mailer: b4 0.14.2 This adds a binding specification for the Analog Devices Inc. AD4030, AD4630 and AD4632 families of ADCs. - ad4030-24 is a 1 channel SAR ADC with 24 bits of precision and a sampling rate of 2M samples per second - ad4032-24 is a 1 channel SAR ADC with 24 bits of precision and a sampling rate of 500K samples per second - ad4630-16 is a 2 channels SAR ADC with 16 bits of precision and a sampling rate of 2M samples per second - ad4630-24 is a 2 channels SAR ADC with 24 bits of precision and a sampling rate of 2M samples per second - ad4632-16 is a 2 channels SAR ADC with 16 bits of precision and a sampling rate of 500K samples per second - ad4632-24 is a 2 channels SAR ADC with 24 bits of precision and a sampling rate of 500K samples per second Reviewed-by: Conor Dooley Signed-off-by: Esteban Blanc --- .../devicetree/bindings/iio/adc/adi,ad4030.yaml | 111 +++++++++++++++++= ++++ MAINTAINERS | 9 ++ 2 files changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml new file mode 100644 index 0000000000000000000000000000000000000000..cef2dc1eefb9126f836794c742b= 9e471a847296a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +# Copyright 2024 BayLibre, SAS. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4030 and AD4630 ADC families + +maintainers: + - Michael Hennerich + - Nuno Sa + +description: | + Analog Devices AD4030 single channel and AD4630/AD4632 dual channel prec= ision + SAR ADC families + + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4030-24-4032-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf + +properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + - adi,ad4630-16 + - adi,ad4630-24 + - adi,ad4632-16 + - adi,ad4632-24 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 102040816 + + spi-rx-bus-width: + enum: [1, 2, 4] + + vdd-5v-supply: true + vdd-1v8-supply: true + vio-supply: true + + ref-supply: + description: + Optional External unbuffered reference. Used when refin-supply is not + connected. + + refin-supply: + description: + Internal buffered Reference. Used when ref-supply is not connected. + + cnv-gpios: + description: + The Convert Input (CNV). It initiates the sampling conversions. + maxItems: 1 + + reset-gpios: + description: + The Reset Input (/RST). Used for asynchronous device reset. + maxItems: 1 + + interrupts: + description: + The BUSY pin is used to signal that the conversions results are avai= lable + to be transferred when in SPI Clocking Mode. This nodes should be + connected to an interrupt that is triggered when the BUSY line goes = low. + maxItems: 1 + + interrupt-names: + const: busy + +required: + - compatible + - reg + - vdd-5v-supply + - vdd-1v8-supply + - vio-supply + - cnv-gpios + +oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4030-24"; + reg =3D <0>; + spi-max-frequency =3D <80000000>; + vdd-5v-supply =3D <&supply_5V>; + vdd-1v8-supply =3D <&supply_1_8V>; + vio-supply =3D <&supply_1_8V>; + ref-supply =3D <&supply_5V>; + cnv-gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index 0fa7c5728f1e64d031f4a47b6fce1db484ce0fc2..01e76f76b051b566b0aed480116= 21e170f192a2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1273,6 +1273,15 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad4= 000.yaml F: Documentation/iio/ad4000.rst F: drivers/iio/adc/ad4000.c =20 +AD4030 ADC DRIVER (AD4030-24/AD4630-16/AD4630-24/AD4632-16/AD4632-24) +M: Michael Hennerich +M: Nuno S=C3=A1 +R: Esteban Blanc +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml + ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav L: linux-iio@vger.kernel.org --=20 2.47.2 From nobody Sat May 9 05:34:59 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CA4A1C1F07 for ; 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AD4030-24 ADC. The driver implements basic support for the AD4030-24 1 channel differential ADC with hardware gain and offset control. Signed-off-by: Esteban Blanc --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 14 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4030.c | 934 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 950 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 01e76f76b051b566b0aed48011621e170f192a2b..9571a917b0437a802190101c0a8= 3bba9bf790ffc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1281,6 +1281,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +F: drivers/iio/adc/ad4030.c =20 ANALOG DEVICES INC AD4130 DRIVER M: Cosmin Tanislav diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 849c90203071a77ec7d94cec06d4378ece44440b..9677343a3269db6405dfdd4e938= 423806c891b47 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -33,6 +33,20 @@ config AD4000 To compile this driver as a module, choose M here: the module will be called ad4000. =20 +config AD4030 + tristate "Analog Devices AD4030 ADC Driver" + depends on SPI + depends on GPIOLIB + select REGMAP + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + Say yes here to build support for Analog Devices AD4030 and AD4630 high= speed + SPI analog to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4030. + config AD4130 tristate "Analog Device AD4130 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index ee19afba62b7fe0a68309c16f3581d98c5b8f653..326536bb672da3d6229b66af138= 74d122b2f7b94 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_AB8500_GPADC) +=3D ab8500-gpadc.o obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o obj-$(CONFIG_AD4000) +=3D ad4000.o +obj-$(CONFIG_AD4030) +=3D ad4030.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD7091R) +=3D ad7091r-base.o diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c new file mode 100644 index 0000000000000000000000000000000000000000..e06424b7f2590d28a57943949b0= 70cd7e185fbb7 --- /dev/null +++ b/drivers/iio/adc/ad4030.c @@ -0,0 +1,934 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD4030 and AD4630 ADC family driver. + * + * Copyright 2024 Analog Devices, Inc. + * Copyright 2024 BayLibre, SAS + * + * based on code from: + * Analog Devices, Inc. + * Sergiu Cuciurean + * Nuno Sa + * Marcelo Schmitt + * Liviu Adace + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD4030_REG_INTERFACE_CONFIG_A 0x00 +#define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7)) +#define AD4030_REG_INTERFACE_CONFIG_B 0x01 +#define AD4030_REG_DEVICE_CONFIG 0x02 +#define AD4030_REG_CHIP_TYPE 0x03 +#define AD4030_REG_PRODUCT_ID_L 0x04 +#define AD4030_REG_PRODUCT_ID_H 0x05 +#define AD4030_REG_CHIP_GRADE 0x06 +#define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10 +#define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) +#define AD4030_REG_SCRATCH_PAD 0x0A +#define AD4030_REG_SPI_REVISION 0x0B +#define AD4030_REG_VENDOR_L 0x0C +#define AD4030_REG_VENDOR_H 0x0D +#define AD4030_REG_STREAM_MODE 0x0E +#define AD4030_REG_INTERFACE_CONFIG_C 0x10 +#define AD4030_REG_INTERFACE_STATUS_A 0x11 +#define AD4030_REG_EXIT_CFG_MODE 0x14 +#define AD4030_REG_EXIT_CFG_MODE_EXIT_MSK BIT(0) +#define AD4030_REG_AVG 0x15 +#define AD4030_REG_AVG_MASK_AVG_SYNC BIT(7) +#define AD4030_REG_AVG_MASK_AVG_VAL GENMASK(4, 0) +#define AD4030_REG_OFFSET_X0_0 0x16 +#define AD4030_REG_OFFSET_X0_1 0x17 +#define AD4030_REG_OFFSET_X0_2 0x18 +#define AD4030_REG_OFFSET_X1_0 0x19 +#define AD4030_REG_OFFSET_X1_1 0x1A +#define AD4030_REG_OFFSET_X1_2 0x1B +#define AD4030_REG_OFFSET_BYTES_NB 3 +#define AD4030_REG_OFFSET_CHAN(ch) (AD4030_REG_OFFSET_X0_2 + \ + (AD4030_REG_OFFSET_BYTES_NB * \ + (ch))) +#define AD4030_REG_GAIN_X0_LSB 0x1C +#define AD4030_REG_GAIN_X0_MSB 0x1D +#define AD4030_REG_GAIN_X1_LSB 0x1E +#define AD4030_REG_GAIN_X1_MSB 0x1F +#define AD4030_REG_GAIN_MAX_GAIN 1999970 +#define AD4030_REG_GAIN_BYTES_NB 2 +#define AD4030_REG_GAIN_CHAN(ch) (AD4030_REG_GAIN_X0_MSB + \ + (AD4030_REG_GAIN_BYTES_NB * \ + (ch))) +#define AD4030_REG_MODES 0x20 +#define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0) +#define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6) +#define AD4030_REG_OSCILATOR 0x21 +#define AD4030_REG_IO 0x22 +#define AD4030_REG_IO_MASK_IO2X BIT(1) +#define AD4030_REG_PAT0 0x23 +#define AD4030_REG_PAT1 0x24 +#define AD4030_REG_PAT2 0x25 +#define AD4030_REG_PAT3 0x26 +#define AD4030_REG_DIG_DIAG 0x34 +#define AD4030_REG_DIG_ERR 0x35 + +/* Sequence starting with "1 0 1" to enable reg access */ +#define AD4030_REG_ACCESS 0xA0 + +#define AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED BITS_TO_BYTES(64) +#define AD4030_MAX_HARDWARE_CHANNEL_NB 2 +#define AD4030_MAX_IIO_CHANNEL_NB 5 +#define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK 0b10 +#define AD4030_GAIN_MIDLE_POINT 0x8000 +/* + * This accounts for 1 sample per channel plus one s64 for the timestamp, + * aligned on a s64 boundary + */ +#define AD4030_MAXIMUM_RX_BUFFER_SIZE \ + (ALIGN(AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED * \ + AD4030_MAX_HARDWARE_CHANNEL_NB, \ + sizeof(s64)) + sizeof(s64)) + +#define AD4030_VREF_MIN_UV (4096 * MILLI) +#define AD4030_VREF_MAX_UV (5000 * MILLI) +#define AD4030_VIO_THRESHOLD_UV (1400 * MILLI) +#define AD4030_SPI_MAX_XFER_LEN 8 +#define AD4030_SPI_MAX_REG_XFER_SPEED (80 * MEGA) +#define AD4030_TCNVH_NS 10 +#define AD4030_TCNVL_NS 20 +#define AD4030_TCYC_NS 500 +#define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS) +#define AD4030_TRESET_PW_NS 50 + +enum ad4030_out_mode { + AD4030_OUT_DATA_MD_DIFF, + AD4030_OUT_DATA_MD_16_DIFF_8_COM, + AD4030_OUT_DATA_MD_24_DIFF_8_COM, + AD4030_OUT_DATA_MD_30_AVERAGED_DIFF, + AD4030_OUT_DATA_MD_32_PATTERN +}; + +struct ad4030_chip_info { + const char *name; + const unsigned long *available_masks; + const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; + u8 grade; + u8 precision_bits; + /* Number of hardware channels */ + int num_voltage_inputs; + unsigned int tcyc_ns; +}; + +struct ad4030_state { + struct spi_device *spi; + struct regmap *regmap; + const struct ad4030_chip_info *chip; + struct gpio_desc *cnv_gpio; + int vref_uv; + int vio_uv; + int offset_avail[3]; + enum ad4030_out_mode mode; + + /* + * DMA (thus cache coherency maintenance) requires the transfer buffers + * to live in their own cache lines. + */ + u8 tx_data[AD4030_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN); + union { + u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE]; + struct { + s32 diff; + u8 common; + }; + } rx_data; +}; + +/* + * For a chip with 2 hardware channel this will be used to create 2 common= -mode + * channels: + * - voltage4 + * - voltage5 + * As the common-mode channels are after the differential ones, we compute= the + * channel number like this: + * - _idx is the scan_index (the order in the output buffer) + * - _ch is the hardware channel number this common-mode channel is related + * - _idx - _ch gives us the number of channel in the chip + * - _idx - _ch * 2 is the starting number of the common-mode channels, si= nce + * for each differential channel there is a common-mode channel + * - _idx - _ch * 2 + _ch gives the channel number for this specific commo= n-mode + * channel + */ +#define AD4030_CHAN_CMO(_idx, _ch) { \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .address =3D (_ch), \ + .channel =3D ((_idx) - (_ch)) * 2 + (_ch), \ + .scan_index =3D (_idx), \ + .scan_type =3D { \ + .sign =3D 'u', \ + .storagebits =3D 8, \ + .realbits =3D 8, \ + .endianness =3D IIO_BE, \ + }, \ +} + +/* + * For a chip with 2 hardware channel this will be used to create 2 differ= ential + * channels: + * - voltage0-voltage1 + * - voltage2-voltage3 + */ +#define AD4030_CHAN_DIFF(_idx, _storage, _real, _shift) { \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_CALIBSCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_CALIBSCALE), \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .address =3D (_idx), \ + .channel =3D (_idx) * 2, \ + .channel2 =3D (_idx) * 2 + 1, \ + .scan_index =3D (_idx), \ + .differential =3D true, \ + .scan_type =3D { \ + .sign =3D 's', \ + .storagebits =3D _storage, \ + .realbits =3D _real, \ + .shift =3D _shift, \ + .endianness =3D IIO_BE, \ + }, \ +} + +static int ad4030_enter_config_mode(struct ad4030_state *st) +{ + st->tx_data[0] =3D AD4030_REG_ACCESS; + + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .bits_per_word =3D 8, + .len =3D 1, + .speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED, + }; + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad4030_exit_config_mode(struct ad4030_state *st) +{ + st->tx_data[0] =3D 0; + st->tx_data[1] =3D AD4030_REG_EXIT_CFG_MODE; + st->tx_data[2] =3D AD4030_REG_EXIT_CFG_MODE_EXIT_MSK; + + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .bits_per_word =3D 8, + .len =3D 3, + .speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED, + }; + + return spi_sync_transfer(st->spi, &xfer, 1); +} + +static int ad4030_spi_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + int ret; + struct ad4030_state *st =3D context; + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .rx_buf =3D st->rx_data.raw, + .bits_per_word =3D 8, + .len =3D reg_size + val_size, + .speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED, + }; + + if (xfer.len > ARRAY_SIZE(st->tx_data) || + xfer.len > ARRAY_SIZE(st->rx_data.raw)) + return -EINVAL; + + ret =3D ad4030_enter_config_mode(st); + if (ret) + return ret; + + memset(st->tx_data, 0, ARRAY_SIZE(st->tx_data)); + memcpy(st->tx_data, reg, reg_size); + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + return ret; + + memcpy(val, &st->rx_data.raw[reg_size], val_size); + + return ad4030_exit_config_mode(st); +} + +static int ad4030_spi_write(void *context, const void *data, size_t count) +{ + int ret; + struct ad4030_state *st =3D context; + bool is_reset =3D count >=3D 3 && + ((u8 *)data)[0] =3D=3D 0 && + ((u8 *)data)[1] =3D=3D 0 && + ((u8 *)data)[2] =3D=3D 0x81; + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .bits_per_word =3D 8, + .len =3D count, + .speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED, + }; + + if (count > ARRAY_SIZE(st->tx_data)) + return -EINVAL; + + ret =3D ad4030_enter_config_mode(st); + if (ret) + return ret; + + memcpy(st->tx_data, data, count); + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + return ret; + + /* + * From datasheet: "After a [...] reset, no SPI commands or conversions + * can be started for 750us" + * After a reset we are in conversion mode, no need to exit config mode + */ + if (is_reset) { + fsleep(750); + return 0; + } + + return ad4030_exit_config_mode(st); +} + +static const struct regmap_bus ad4030_regmap_bus =3D { + .read =3D ad4030_spi_read, + .write =3D ad4030_spi_write, + .reg_format_endian_default =3D REGMAP_ENDIAN_BIG, +}; + +static const struct regmap_range ad4030_regmap_rd_range[] =3D { + regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_A, AD4030_REG_CHIP_GRADE), + regmap_reg_range(AD4030_REG_SCRATCH_PAD, AD4030_REG_STREAM_MODE), + regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_C, + AD4030_REG_INTERFACE_STATUS_A), + regmap_reg_range(AD4030_REG_EXIT_CFG_MODE, AD4030_REG_PAT3), + regmap_reg_range(AD4030_REG_DIG_DIAG, AD4030_REG_DIG_ERR), +}; + +static const struct regmap_range ad4030_regmap_wr_range[] =3D { + regmap_reg_range(AD4030_REG_CHIP_TYPE, AD4030_REG_CHIP_GRADE), + regmap_reg_range(AD4030_REG_SPI_REVISION, AD4030_REG_VENDOR_H), +}; + +static const struct regmap_access_table ad4030_regmap_rd_table =3D { + .yes_ranges =3D ad4030_regmap_rd_range, + .n_yes_ranges =3D ARRAY_SIZE(ad4030_regmap_rd_range), +}; + +static const struct regmap_access_table ad4030_regmap_wr_table =3D { + .no_ranges =3D ad4030_regmap_wr_range, + .n_no_ranges =3D ARRAY_SIZE(ad4030_regmap_wr_range), +}; + +static const struct regmap_config ad4030_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .read_flag_mask =3D 0x80, + .rd_table =3D &ad4030_regmap_rd_table, + .wr_table =3D &ad4030_regmap_wr_table, + .max_register =3D AD4030_REG_DIG_ERR, +}; + +static int ad4030_get_chan_scale(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + if (chan->differential) { + *val =3D (st->vref_uv * 2) / MILLI; + *val2 =3D st->chip->precision_bits; + return IIO_VAL_FRACTIONAL_LOG2; + } + + *val =3D st->vref_uv / 256; + return IIO_VAL_INT; +} + +static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + u16 gain; + int ret; + + ret =3D regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address), + st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB); + if (ret) + return ret; + + gain =3D get_unaligned_be16(st->rx_data.raw); + + /* From datasheet: multiplied output =3D input =C3=97 gain word/0x8000 */ + *val =3D gain / AD4030_GAIN_MIDLE_POINT; + *val2 =3D mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO, + AD4030_GAIN_MIDLE_POINT); + + return IIO_VAL_INT_PLUS_NANO; +} + +/* Returns the offset where 1 LSB =3D (VREF/2^precision_bits - 1)/gain */ +static int ad4030_get_chan_calibbias(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D regmap_bulk_read(st->regmap, + AD4030_REG_OFFSET_CHAN(chan->address), + st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB); + if (ret) + return ret; + + switch (st->chip->precision_bits) { + case 16: + *val =3D sign_extend32(get_unaligned_be16(st->rx_data.raw), 15); + return IIO_VAL_INT; + + case 24: + *val =3D sign_extend32(get_unaligned_be24(st->rx_data.raw), 23); + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int gain_int, + int gain_frac) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + u64 gain; + + if (gain_int < 0 || gain_frac < 0) + return -EINVAL; + + gain =3D mul_u32_u32(gain_int, MICRO) + gain_frac; + + if (gain > AD4030_REG_GAIN_MAX_GAIN) + return -EINVAL; + + put_unaligned_be16(DIV_ROUND_CLOSEST_ULL(gain * AD4030_GAIN_MIDLE_POINT, + MICRO), + st->tx_data); + + return regmap_bulk_write(st->regmap, + AD4030_REG_GAIN_CHAN(chan->address), + st->tx_data, AD4030_REG_GAIN_BYTES_NB); +} + +static int ad4030_set_chan_calibbias(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int offset) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + if (offset < st->offset_avail[0] || offset > st->offset_avail[2]) + return -EINVAL; + + st->tx_data[2] =3D 0; + + switch (st->chip->precision_bits) { + case 16: + put_unaligned_be16(offset, st->tx_data); + break; + + case 24: + put_unaligned_be24(offset, st->tx_data); + break; + + default: + return -EINVAL; + } + + return regmap_bulk_write(st->regmap, + AD4030_REG_OFFSET_CHAN(chan->address), + st->tx_data, AD4030_REG_OFFSET_BYTES_NB); +} + +static bool ad4030_is_common_byte_asked(struct ad4030_state *st, + unsigned int mask) +{ + return mask & AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK; +} + +static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + if (ad4030_is_common_byte_asked(st, mask)) + st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; + else + st->mode =3D AD4030_OUT_DATA_MD_DIFF; + + return regmap_update_bits(st->regmap, AD4030_REG_MODES, + AD4030_REG_MODES_MASK_OUT_DATA_MODE, + st->mode); +} + +static int ad4030_conversion(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type scan_type =3D indio_dev->channels->scan_type; + unsigned char diff_realbytes =3D BITS_TO_BYTES(scan_type.realbits); + unsigned int bytes_to_read; + int ret; + + /* Number of bytes for one differential channel */ + bytes_to_read =3D diff_realbytes; + /* Add one byte if we are using a differential + common byte mode */ + bytes_to_read +=3D (st->mode =3D=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM || + st->mode =3D=3D AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0; + /* Mulitiply by the number of hardware channels */ + bytes_to_read *=3D st->chip->num_voltage_inputs; + + gpiod_set_value_cansleep(st->cnv_gpio, 1); + ndelay(AD4030_TCNVH_NS); + gpiod_set_value_cansleep(st->cnv_gpio, 0); + ndelay(st->chip->tcyc_ns); + + ret =3D spi_read(st->spi, st->rx_data.raw, bytes_to_read); + if (ret) + return ret; + + if (st->mode !=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM) + return 0; + + st->rx_data.common =3D st->rx_data.raw[diff_realbytes]; + + return 0; +} + +static int ad4030_single_conversion(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int *val) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad4030_set_mode(indio_dev, BIT(chan->scan_index)); + if (ret) + return ret; + + ret =3D ad4030_conversion(indio_dev); + if (ret) + return ret; + + if (chan->differential) + *val =3D st->rx_data.diff; + else + *val =3D st->rx_data.common; + + return IIO_VAL_INT; +} + +static irqreturn_t ad4030_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad4030_conversion(indio_dev); + if (ret) + goto out; + + iio_push_to_buffers_with_timestamp(indio_dev, st->rx_data.raw, + pf->timestamp); + +out: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static const int ad4030_gain_avail[3][2] =3D { + { 0, 0 }, + { 0, 30518 }, + { 1, 999969482 }, +}; + +static int ad4030_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, + const int **vals, int *type, + int *length, long mask) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_CALIBBIAS: + *vals =3D st->offset_avail; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + + case IIO_CHAN_INFO_CALIBSCALE: + *vals =3D (void *)ad4030_gain_avail; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; + + default: + return -EINVAL; + } +} + +static int ad4030_read_raw_dispatch(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + switch (info) { + case IIO_CHAN_INFO_RAW: + return ad4030_single_conversion(indio_dev, chan, val); + + case IIO_CHAN_INFO_CALIBSCALE: + return ad4030_get_chan_calibscale(indio_dev, chan, val, val2); + + case IIO_CHAN_INFO_CALIBBIAS: + return ad4030_get_chan_calibbias(indio_dev, chan, val); + + default: + return -EINVAL; + } +} + +static int ad4030_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + int ret; + + if (info =3D=3D IIO_CHAN_INFO_SCALE) + return ad4030_get_chan_scale(indio_dev, chan, val, val2); + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad4030_read_raw_dispatch(indio_dev, chan, val, val2, info); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static int ad4030_write_raw_dispatch(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long info) +{ + switch (info) { + case IIO_CHAN_INFO_CALIBSCALE: + return ad4030_set_chan_calibscale(indio_dev, chan, val, val2); + + case IIO_CHAN_INFO_CALIBBIAS: + if (val2 !=3D 0) + return -EINVAL; + return ad4030_set_chan_calibbias(indio_dev, chan, val); + + default: + return -EINVAL; + } +} + +static int ad4030_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long info) +{ + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D ad4030_write_raw_dispatch(indio_dev, chan, val, val2, info); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + const struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + if (readval) + ret =3D regmap_read(st->regmap, reg, readval); + else + ret =3D regmap_write(st->regmap, reg, writeval); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static int ad4030_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + char *label) +{ + if (chan->differential) + return sprintf(label, "differential%lu\n", chan->address); + return sprintf(label, "common-mode%lu\n", chan->address); +} + +static const struct iio_info ad4030_iio_info =3D { + .read_avail =3D ad4030_read_avail, + .read_raw =3D ad4030_read_raw, + .write_raw =3D ad4030_write_raw, + .debugfs_reg_access =3D ad4030_reg_access, + .read_label =3D ad4030_read_label, +}; + +static int ad4030_buffer_preenable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D ad4030_set_mode(indio_dev, *indio_dev->active_scan_mask); + if (ret) + return ret; + + return 0; +} + +static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops =3D { + .preenable =3D ad4030_buffer_preenable, +}; + +static int ad4030_regulators_get(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + static const char * const ids[] =3D { "vdd-5v", "vdd-1v8" }; + int ret; + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ids), ids); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable regulators\n"); + + st->vio_uv =3D devm_regulator_get_enable_read_voltage(dev, "vio"); + if (st->vio_uv < 0) + return dev_err_probe(dev, st->vio_uv, + "Failed to enable and read vio voltage\n"); + + st->vref_uv =3D devm_regulator_get_enable_read_voltage(dev, "ref"); + if (st->vref_uv < 0) { + if (st->vref_uv !=3D -ENODEV) + return dev_err_probe(dev, st->vref_uv, + "Failed to read ref voltage\n"); + + /* if not using optional REF, the internal REFIN must be used */ + st->vref_uv =3D devm_regulator_get_enable_read_voltage(dev, + "refin"); + if (st->vref_uv < 0) + return dev_err_probe(dev, st->vref_uv, + "Failed to read refin voltage\n"); + } + + return 0; +} + +static int ad4030_reset(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct gpio_desc *reset; + int ret; + + reset =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset)) + return dev_err_probe(dev, PTR_ERR(reset), + "Failed to get reset GPIO\n"); + + if (reset) { + ndelay(50); + gpiod_set_value_cansleep(reset, 0); + } else { + ret =3D regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A, + AD4030_REG_INTERFACE_CONFIG_A_SW_RESET); + if (ret) + return ret; + } + + return 0; +} + +static int ad4030_detect_chip_info(const struct ad4030_state *st) +{ + unsigned int grade; + int ret; + + ret =3D regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade); + if (ret) + return ret; + + grade =3D FIELD_GET(AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE, grade); + if (grade !=3D st->chip->grade) + dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade, + st->chip->name); + + return 0; +} + +static int ad4030_config(struct ad4030_state *st) +{ + st->offset_avail[0] =3D (int)BIT(st->chip->precision_bits - 1) * -1; + st->offset_avail[1] =3D 1; + st->offset_avail[2] =3D BIT(st->chip->precision_bits - 1) - 1; + + if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) + return regmap_write(st->regmap, AD4030_REG_IO, + AD4030_REG_IO_MASK_IO2X); + + return 0; +} + +static int ad4030_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad4030_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->spi =3D spi; + + st->regmap =3D devm_regmap_init(dev, &ad4030_regmap_bus, st, + &ad4030_regmap_config); + if (IS_ERR(st->regmap)) + dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + st->chip =3D spi_get_device_match_data(spi); + if (!st->chip) + return -EINVAL; + + ret =3D ad4030_regulators_get(st); + if (ret) + return ret; + + /* + * From datasheet: "Perform a reset no sooner than 3ms after the power + * supplies are valid and stable" + */ + fsleep(3000); + + ret =3D ad4030_reset(st); + if (ret) + return ret; + + ret =3D ad4030_detect_chip_info(st); + if (ret) + return ret; + + ret =3D ad4030_config(st); + if (ret) + return ret; + + st->cnv_gpio =3D devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW); + if (IS_ERR(st->cnv_gpio)) + return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), + "Failed to get cnv gpio\n"); + + /* + * One hardware channel is split in two software channels when using + * common byte mode. Add one more channel for the timestamp. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; + indio_dev->name =3D st->chip->name; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->info =3D &ad4030_iio_info; + indio_dev->channels =3D st->chip->channels; + indio_dev->available_scan_masks =3D st->chip->available_masks; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4030_trigger_handler, + &ad4030_buffer_setup_ops); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup triggered buffer\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static const unsigned long ad4030_channel_masks[] =3D { + /* Differential only */ + BIT(0), + /* Differential and common-mode voltage */ + GENMASK(1, 0), + 0, +}; + +static const struct ad4030_chip_info ad4030_24_chip_info =3D { + .name =3D "ad4030-24", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + AD4030_CHAN_DIFF(0, 32, 24, 8), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, + .precision_bits =3D 24, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, +}; 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Thu, 30 Jan 2025 03:08:51 -0800 (PST) Received: from [127.0.0.1] ([2a01:e0a:448:76e0:2c72:cd2d:79b2:82ff]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c102bb2sm1689225f8f.34.2025.01.30.03.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 03:08:50 -0800 (PST) From: Esteban Blanc Date: Thu, 30 Jan 2025 12:08:27 +0100 Subject: [PATCH v3 3/6] iio: adc: ad4030: add averaging support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250130-eblanc-ad4630_v1-v3-3-052e8c2d897d@baylibre.com> References: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> In-Reply-To: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Esteban Blanc X-Mailer: b4 0.14.2 This add support for the averaging mode of AD4030 using oversampling IIO attribute Signed-off-by: Esteban Blanc --- drivers/iio/adc/ad4030.c | 130 +++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 114 insertions(+), 16 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index e06424b7f2590d28a57943949b070cd7e185fbb7..ef76f077feb0b995938b7acdddf= 3d45c990ea8ef 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -114,6 +114,11 @@ enum ad4030_out_mode { AD4030_OUT_DATA_MD_32_PATTERN }; =20 +enum { + AD4030_SCAN_TYPE_NORMAL, + AD4030_SCAN_TYPE_AVG, +}; + struct ad4030_chip_info { const char *name; const unsigned long *available_masks; @@ -129,10 +134,12 @@ struct ad4030_state { struct spi_device *spi; struct regmap *regmap; const struct ad4030_chip_info *chip; + const struct iio_scan_type *current_scan_type; struct gpio_desc *cnv_gpio; int vref_uv; int vio_uv; int offset_avail[3]; + unsigned int avg_log2; enum ad4030_out_mode mode; =20 /* @@ -186,7 +193,11 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define AD4030_CHAN_DIFF(_idx, _storage, _real, _shift) { \ +#define AD4030_CHAN_DIFF(_idx, _scan_type) { \ + .info_mask_shared_by_all =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT(IIO_CHAN_INFO_CALIBBIAS) | \ @@ -200,15 +211,16 @@ struct ad4030_state { .channel2 =3D (_idx) * 2 + 1, \ .scan_index =3D (_idx), \ .differential =3D true, \ - .scan_type =3D { \ - .sign =3D 's', \ - .storagebits =3D _storage, \ - .realbits =3D _real, \ - .shift =3D _shift, \ - .endianness =3D IIO_BE, \ - }, \ + .has_ext_scan_type =3D 1, \ + .ext_scan_type =3D _scan_type, \ + .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +static const int ad4030_average_modes[] =3D { + 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, + 32768, 65536 +}; + static int ad4030_enter_config_mode(struct ad4030_state *st) { st->tx_data[0] =3D AD4030_REG_ACCESS; @@ -475,6 +487,27 @@ static int ad4030_set_chan_calibbias(struct iio_dev *i= ndio_dev, st->tx_data, AD4030_REG_OFFSET_BYTES_NB); } =20 +static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val) +{ + struct ad4030_state *st =3D iio_priv(dev); + unsigned int avg_log2 =3D ilog2(avg_val); + unsigned int last_avg_idx =3D ARRAY_SIZE(ad4030_average_modes) - 1; + int ret; + + if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx]) + return -EINVAL; + + ret =3D regmap_write(st->regmap, AD4030_REG_AVG, + AD4030_REG_AVG_MASK_AVG_SYNC | + FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2)); + if (ret) + return ret; + + st->avg_log2 =3D avg_log2; + + return 0; +} + static bool ad4030_is_common_byte_asked(struct ad4030_state *st, unsigned int mask) { @@ -485,11 +518,18 @@ static int ad4030_set_mode(struct iio_dev *indio_dev,= unsigned long mask) { struct ad4030_state *st =3D iio_priv(indio_dev); =20 - if (ad4030_is_common_byte_asked(st, mask)) + if (st->avg_log2 > 0) + st->mode =3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; + else if (ad4030_is_common_byte_asked(st, mask)) st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; else st->mode =3D AD4030_OUT_DATA_MD_DIFF; =20 + st->current_scan_type =3D iio_get_current_scan_type(indio_dev, + st->chip->channels); + if (IS_ERR(st->current_scan_type)) + return PTR_ERR(st->current_scan_type); + return regmap_update_bits(st->regmap, AD4030_REG_MODES, AD4030_REG_MODES_MASK_OUT_DATA_MODE, st->mode); @@ -498,9 +538,11 @@ static int ad4030_set_mode(struct iio_dev *indio_dev, = unsigned long mask) static int ad4030_conversion(struct iio_dev *indio_dev) { struct ad4030_state *st =3D iio_priv(indio_dev); - const struct iio_scan_type scan_type =3D indio_dev->channels->scan_type; - unsigned char diff_realbytes =3D BITS_TO_BYTES(scan_type.realbits); + unsigned char diff_realbytes =3D + BITS_TO_BYTES(st->current_scan_type->realbits); unsigned int bytes_to_read; + unsigned long cnv_nb =3D BIT(st->avg_log2); + unsigned int i; int ret; =20 /* Number of bytes for one differential channel */ @@ -511,10 +553,12 @@ static int ad4030_conversion(struct iio_dev *indio_de= v) /* Mulitiply by the number of hardware channels */ bytes_to_read *=3D st->chip->num_voltage_inputs; =20 - gpiod_set_value_cansleep(st->cnv_gpio, 1); - ndelay(AD4030_TCNVH_NS); - gpiod_set_value_cansleep(st->cnv_gpio, 0); - ndelay(st->chip->tcyc_ns); + for (i =3D 0; i < cnv_nb; i++) { + gpiod_set_value_cansleep(st->cnv_gpio, 1); + ndelay(AD4030_TCNVH_NS); + gpiod_set_value_cansleep(st->cnv_gpio, 0); + ndelay(st->chip->tcyc_ns); + } =20 ret =3D spi_read(st->spi, st->rx_data.raw, bytes_to_read); if (ret) @@ -594,6 +638,12 @@ static int ad4030_read_avail(struct iio_dev *indio_dev, *type =3D IIO_VAL_INT_PLUS_NANO; return IIO_AVAIL_RANGE; =20 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D ad4030_average_modes; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(ad4030_average_modes); + return IIO_AVAIL_LIST; + default: return -EINVAL; } @@ -603,6 +653,8 @@ static int ad4030_read_raw_dispatch(struct iio_dev *ind= io_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) { + struct ad4030_state *st =3D iio_priv(indio_dev); + switch (info) { case IIO_CHAN_INFO_RAW: return ad4030_single_conversion(indio_dev, chan, val); @@ -613,6 +665,10 @@ static int ad4030_read_raw_dispatch(struct iio_dev *in= dio_dev, case IIO_CHAN_INFO_CALIBBIAS: return ad4030_get_chan_calibbias(indio_dev, chan, val); =20 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D BIT(st->avg_log2); + return IIO_VAL_INT; + default: return -EINVAL; } @@ -651,6 +707,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *in= dio_dev, return -EINVAL; return ad4030_set_chan_calibbias(indio_dev, chan, val); =20 + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4030_set_avg_frame_len(indio_dev, val); + default: return -EINVAL; } @@ -702,12 +761,21 @@ static int ad4030_read_label(struct iio_dev *indio_de= v, return sprintf(label, "common-mode%lu\n", chan->address); } =20 +static int ad4030_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL; +} + static const struct iio_info ad4030_iio_info =3D { .read_avail =3D ad4030_read_avail, .read_raw =3D ad4030_read_raw, .write_raw =3D ad4030_write_raw, .debugfs_reg_access =3D ad4030_reg_access, .read_label =3D ad4030_read_label, + .get_current_scan_type =3D ad4030_get_current_scan_type, }; =20 static int ad4030_buffer_preenable(struct iio_dev *indio_dev) @@ -722,8 +790,21 @@ static int ad4030_buffer_preenable(struct iio_dev *ind= io_dev) return 0; } =20 +static bool ad4030_validate_scan_mask(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + + /* Asking for both common channels and averaging */ + if (st->avg_log2 && ad4030_is_common_byte_asked(st, *scan_mask)) + return false; + + return true; +} + static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops =3D { .preenable =3D ad4030_buffer_preenable, + .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 static int ad4030_regulators_get(struct ad4030_state *st) @@ -893,11 +974,28 @@ static const unsigned long ad4030_channel_masks[] =3D= { 0, }; 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Thu, 30 Jan 2025 03:08:52 -0800 (PST) Received: from [127.0.0.1] ([2a01:e0a:448:76e0:2c72:cd2d:79b2:82ff]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c102bb2sm1689225f8f.34.2025.01.30.03.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 03:08:51 -0800 (PST) From: Esteban Blanc Date: Thu, 30 Jan 2025 12:08:28 +0100 Subject: [PATCH v3 4/6] iio: adc: ad4030: add support for ad4630-24 and ad4630-16 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250130-eblanc-ad4630_v1-v3-4-052e8c2d897d@baylibre.com> References: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> In-Reply-To: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Esteban Blanc X-Mailer: b4 0.14.2 AD4630-24 and AD4630-16 are 2 channels ADCs. Both channels are interleaved bit per bit on SDO line. Signed-off-by: Esteban Blanc --- drivers/iio/adc/ad4030.c | 188 +++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 178 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index ef76f077feb0b995938b7acdddf3d45c990ea8ef..45d99152d84aeb878c7554edfdc= 32d3a1295e9c4 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -33,6 +33,8 @@ #define AD4030_REG_PRODUCT_ID_H 0x05 #define AD4030_REG_CHIP_GRADE 0x06 #define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10 +#define AD4030_REG_CHIP_GRADE_AD4630_16_GRADE 0x03 +#define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -85,6 +87,7 @@ #define AD4030_MAX_HARDWARE_CHANNEL_NB 2 #define AD4030_MAX_IIO_CHANNEL_NB 5 #define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK 0b10 +#define AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK 0b1100 #define AD4030_GAIN_MIDLE_POINT 0x8000 /* * This accounts for 1 sample per channel plus one s64 for the timestamp, @@ -114,6 +117,13 @@ enum ad4030_out_mode { AD4030_OUT_DATA_MD_32_PATTERN }; =20 +enum { + AD4030_LANE_MD_1_PER_CH, + AD4030_LANE_MD_2_PER_CH, + AD4030_LANE_MD_4_PER_CH, + AD4030_LANE_MD_INTERLEAVED, +}; + enum { AD4030_SCAN_TYPE_NORMAL, AD4030_SCAN_TYPE_AVG, @@ -152,7 +162,11 @@ struct ad4030_state { struct { s32 diff; u8 common; - }; + } single; + struct { + s32 diff[2]; + u8 common[2]; + } dual; } rx_data; }; =20 @@ -511,19 +525,33 @@ static int ad4030_set_avg_frame_len(struct iio_dev *d= ev, int avg_val) static bool ad4030_is_common_byte_asked(struct ad4030_state *st, unsigned int mask) { - return mask & AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK; + return mask & (st->chip->num_voltage_inputs =3D=3D 1 ? + AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK : + AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK); } =20 static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask) { struct ad4030_state *st =3D iio_priv(indio_dev); =20 - if (st->avg_log2 > 0) + if (st->avg_log2 > 0) { st->mode =3D AD4030_OUT_DATA_MD_30_AVERAGED_DIFF; - else if (ad4030_is_common_byte_asked(st, mask)) - st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; - else + } else if (ad4030_is_common_byte_asked(st, mask)) { + switch (st->chip->precision_bits) { + case 16: + st->mode =3D AD4030_OUT_DATA_MD_16_DIFF_8_COM; + break; + + case 24: + st->mode =3D AD4030_OUT_DATA_MD_24_DIFF_8_COM; + break; + + default: + return -EINVAL; + } + } else { st->mode =3D AD4030_OUT_DATA_MD_DIFF; + } =20 st->current_scan_type =3D iio_get_current_scan_type(indio_dev, st->chip->channels); @@ -535,11 +563,52 @@ static int ad4030_set_mode(struct iio_dev *indio_dev,= unsigned long mask) st->mode); } =20 +/* + * Descramble 2 32bits numbers out of a 64bits. The bits are interleaved: + * 1 bit for first number, 1 bit for the second, and so on... + */ +static void ad4030_extract_interleaved(u8 *src, u32 *ch0, u32 *ch1) +{ + u8 h0, h1, l0, l1; + u32 out0, out1; + u8 *out0_raw =3D (u8 *)&out0; + u8 *out1_raw =3D (u8 *)&out1; + + for (int i =3D 0; i < 4; i++) { + h0 =3D src[i * 2]; + l1 =3D src[i * 2 + 1]; + h1 =3D h0 << 1; + l0 =3D l1 >> 1; + + h0 &=3D 0xAA; + l0 &=3D 0x55; + h1 &=3D 0xAA; + l1 &=3D 0x55; + + h0 =3D (h0 | h0 << 001) & 0xCC; + h1 =3D (h1 | h1 << 001) & 0xCC; + l0 =3D (l0 | l0 >> 001) & 0x33; + l1 =3D (l1 | l1 >> 001) & 0x33; + h0 =3D (h0 | h0 << 002) & 0xF0; + h1 =3D (h1 | h1 << 002) & 0xF0; + l0 =3D (l0 | l0 >> 002) & 0x0F; + l1 =3D (l1 | l1 >> 002) & 0x0F; + + out0_raw[i] =3D h0 | l0; + out1_raw[i] =3D h1 | l1; + } + + *ch0 =3D out0; + *ch1 =3D out1; +} + static int ad4030_conversion(struct iio_dev *indio_dev) { struct ad4030_state *st =3D iio_priv(indio_dev); unsigned char diff_realbytes =3D BITS_TO_BYTES(st->current_scan_type->realbits); + unsigned char diff_storagebytes =3D + BITS_TO_BYTES(st->current_scan_type->storagebits); unsigned int bytes_to_read; unsigned long cnv_nb =3D BIT(st->avg_log2); unsigned int i; @@ -564,10 +633,23 @@ static int ad4030_conversion(struct iio_dev *indio_de= v) if (ret) return ret; =20 - if (st->mode !=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM) + if (st->chip->num_voltage_inputs =3D=3D 2) + ad4030_extract_interleaved(st->rx_data.raw, + &st->rx_data.dual.diff[0], + &st->rx_data.dual.diff[1]); + + if (st->mode !=3D AD4030_OUT_DATA_MD_16_DIFF_8_COM && + st->mode !=3D AD4030_OUT_DATA_MD_24_DIFF_8_COM) + return 0; + + if (st->chip->num_voltage_inputs =3D=3D 1) { + st->rx_data.single.common =3D st->rx_data.raw[diff_realbytes]; return 0; + } =20 - st->rx_data.common =3D st->rx_data.raw[diff_realbytes]; + for (i =3D 0; i < st->chip->num_voltage_inputs; i++) + st->rx_data.dual.common[i] =3D + st->rx_data.raw[diff_storagebytes * i + diff_realbytes]; =20 return 0; } @@ -582,14 +664,25 @@ static int ad4030_single_conversion(struct iio_dev *i= ndio_dev, if (ret) return ret; =20 + st->current_scan_type =3D iio_get_current_scan_type(indio_dev, + st->chip->channels); + if (IS_ERR(st->current_scan_type)) + return PTR_ERR(st->current_scan_type); + ret =3D ad4030_conversion(indio_dev); if (ret) return ret; =20 if (chan->differential) - *val =3D st->rx_data.diff; + if (st->chip->num_voltage_inputs =3D=3D 1) + *val =3D st->rx_data.single.diff; + else + *val =3D st->rx_data.dual.diff[chan->address]; else - *val =3D st->rx_data.common; + if (st->chip->num_voltage_inputs =3D=3D 1) + *val =3D st->rx_data.single.common; + else + *val =3D st->rx_data.dual.common[chan->address]; =20 return IIO_VAL_INT; } @@ -882,10 +975,24 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) =20 static int ad4030_config(struct ad4030_state *st) { + int ret; + u8 reg_modes; + st->offset_avail[0] =3D (int)BIT(st->chip->precision_bits - 1) * -1; st->offset_avail[1] =3D 1; st->offset_avail[2] =3D BIT(st->chip->precision_bits - 1) - 1; =20 + if (st->chip->num_voltage_inputs > 1) + reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, + AD4030_LANE_MD_INTERLEAVED); + else + reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, + AD4030_LANE_MD_1_PER_CH); + + ret =3D regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); + if (ret) + return ret; + if (st->vio_uv < AD4030_VIO_THRESHOLD_UV) return regmap_write(st->regmap, AD4030_REG_IO, AD4030_REG_IO_MASK_IO2X); @@ -974,6 +1081,14 @@ static const unsigned long ad4030_channel_masks[] =3D= { 0, }; =20 +static const unsigned long ad4630_channel_masks[] =3D { + /* Differential only */ + BIT(1) | BIT(0), + /* Differential with common byte */ + GENMASK(3, 0), + 0, +}; + static const struct iio_scan_type ad4030_24_scan_types[] =3D { [AD4030_SCAN_TYPE_NORMAL] =3D { .sign =3D 's', @@ -991,6 +1106,23 @@ static const struct iio_scan_type ad4030_24_scan_type= s[] =3D { }, }; =20 +static const struct iio_scan_type ad4030_16_scan_types[] =3D { + [AD4030_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 16, + .endianness =3D IIO_BE, + }, + [AD4030_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_BE, + } +}; + static const struct ad4030_chip_info ad4030_24_chip_info =3D { .name =3D "ad4030-24", .available_masks =3D ad4030_channel_masks, @@ -1005,14 +1137,50 @@ static const struct ad4030_chip_info ad4030_24_chip= _info =3D { .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, }; =20 +static const struct ad4030_chip_info ad4630_16_chip_info =3D { + .name =3D "ad4630-16", + .available_masks =3D ad4630_channel_masks, + .channels =3D { + AD4030_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_DIFF(1, ad4030_16_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, + .precision_bits =3D 16, + .num_voltage_inputs =3D 2, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, +}; + +static const struct ad4030_chip_info ad4630_24_chip_info =3D { + .name =3D "ad4630-24", + .available_masks =3D ad4630_channel_masks, + .channels =3D { + AD4030_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_DIFF(1, ad4030_24_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, + .precision_bits =3D 24, + .num_voltage_inputs =3D 2, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, +}; 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Thu, 30 Jan 2025 03:08:52 -0800 (PST) Received: from [127.0.0.1] ([2a01:e0a:448:76e0:2c72:cd2d:79b2:82ff]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c102bb2sm1689225f8f.34.2025.01.30.03.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 03:08:52 -0800 (PST) From: Esteban Blanc Date: Thu, 30 Jan 2025 12:08:29 +0100 Subject: [PATCH v3 5/6] iio: adc: ad4030: add support for ad4632-16 and ad4632-24 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250130-eblanc-ad4630_v1-v3-5-052e8c2d897d@baylibre.com> References: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> In-Reply-To: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Esteban Blanc X-Mailer: b4 0.14.2 AD4632-24 and AD4632-16 are 2 channels ADCs. Both channels are interleaved bit per bit on SDO line. Both of them do not have evaluation board. As such, the support added here can't be tested. Support is provided as best effort until someone get their hands on one. Signed-off-by: Esteban Blanc --- drivers/iio/adc/ad4030.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 45d99152d84aeb878c7554edfdc32d3a1295e9c4..753051edbf96e3532d3178726c1= cd159263d7355 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -35,6 +35,8 @@ #define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10 #define AD4030_REG_CHIP_GRADE_AD4630_16_GRADE 0x03 #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 +#define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 +#define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -108,6 +110,9 @@ #define AD4030_TCYC_NS 500 #define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS) #define AD4030_TRESET_PW_NS 50 +#define AD4632_TCYC_NS 2000 +#define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) +#define AD4030_TRESET_COM_DELAY_MS 750 =20 enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, @@ -1169,10 +1174,44 @@ static const struct ad4030_chip_info ad4630_24_chip= _info =3D { .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, }; =20 +static const struct ad4030_chip_info ad4632_16_chip_info =3D { + .name =3D "ad4632-16", + .available_masks =3D ad4630_channel_masks, + .channels =3D { + AD4030_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_DIFF(1, ad4030_16_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, + .precision_bits =3D 16, + .num_voltage_inputs =3D 2, + .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, +}; + +static const struct ad4030_chip_info ad4632_24_chip_info =3D { + .name =3D "ad4632-24", + .available_masks =3D ad4630_channel_masks, + .channels =3D { + AD4030_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_DIFF(1, ad4030_24_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + IIO_CHAN_SOFT_TIMESTAMP(4), + }, + .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, + .precision_bits =3D 24, + .num_voltage_inputs =3D 2, + .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, + { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, + { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, { } }; 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Thu, 30 Jan 2025 03:08:53 -0800 (PST) Received: from [127.0.0.1] ([2a01:e0a:448:76e0:2c72:cd2d:79b2:82ff]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c102bb2sm1689225f8f.34.2025.01.30.03.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 03:08:53 -0800 (PST) From: Esteban Blanc Date: Thu, 30 Jan 2025 12:08:30 +0100 Subject: [PATCH v3 6/6] docs: iio: ad4030: add documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250130-eblanc-ad4630_v1-v3-6-052e8c2d897d@baylibre.com> References: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> In-Reply-To: <20250130-eblanc-ad4630_v1-v3-0-052e8c2d897d@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Cc: Michael Hennerich , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Esteban Blanc X-Mailer: b4 0.14.2 This adds a new page to document how to use the ad4030 ADC driver Signed-off-by: Esteban Blanc --- Documentation/iio/ad4030.rst | 181 +++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 183 insertions(+) diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst new file mode 100644 index 0000000000000000000000000000000000000000..41ce5ca5c710c46a0995d1b127f= a1c10fca4c1eb --- /dev/null +++ b/Documentation/iio/ad4030.rst @@ -0,0 +1,181 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD4030 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD4030 and similar devices. The module = name +is ``ad4030``. + + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD4030-24 `_ +* `AD4032-24 `_ +* `AD4630-16 `_ +* `AD4630-24 `_ +* `AD4632-16 `_ +* `AD4632-24 `_ + +IIO channels +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Each "hardware" channel as described in the datasheet is split in 2 IIO +channels: + +- One channel for the differential data +- One channel for the common byte. + +The possible IIO channels depending on the numbers of "hardware" channel a= re: + ++------------------------------------+------------------------------------+ +| 1 channel ADC | 2 channels ADC | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| - voltage0-voltage1 (differential) | - voltage0-voltage1 (differential) | +| - voltage2 (common-mode) | - voltage2-voltage3 (differential) | +| | - voltage4 (common-mode) | +| | - voltage5 (common-mode) | ++------------------------------------+------------------------------------+ + +Labels +------ + +For ease of use, the IIO channels provide a label. For a differential chan= nel, +the label is ``differentialN`` where ``N`` is the "hardware" channel id. F= or a +common-mode channel, the label is ``common-modeN`` where ``N`` is the +"hardware" channel id. + +The possible labels are: + ++-----------------+-----------------+ +| 1 channel ADC | 2 channels ADC | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| - differential0 | - differential0 | +| - common-mode0 | - differential1 | +| | - common-mode0 | +| | - common-mode1 | ++-----------------+-----------------+ + +Supported features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +SPI wiring modes +---------------- + +The driver currently supports the following SPI wiring configurations: + +One lane mode +^^^^^^^^^^^^^ + +In this mode, each channel has its own SDO line to send the conversion res= ults. +At the moment this mode can only be used on AD4030 which has one channel s= o only +one SDO line is used. + +.. code-block:: + + +-------------+ +-------------+ + | ADC | | HOST | + | | | | + | CNV |<--------| CNV | + | CS |<--------| CS | + | SDI |<--------| SDO | + | SDO0 |-------->| SDI | + | SCLK |<--------| SCLK | + +-------------+ +-------------+ + +Interleaved mode +^^^^^^^^^^^^^^^^ + +In this mode, both channels conversion results are bit interleaved one SDO= line. +As such the wiring is the same as `One lane mode`_. + +SPI Clock mode +-------------- + +Only the SPI clocking mode is supported. + +Output modes +------------ + +There are more exposed IIO channels than channels as describe in the devic= es +datasheet. This is due to the `Differential data + common-mode`_ encoding +2 types of information in one conversion result. As such a "device" channel +provides 2 IIO channels, one for the differential data and one for the com= mon +byte. + +Differential data +^^^^^^^^^^^^^^^^^ + +This mode is selected when: + +- Only differential channels are enabled in a buffered read +- Oversampling attribute is set to 1 + +Differential data + common-mode +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This mode is selected when: + +- Differential and common-mode channels are enabled in a buffered read +- Oversampling attribute is set to 1 + +For the 24-bits chips, this mode is also available with 16-bits differenti= al +data but is not selectable yet. + +Averaged differential data +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This mode is selected when: + +- Only differential channels are selected enabled in a buffered read +- Oversampling attribute is greater than 1 + +Digital Gain and Offset +----------------------- + +Each differential data channel has a 16-bits unsigned configurable hardware +gain applied to it. By default it's equal to 1. Note that applying gain can +cause numerical saturation. + +Each differential data channel has a signed configurable hardware offset. +For the ADCs ending in ``-24``, the gain is encoded on 24-bits. +Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note = that +applying an offset can cause numerical saturation. + +The final differential data returned by the ADC is computed by first apply= ing +the gain, then the offset. + +The gain is controlled by the ``calibscale`` IIO attribute while the offse= t is +controlled by the ``calibbias`` attribute. + +Reference voltage +----------------- + +The chip supports an external reference voltage via the ``REF`` input or an +internal buffered reference voltage via the ``REFIN`` input. The driver lo= oks +at the device tree to determine which is being used. If ``ref-supply`` is +present, then the external reference voltage is used and the internal buff= er is +disabled. If ``refin-supply`` is present, then the internal buffered refer= ence +voltage is used. + +Reset +----- + +Both hardware and software reset are supported. The driver looks first at = the +device tree to see if the ``reset-gpio`` is populated. +If not present, the driver will fallback to a software reset by wiring to = the +device's registers. + +Unimplemented features +---------------------- + +- ``BUSY`` indication +- Additional wiring modes +- Additional clock modes +- Differential data 16-bits + common-mode for 24-bits chips +- Overrange events +- Test patterns + diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index 074dbbf7ba0a087ab117efaf3d69fc559fc00fa5..982ac1bd9dfd7bfd54bfbf87d62= 58e6249edf799 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -19,6 +19,7 @@ Industrial I/O Kernel Drivers :maxdepth: 1 =20 ad4000 + ad4030 ad4695 ad7380 ad7606 diff --git a/MAINTAINERS b/MAINTAINERS index 9571a917b0437a802190101c0a83bba9bf790ffc..2cf66e6c7635eba394293342087= 8a610462f127e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1281,6 +1281,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +F: Documentation/iio/ad4030.rst F: drivers/iio/adc/ad4030.c =20 ANALOG DEVICES INC AD4130 DRIVER --=20 2.47.2