From nobody Mon Feb 9 15:07:01 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0723B33997 for ; Wed, 29 Jan 2025 15:48:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738165690; cv=none; b=RBzZDaElzEOITOilDCPBZF44haSThZMzmsmSy02OKaMenwCRLU1iJ3SeudpvkOk+th56v7b/fxM7JWdqhITVVJJCqoNytm2JRZKXJgI35VaFOozj8hAMLPUZ/CcOw7qQh1qWerMOS9NNKOyGfa/5JNQ/jsy5vAT+44MtH1GIEPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738165690; c=relaxed/simple; bh=s64cKgIaPu4saFifMwdX/Vl5ylPbrbaF472vL8wl9cg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J2lIfWvxqQOFEjGqEr0mAeKgQ3JXYw9AozmzK/azG5+ytBQARoV0FRm4wqdd1swhIKaf8sIgrhiNyX7D4s1OdySufVJgbietf7V55S7v1UUHbiIjdO6mOlN/T2sO+D+zQ8bO6jP9QMoccCqrFrHLx+E0rct31HrzgVSDsxqsH7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ArzGCCa7; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ArzGCCa7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738165689; x=1769701689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s64cKgIaPu4saFifMwdX/Vl5ylPbrbaF472vL8wl9cg=; b=ArzGCCa7/KagsOdqDy1j6zEySCrhlgHY4vSxDtPv9QNhlz1jcjzIu4XK 0EaArIC9jus2OXE+7Aaj9CXDt62AhxXWF0CbrIj3mkOH4vdxydekucyOL zL7XGvnJ5c/qnXfic/PJzTe5Bv2+HKbywJPiYC8mF7XnKeSBd6a2vcJY0 vZeQh3ylK48lxjIkudMwOzxKbF+Moz1jgcQy7N1Bw3tQf+zeOT1YXzhO4 veAUuZJFFSZrcLNFbBlwOsoNsdcUZDa+0oufU1w18KFOo0wZyr6HD+oEn 3xQ+qlXq5Q0aDga+8EdeE6EDFeL8pRSbIOQ26h8pQyBopk/RfUrcwqwHA g==; X-CSE-ConnectionGUID: 7sPZSg2iQSKEg7Y6ToFRvA== X-CSE-MsgGUID: aU4MjDHKT1ii7WYq/F87Rw== X-IronPort-AV: E=McAfee;i="6700,10204,11330"; a="37882918" X-IronPort-AV: E=Sophos;i="6.13,243,1732608000"; d="scan'208";a="37882918" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 07:48:06 -0800 X-CSE-ConnectionGUID: 4cYR7tRqRaqBipx1PCUppA== X-CSE-MsgGUID: oJon+YFdS7OZUoIXxCtgnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="108927426" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orviesa010.jf.intel.com with ESMTP; 29 Jan 2025 07:48:06 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, ak@linux.intel.com, linux-kernel@vger.kernel.org Cc: dapeng1.mi@linux.intel.com, Kan Liang Subject: [PATCH 1/3] perf/x86/intel: Clean up PEBS-via-PT on hybrid Date: Wed, 29 Jan 2025 07:48:18 -0800 Message-Id: <20250129154820.3755948-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250129154820.3755948-1-kan.liang@linux.intel.com> References: <20250129154820.3755948-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The PEBS-via-PT feature is exposed for the e-core of some hybrid platforms, e.g., ADL and MTL. But it never works. $ dmesg | grep PEBS [ 1.793888] core: cpu_atom PMU driver: PEBS-via-PT $ perf record -c 1000 -e '{intel_pt/branch=3D0/, cpu_atom/cpu-cycles,aux-output/pp}' -C8 Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (cpu_atom/cpu-cycles,aux-output/pp). "dmesg | grep -i perf" may provide additional information. The "PEBS-via-PT" is printed if the corresponding bit of per-PMU capabilities is set. Since the feature is supported by the e-core HW, perf sets the bit for e-core. However, for Intel PT, if a feature is not supported on all CPUs, it is not supported at all. The PEBS-via-PT event cannot be created successfully. The PEBS-via-PT is no longer enumerated on the latest hybrid platform. It will be deprecated on future platforms with Arch PEBS. Let's remove it from the existing hybrid platforms. Fixes: d9977c43bff8 ("perf/x86: Register hybrid PMUs") Signed-off-by: Kan Liang Cc: Adrian Hunter Cc: Alexander Shishkin --- The original V1 patch can be found at https://lore.kernel.org/lkml/20250124183432.3565061-1-kan.liang@linux.intel= .com/ The patch only updates the comments. arch/x86/events/intel/core.c | 10 ---------- arch/x86/events/intel/ds.c | 10 +++++++++- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7f1b6b90a5fb..0a1030eb6db8 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4981,11 +4981,6 @@ static void intel_pmu_check_hybrid_pmus(struct x86_h= ybrid_pmu *pmu) else pmu->intel_ctrl &=3D ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); =20 - if (pmu->intel_cap.pebs_output_pt_available) - pmu->pmu.capabilities |=3D PERF_PMU_CAP_AUX_OUTPUT; - else - pmu->pmu.capabilities &=3D ~PERF_PMU_CAP_AUX_OUTPUT; - intel_pmu_check_event_constraints(pmu->event_constraints, pmu->cntr_mask64, pmu->fixed_cntr_mask64, @@ -5063,9 +5058,6 @@ static bool init_hybrid_pmu(int cpu) =20 pr_info("%s PMU driver: ", pmu->name); =20 - if (pmu->intel_cap.pebs_output_pt_available) - pr_cont("PEBS-via-PT "); - pr_cont("\n"); =20 x86_pmu_show_pmu_cap(&pmu->pmu); @@ -6420,11 +6412,9 @@ static __always_inline int intel_pmu_init_hybrid(enu= m hybrid_pmu_type pmus) pmu->intel_cap.capabilities =3D x86_pmu.intel_cap.capabilities; if (pmu->pmu_type & hybrid_small_tiny) { pmu->intel_cap.perf_metrics =3D 0; - pmu->intel_cap.pebs_output_pt_available =3D 1; pmu->mid_ack =3D true; } else if (pmu->pmu_type & hybrid_big) { pmu->intel_cap.perf_metrics =3D 1; - pmu->intel_cap.pebs_output_pt_available =3D 0; pmu->late_ack =3D true; } } diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 13a78a8a2780..46aaaeae0c8d 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2742,7 +2742,15 @@ void __init intel_ds_init(void) } pr_cont("PEBS fmt%d%c%s, ", format, pebs_type, pebs_qual); =20 - if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { + /* + * The PEBS-via-PT is not supported on hybrid platforms, + * because not all CPUs of a hybrid machine support it. + * The global x86_pmu.intel_cap, which only contains the + * common capabilities, is used to check the availability + * of the feature. The per-PMU pebs_output_pt_available + * in a hybrid machine should be ignored. + */ + if (x86_pmu.intel_cap.pebs_output_pt_available) { pr_cont("PEBS-via-PT, "); x86_get_pmu(smp_processor_id())->capabilities |=3D PERF_PMU_CAP_AUX_OU= TPUT; } --=20 2.38.1