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([178.197.218.98]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1bb040sm17528115f8f.67.2025.01.29.07.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 07:45:23 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent Date: Wed, 29 Jan 2025 16:45:19 +0100 Message-ID: <20250129154519.209791-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up the rates, because this messes up entire clock hierarchy when setting clock rates in MSM DSI driver. The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates via dev_pm_opp_set_rate() on byte clock and then sets individual clock rates, like pixel and byte_intf clocks, to proper frequencies. Having CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this and align with SM8550 and SM8650. Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock co= ntroller") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong --- Fix for v6.14-rcX. --- drivers/clk/qcom/dispcc-sm8750.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8= 750.c index 0358dff91da5..e9bca179998b 100644 --- a/drivers/clk/qcom/dispcc-sm8750.c +++ b/drivers/clk/qcom/dispcc-sm8750.c @@ -827,7 +827,6 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk= _src =3D { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; @@ -842,7 +841,6 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk= _src =3D { &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_regmap_div_ops, }, }; --=20 2.43.0