From nobody Thu Dec 18 09:45:22 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9094414D433 for ; Wed, 29 Jan 2025 13:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738156629; cv=none; b=cVlms7ohz8vJ9GYdYMxYgmYsa+IwmSY04+sEY52HqsOA6VoGL1ZU/bjkxIgHk41WCICtfAwdlcGcv4CVPbH+nAr35A9MzdkEca9UmN1O8/werJq6lYRvdJF2F5iOJ1PHuGwy/Kk8cBeIPK7bvaEw8i/VxWrZhYXOd7snYdINiZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738156629; c=relaxed/simple; bh=ReZxFIqLR0hdwHVdMvwtJkff3li/LDULGUeO3+SkwvI=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Content-Type; b=BSwI6fMeVmPPqMiPJfqxvcUcmqv0T9zUmPBA8Dx3u2spei1W+DH7jmGio+spVfNIJ1ujP4Un8V5wyc1TFs3Xd6ZOj5w7by/fXqQO1AkJ6IaPMBs+yLlmJigmJlZ/JYpczHH187nDfO/PlrmpPFvVR2m+7tO3a9gDj4Zkxw/wUMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZECdOKUk; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZECdOKUk" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-5d7e3f1fdafso12954797a12.0 for ; Wed, 29 Jan 2025 05:17:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738156626; x=1738761426; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=FrzHi7EcBna9oszkhdrvxCzw/It0oCRqn6cqPoPKlzA=; b=ZECdOKUkSQd9f7hwwdcLLDX/6HgOJDqgKniUmDjulHjcJyRrJdZB/xmJwP1PJiCimR 5LSXK5ZgIalT9fafiQZJpdc2VK2hdvTlR/VAwIZ8wH+Js8qXpIYmZYKOuUyfcK2nOH4o G+X4KzEagZKD2sq0wYAgGwKAPy5exmgEaaF4XBecI0bOHm6x3fmIWJ3IXArKwa0cw/os GRxxSgQr1YHtlKy8xJwfBPe2GiKmgHKOHDR+XWIXNQ8rWi/uAlfmB5fqa4V4AmILntMF 7rSbunqF82kEwxcfQ8kkAVOEfh/t+WV15IqNvxSUQAdzwLYrVIM8LDkMHIOlcZuaktZ8 mpQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738156626; x=1738761426; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FrzHi7EcBna9oszkhdrvxCzw/It0oCRqn6cqPoPKlzA=; b=uZ5rTrNIrr9btRSzjuSABeXqQnA6TjMa8xPQw7B/tWXOruGTwkaCkM0cbPyuf/WHJg drB5GRfJ+hXnlrzAr5by3qoWMumu+CLioZ1caxlIYl/qupT3b+0/4fN1zRS97IEu83Rb 4c2r3x6baCW9t5RdwHFfSwUT3tccdoba7YIH10khb3aeier+DueSq9ulDOEuEv84SV/j 01rqITKktZCjq3DXwSSEt94sjYE0+74zt+P8mNPGKQmYe5ml4ycU87xAGAUUtt4JBns6 MDhgsSLUh5PP9iYgn/F7c642Uq29reAH6PksHbP4zInUQvj2O8Iq9BO2VNDXXc7Jje8b h2Qw== X-Forwarded-Encrypted: i=1; AJvYcCVB9oWPZK6lCAPQj1Bb1i1B26/KufI9b6n/acJbk43Nfc7wGFdBtExN1S+2vjN8uyxiadIOzR4dPGaAhbI=@vger.kernel.org X-Gm-Message-State: AOJu0YyqCZ/Tu8oxdAaNFyyC1+U8HYBwgv1MGqwQ9pqt4QIRhYlWhnnG F0FsGgjFlp2/9CuUwmTCBWDPl2ovNtK4hKhlKFajexh3+Bz5hciR X-Gm-Gg: ASbGncv9g+2IP7OAvljUGYlAODbhBgCySpAuocoaRBkXQ6JEbwSvWMlBec/0wed2paW Ja15WJ4LZuanZ0o2mbTPLP/7RxW1/LHAm6QnDp/SgRDJt7Xu0MzrcWYaosIFsCRBxHeJiw16V65 RHZbF11eUsNdyvusB9WFTqPw9rAy+/8NPYgjGoKg38ezCJQbH4GrZL/c54Td67Ujisj3iVj+6gj hLco+CIu+UF2tmi3oOs36kDokzrefEo1pK/WsLWX82DueqR8SHel6T6Xe99m6kkzO+If6DKWw+t mzKVB8TmThXTNan1BmCPzNAM X-Google-Smtp-Source: AGHT+IE/JeaMlECCj6vgX8ISzQ+c9qstL/zmPISYVXw2GilRdHKOw9QquXTAzMnJOGnCk7G48Lpbhg== X-Received: by 2002:a17:907:9711:b0:ab3:47c8:d3c6 with SMTP id a640c23a62f3a-ab6cfcca024mr261771966b.11.1738156625302; Wed, 29 Jan 2025 05:17:05 -0800 (PST) Received: from localhost.localdomain ([79.175.114.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab675e6299dsm956189466b.47.2025.01.29.05.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 05:17:04 -0800 (PST) From: Aleksandar Rikalo To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , =?UTF-8?q?Christoph=20M=C3=BCllner?= , Aleksandar Rikalo , linux-kernel@vger.kernel.org, Djordje Todorovic Subject: [PATCH v3] riscv: Fix the PAUSE Opcode for MIPS P8700. Date: Wed, 29 Jan 2025 14:17:03 +0100 Message-Id: <20250129131703.733098-1-arikalo@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Djordje Todorovic The riscv MIPS P8700 uses a different opcode for PAUSE. It is a =E2=80=98hint=E2=80=99 encoding of the SLLI instruction, with rd=3D= 0, rs1=3D0 and imm=3D5. It will behave as a NOP instruction if no additional behavior beyond that of SLLI is implemented. Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for MIPS CPUs. Signed-off-by: Djordje Todorovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Raj Vishwanathan4 --- arch/riscv/Kconfig.errata | 23 +++++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/mips/Makefile | 5 +++ arch/riscv/errata/mips/errata.c | 41 +++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/cmpxchg.h | 3 +- arch/riscv/include/asm/errata_list.h | 20 ++++++++- arch/riscv/include/asm/vdso/processor.h | 4 +- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 +++ arch/riscv/kernel/entry.S | 2 + arch/riscv/mm/init.c | 1 + tools/arch/riscv/include/asm/vdso/processor.h | 5 ++- 13 files changed, 110 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/errata/mips/Makefile create mode 100644 arch/riscv/errata/mips/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 2acc7d876e1f..1589528fdc30 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO =20 If you don't know what to do here, say "Y". =20 +config ERRATA_MIPS + bool "MIPS errata" + depends on RISCV_ALTERNATIVE + help + All MIPS errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all MIPS errata. Please say "Y" + here if your platform uses MIPS CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_MIPS_P8700_PAUSE_OPCODE + bool "Fix the PAUSE Opcode for MIPS P8700" + depends on ERRATA_MIPS && 64BIT + default n + help + The RISCV MIPS P8700 uses a different opcode for PAUSE. + It is a 'hint' encoding of the SLLI instruction, + with rd=3D0, rs1=3D0 and imm=3D5. It will behave as a NOP + instruction if no additional behavior beyond that of + SLLI is implemented. + + If you are not using the P8700 processor, say n. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index f0da9d7b39c3..156cafb338c1 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -9,5 +9,6 @@ endif endif =20 obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ +obj-$(CONFIG_ERRATA_MIPS) +=3D mips/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makef= ile new file mode 100644 index 000000000000..6278c389b801 --- /dev/null +++ b/arch/riscv/errata/mips/Makefile @@ -0,0 +1,5 @@ +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY +CFLAGS_errata.o :=3D -mcmodel=3Dmedany +endif + +obj-y +=3D errata.o diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errat= a.c new file mode 100644 index 000000000000..998bbcaa50d1 --- /dev/null +++ b/arch/riscv/errata/mips/errata.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include +#include + +void mips_errata_patch_func(struct alt_entry *begin, + struct alt_entry *end, + unsigned long archid, + unsigned long impid, + unsigned int stage) +{ + struct alt_entry *alt; + + BUILD_BUG_ON(ERRATA_MIPS_NUMBER >=3D RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt =3D begin; alt < end; alt++) { + if (alt->vendor_id !=3D MIPS_VENDOR_ID) + continue; + + if (alt->patch_id >=3D ERRATA_MIPS_NUMBER) { + WARN(1, "MIPS errata id:%d not in kernel errata list\n", + alt->patch_id); + continue; + } + + mutex_lock(&text_mutex); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), alt->alt_len); + mutex_unlock(&text_mutex); + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 3c2b59b25017..bc3ada8190a9 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -48,6 +48,9 @@ struct alt_entry { void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, unsigned long archid, unsigned long impid, unsigned int stage); +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 4cadc56220fe..2f5705f49dcc 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -13,6 +13,7 @@ #include #include #include +#include =20 #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \ swap_append, r, p, n) \ @@ -404,7 +405,7 @@ static __always_inline void __cmpwait(volatile void *pt= r, return; =20 no_zawrs: - asm volatile(RISCV_PAUSE : : : "memory"); + ALT_RISCV_PAUSE(); } =20 #define __cmpwait_relaxed(ptr, val) \ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 7c8a71a526a3..68c46ccb9b7c 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -5,7 +5,6 @@ #ifndef ASM_ERRATA_LIST_H #define ASM_ERRATA_LIST_H =20 -#include #include #include #include @@ -28,6 +27,11 @@ #define ERRATA_THEAD_NUMBER 2 #endif =20 +#ifdef CONFIG_ERRATA_MIPS +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0 +#define ERRATA_MIPS_NUMBER 1 +#endif + #ifdef __ASSEMBLY__ =20 #define ALT_INSN_FAULT(x) \ @@ -58,6 +62,20 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIV= E_VENDOR_ID, \ ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ : : "r" (addr), "r" (asid) : "memory") =20 +#ifdef CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE +#define ALT_RISCV_PAUSE() \ +asm volatile(ALTERNATIVE( \ + RISCV_PAUSE, /* Original RISC=E2=80=91V pause insn */ = \ + ".4byte 0x00501013", /* Replacement for MIPS P8700 */ \ + MIPS_VENDOR_ID, /* Vendor ID to match */ \ + ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */ \ + CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE) \ + : /* no outputs */ : /* no inputs */ : "memory") +#else +#define ALT_RISCV_PAUSE() \ + asm volatile(RISCV_PAUSE : : : "memory") +#endif + /* * _val is marked as "will be overwritten", so need to set it to 0 * in the default case. diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index 8f383f05a290..8f749552ecfe 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -5,6 +5,8 @@ #ifndef __ASSEMBLY__ =20 #include + +#include #include =20 static inline void cpu_relax(void) @@ -19,7 +21,7 @@ static inline void cpu_relax(void) * Reduce instruction retirement. * This assumes the PC changes. */ - __asm__ __volatile__ (RISCV_PAUSE); + ALT_RISCV_PAUSE(); barrier(); } =20 diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index a5150cdf34d8..3b09874d7a6d 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,5 +9,6 @@ #define MICROCHIP_VENDOR_ID 0x029 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x722 =20 #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 7eb3cb1215c6..7642704c7f18 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactu= rer_info_t *cpu_mfr_info cpu_mfr_info->patch_func =3D andes_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_MIPS + case MIPS_VENDOR_ID: + cpu_mfr_info->patch_func =3D mips_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 33a5a9f2a0d4..2007d9de7f27 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -15,6 +15,8 @@ #include #include #include +#include + #include =20 .section .irqentry.text, "ax" diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 722178ae3488..ee8a2c5b40f8 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 #include "../kernel/head.h" =20 diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/ris= cv/include/asm/vdso/processor.h index 662aca039848..880f26a24f69 100644 --- a/tools/arch/riscv/include/asm/vdso/processor.h +++ b/tools/arch/riscv/include/asm/vdso/processor.h @@ -14,7 +14,10 @@ static inline void cpu_relax(void) __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)); #endif =20 -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE +#ifdef CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE + /* MIPS P8700 pause opcode */ + __asm__ __volatile__ (".4byte 0x00501013"); +#elif CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE /* * Reduce instruction retirement. * This assumes the PC changes. --=20 2.25.1