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[95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:14 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:08 +0100 Subject: [PATCH v3 07/10] iio: adc: adi-axi-adc: add support for AD7606 register writing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-7-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols Since we must access the bus parallel bus using a custom procedure, let's add a specialized compatible, and define specialized callbacks for writing the registers using the parallel interface. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- drivers/iio/adc/adi-axi-adc.c | 100 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 0923565cf5bb..aaeb445a8a3e 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -27,6 +27,7 @@ #include #include =20 +#include "ad7606_bus_iface.h" /* * Register definitions: * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map @@ -73,6 +74,12 @@ #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) =20 +#define ADI_AXI_REG_CONFIG_WR 0x0080 +#define ADI_AXI_REG_CONFIG_RD 0x0084 +#define ADI_AXI_REG_CONFIG_CTRL 0x008c +#define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 +#define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 + #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 =20 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ @@ -80,6 +87,10 @@ ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ ADI_AXI_REG_CHAN_CTRL_ENABLE) =20 +#define ADI_AXI_REG_READ_BIT 0x8000 +#define ADI_AXI_REG_ADDRESS_MASK 0xff00 +#define ADI_AXI_REG_VALUE_MASK 0x00ff + struct axi_adc_info { unsigned int version; const struct iio_backend_info *backend_info; @@ -313,6 +324,81 @@ static struct iio_buffer *axi_adc_request_buffer(struc= t iio_backend *back, return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); } =20 +static int axi_adc_raw_write(struct iio_backend *back, void *buf, unsigned= int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 data; + + data =3D *(u32 *)(buf); + + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, data); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_WRITE); + usleep_range(50, 100); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int axi_adc_raw_read(struct iio_backend *back, void *buf, unsigned = int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 *bdata =3D buf; + + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_READ); + usleep_range(50, 100); + regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, bdata); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* + * The address is written on the highest weight byte, and the MSB set + * at 1 indicates a read operation. + */ + buf =3D FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT; + axi_adc_raw_write(back, &buf, sizeof(buf)); + axi_adc_raw_read(back, val, 4); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + return 0; +} + +static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* Write any register to switch to register mode */ + buf =3D 0xaf00; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + buf =3D FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | + FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val); + axi_adc_raw_write(back, &buf, sizeof(buf)); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + return 0; +} + static void axi_adc_free_buffer(struct iio_backend *back, struct iio_buffer *buffer) { @@ -484,9 +570,23 @@ static const struct axi_adc_info adc_generic =3D { .backend_info =3D &adi_axi_adc_generic, }; =20 +static const struct ad7606_platform_data ad7606_pdata =3D { + .bus_reg_read =3D ad7606_bus_reg_read, + .bus_reg_write =3D ad7606_bus_reg_write, +}; + +static const struct axi_adc_info adc_ad7606 =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &adi_axi_adc_generic, + .bus_controller =3D true, + .pdata =3D &ad7606_pdata, + .pdata_sz =3D sizeof(ad7606_pdata), +}; + /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, + { .compatible =3D "adi,axi-ad7606x", .data =3D &adc_ad7606 }, { /* end of list */ } }; MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); --=20 2.47.0