From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 019C31B4153 for ; Wed, 29 Jan 2025 11:04:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148700; cv=none; b=SQP5qrIdXKbBimm6cvlOq883Z8W46KUKFumxrylXBZL3wu94o+loIc94/xhksj2OoDthf6gLzgALSeoLxcXWTuoJezWE8FXNxnl//Z0i+SI0cA3EFhVEaGdD+VY1Q3nlbVfYieCK2Ufhu87SORNkvEYfGbK/7D2HjIMONhw8sIw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148700; c=relaxed/simple; bh=qTP9VZUeKRuaZ9Hqi5LnAy3vZJvi795fRxc+xbuF8Io=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JBp+FyDUkODv2p35mN2R1WBtia71SPu0Y2BO7FGm5r+HSpCBrIZ1yMnM5VL6btlKrQEdtqTtOmBH9pJMYnveLIrYayfMfqA/585QMC55EoT3Wtpj8KZkNamKskKtrUsi4goESHtDCJrRxeaoRiBQZiTUdyaaqGkE1u8B22p727o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=yq/gACss; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="yq/gACss" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3862f32a33eso3092108f8f.3 for ; Wed, 29 Jan 2025 03:04:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148697; x=1738753497; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vjQqajOlG7CxEKLfZvVkKt1P2pyBeTRvUu/sCOgs0mw=; b=yq/gACssKX8rQhDMds6SLHK7d7qPBSLXuWCSIA+BltrjAMGOjRDPkIwLX+nm4tK7dt nNifzCSqvgDSHrFzAP7WqsR8VN4j/2nwUvbMZW9+4IPEgHiTyzIJPyH9HBufzxxi7q+h te0tHiakS2DZ7nSmIq+RMpur8kqNIQWvSyDSct6L7TSC3qypEU1EVyqnqjRiRYcyCmTk EuC1yzHKY352syOFjAZDV8gqwSiB34gYZlj8b/TR6XHqO/cylVpUzWQnsStSDjvtIuvg pik3RlgR9FmPDxKNoRHWT4JeYwaSnX7mXQS877HhHMkR5Ows7j8yE/YrjCzCN5PWFDl8 vrOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148697; x=1738753497; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vjQqajOlG7CxEKLfZvVkKt1P2pyBeTRvUu/sCOgs0mw=; b=NrXeBiQDCQbkzv0G7DTAP2c+rfkOp5GAMO6u9A/abemCPaZl4smE+dwYDJBVq+NTMt kOrt3aMNza1NhxKS61JpWsCJu2CC6PVhz9tgrCXEyNqCepoTCoqCRXJwXK0vPrzg/OF5 oj1c1gbkNJ5VrICjvcxmVaGAaRi8yRMM4RvyjCqCLVnPPIkCSa27a41+laCz+oRz7CSn 51xZndIRknExAytOgAA/oahVZggDOckBbiJLx06/Cf6eqTFsJwQPNPIFDjwCXxGWm1MD EIRnjwgPv0iJY8I/N9/F7XCk2UA3I+KZ4ubZ0x+LXl7KA6GV0AACDKNJUTW+eVR0XaZ4 Pnew== X-Forwarded-Encrypted: i=1; AJvYcCWLfMQXY5bO7q61J+0zjwV5Z2xVXiGFhEsYJXsyxjPiK9vg+SCI19BU9Hwbzki0r6vKQmg51AdL8AfUvLA=@vger.kernel.org X-Gm-Message-State: AOJu0YxsIqOmDQpHnu6XXdTaGjjEGLA1Q32WMqc+PyP0YcrYc2w8QOJw L6TVFTJa13m1QjVBc+H7g4qjEazj2YHGsSgeUSmOeDOaS4tKHUWdkmW49FI5Vis= X-Gm-Gg: ASbGnctNYlCWW8MsrpUU1kqFrlnEMs7alOr9suguAfwihiRhanpXUfL4Ekkw/z3oqWD 3Y7Bbp6DhqsgiBOvo+bxhAmrRSbZG6+c76zzHmQKCuj4Rvwc5FL78TbDn8fcNsJ/sohfnKVDIOM 3I8WQD49Qb+lRhZkjO/wgDW5+qpjHAq3/MnOUPHglZrCuE+7WhbPEHuezPKO9fV2r7OENuVQGch OQ6ByWxh+0uGrL3vjkIq0TrIJmRL2vKedaCIDNKxHrEnzC+YL7Gkb5nWfW6k0nLvBvE/OO1d1u4 sGPozUOt/MEHQNwRCDpXtEyevgACcQh1qPUGRgn1Z7oKFd5Q/+8CI8Ycb/Kl0o16bcSqKRE= X-Google-Smtp-Source: AGHT+IGuZV55gZIAdwXj62dAal2XvKkGucrO0OnzpAfK3Sa3kD6jA1qfS4afbucGb1xx4G4rVbpYwA== X-Received: by 2002:a5d:6489:0:b0:38c:246f:b0b3 with SMTP id ffacd0b85a97d-38c52097871mr2095096f8f.51.1738148697140; Wed, 29 Jan 2025 03:04:57 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:04:56 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:02 +0100 Subject: [PATCH v3 01/10] dt-bindings: iio: dac: adi-axi-adc: fix ad7606 pwm-names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-1-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Fix make dt_binding_check warning: DTC [C] Documentation/devicetree/bindings/iio/adc/adi,axi-adc.example.dtb .../adc/adi,axi-adc.example.dtb: adc@0: pwm-names: ['convst1'] is too short from schema $id: http://devicetree.org/schemas/iio/adc/adi,ad7606.yaml# Add "minItems" to pwm-names, it allows to use one single pwm when connected to both adc conversion inputs. Fixes: 7c2357b10490 ("dt-bindings: iio: adc: ad7606: Add iio backend bindin= gs") Signed-off-by: Angelo Dureghello Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index ab5881d0d017..52d3f1ce3367 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -146,6 +146,7 @@ properties: maxItems: 2 =20 pwm-names: + minItems: 1 items: - const: convst1 - const: convst2 --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 611A91B87F7 for ; Wed, 29 Jan 2025 11:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148703; cv=none; b=PVwVVu8KV3yqx0Y5L41cZF2+b8nsxRK9S+w2o/5ncf0o05Qi9y5K0BeOpM2pGq0iGwnbuwLDCgnY8eKlCFa3EgnB+w/gFZ0NeimOkZX/uXz50s+XdF35dduUnRosbbmYnFuP490MGhvxuZ+vcQB1qgffzcKjeiEV3yioopXrq44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148703; c=relaxed/simple; bh=cnVjGzTMN2TPaWEc4tBzgCPSdtCmJYQ6NezfGmcnYHg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UHoz3UgB0sJwuW3hXTICsZVJ+CfHP74Sp8HLUjXLP4QoTTurQIMSQZs+fB7OMcuzzGSrp7h+IdcFIajQWt1ktNauLZ2w0GYWxFkv6ZJkf3DupIRFtGpGNReFyE/0yY0KEpZAdiAYhC6peBXd/EIvIsb8HoBF84H0P1kYwglYd6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=zkMbT9Wk; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="zkMbT9Wk" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4361b6f9faeso3745315e9.1 for ; Wed, 29 Jan 2025 03:05:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148699; x=1738753499; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R/0RoFqTCD5DMTJ3Smbits6g5SDLM5bAcIh9sicHZS8=; b=zkMbT9WkPQks7OCYPjNEeAEyxrDJMvWEzxmT0teydkpJ8Qci57b76k+M06sJW/Q3Xf QouadG6ykCFIYvLDclp2n6OH4SDmoWOozWogcQtIU02dUUZDU78WkUV3RNaXMgt/TdrM c1Mlb4r4NgAT1UJQWszbDW/aNTG6KdwnDsp5Gk89HVHG5RIXtL5H20mRiJ31Qy6wAkwE iFm15YRRXNIgUtXv0JoEu/VgDyDDVjLDbIV/es/1NY8ceJdM7QUsdAzI2QKu0yO/bhMJ mcx5xiJqkTf7FdgdwY0vKzPK+fmwrGQdXIrdqpkTgPfRiz/Ko7wFOV6Rm1et0WHag5lR 2sXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148699; x=1738753499; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/0RoFqTCD5DMTJ3Smbits6g5SDLM5bAcIh9sicHZS8=; b=a1K2+rnX7PKY/1ENPZaYSQO56+cA72kxWZIj9/1Nacm9Xz4cLtGYmeJZmaNNn6ZETt u94OOLyUf76en5POYnOGv/N+ilPVRzEbxJl2cD+wMxySUazT4Dn9TpUEvCKAoJ3B4GPn LkfVQ38BKdksN0sxQ0tRSbtIrJMBcoSRzvoWpogY3E7Ft7P6GbzL4uBPqJWXD3LR+peQ LV1YdOxDQ/E6h3QCZks6TeWdNYbZCCDb9vvhn/Zn0HCzjJs5GWRWzmDYoS14o15wf4TY QSu8tE7wF2g3+zNmWfeg8r0n3XUuJLSkNW2F2tnzE1zC38AHe5MM+kPtGNwBkwKVe2vi 4wsg== X-Forwarded-Encrypted: i=1; AJvYcCWJwTFMbcxrmVaT9IJsh86q434QCWfia1W/K04JbfHy0Zp8zt6YydcIBib1oe2vvAuYO52P+qEGwsZEwHw=@vger.kernel.org X-Gm-Message-State: AOJu0YyxZgWpMFdztDKBNrfJaQWa1LOFcvN4qdFJXqBoX+hZlTVfrt2V KXGVGZSUH+qFrjWy61YPfhikose2UsGqAvMfvWzx83NrHfnLZ8ZHF8083bWfyms= X-Gm-Gg: ASbGnctTOA9L52BGlUEDmxvod5/zyODFuEyuEucYM4sqYhuFYRUU0HzwwuvbOl9Kpnw AiSknw+kjbDu0dZQsA8EihQnuSW0ygsBCvP+eFNvqRvXqWsPJ5g5Mht+Gp257/qhGL0E1VfJWv1 RiH171whL/xHU+e3hGKbEG5HwRqjrG2QlkKYWPHtc0A+LeORKCyPAjtdUmX5lF2d+3EC9PJE6HV j2oGJBcREB6zoX0VOBEiEhQN4omlQYMxcQBEKEjqISbCl+c4GhnG0zYDndpI8d5pFVL54eIyDcx n4CHD+wqISV/Wpitv85n9ZTGDYH4TlwmiyG63FT8xGxdHJSszs1ibmgnNGGNh3YVPNHcCsY= X-Google-Smtp-Source: AGHT+IFBn2p+/DJKFxVKospqHngi1hJUPJKLIlntYQuHgPLs/sEFjOQJayjg0+HqA9m/QLDPtJ23iw== X-Received: by 2002:a05:600c:4f0f:b0:438:a313:cda9 with SMTP id 5b1f17b1804b1-438d599b9a0mr59366575e9.10.1738148699584; Wed, 29 Jan 2025 03:04:59 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:04:58 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:03 +0100 Subject: [PATCH v3 02/10] dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-2-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols A new compatible is added to reflect the specialized version of the HDL. We use the parallel interface to write the ADC's registers, and accessing this interface requires to use ADI_AXI_REG_CONFIG_RD, ADI_AXI_REG_CONFIG_WR and ADI_AXI_REG_CONFIG_CTRL in a custom fashion. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/iio/adc/adi,axi-adc.yaml | 70 ++++++++++++++++++= +++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/D= ocumentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index e1f450b80db2..4fa82dcf6fc9 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -17,13 +17,23 @@ description: | interface for the actual ADC, while this IP core will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. + In some cases, the AXI ADC interface is used to perform specialized + operation to a particular ADC, e.g access the physical bus through + specific registers to write ADC registers. + In this case, we use a different compatible which indicates the target + IP core's name. + The following IP is currently supported: + - AXI AD7606x: specialized version of the IP core for all the chips fr= om + the ad7606 family. =20 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html =20 properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad7606x =20 reg: maxItems: 1 @@ -47,17 +57,48 @@ properties: '#io-backend-cells': const: 0 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^adc@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + additionalProperties: true + required: + - compatible + - reg + required: - compatible - dmas - reg - clocks =20 +allOf: + - if: + properties: + compatible: + not: + contains: + const: adi,axi-ad7606x + then: + properties: + '#address-cells': false + '#size-cells': false + patternProperties: + "^adc@[0-9a-f]+$": false + additionalProperties: false =20 examples: - | - axi-adc@44a00000 { + adc@44a00000 { compatible =3D "adi,axi-adc-10.0.a"; reg =3D <0x44a00000 0x10000>; dmas =3D <&rx_dma 0>; @@ -65,4 +106,31 @@ examples: clocks =3D <&axi_clk>; #io-backend-cells =3D <0>; }; + - | + #include + parallel_bus_controller@44a00000 { + compatible =3D "adi,axi-ad7606x"; + reg =3D <0x44a00000 0x10000>; + dmas =3D <&rx_dma 0>; + dma-names =3D "rx"; + clocks =3D <&ext_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad7606b"; + reg =3D <0>; + pwms =3D <&axi_pwm_gen 0 0>; + pwm-names =3D "convst1"; + avcc-supply =3D <&adc_vref>; + vdrive-supply =3D <&vdd_supply>; + reset-gpios =3D <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios =3D <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios =3D <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios =3D <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends =3D <¶llel_bus_controller>; + }; + }; ... --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD37E1D90A5 for ; Wed, 29 Jan 2025 11:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148707; cv=none; b=Jr2Bz5spI/kI+paFV3hylKxZUICRq55MVLGp8AlfHfCmZOjVS7w1O2AMHNg5AJKIdeqJVDbnG3/jtDAhm6XZjlKoCT3dflIFE8TegDEKOJBHrLjtUQjT9aRpY2fQNzhQacXdpAxJXusG0l9m5x/4cF4UMDbZ6yU4Q/VEn0xjaR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148707; c=relaxed/simple; bh=eeeG742/LDeOmZMMgJC+W4hlPYKRzBPb8KIQGlxLJKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c6KEjKLkgQpzgrjXc5B7Bh8ngdN4wHyuS6Qd3Ukd/8EPNRkV4sdheF8oQ13oL9fG7vgCHMP9fr/fafgvr8IH7Weq7oN0/SE+5LGq5BEQ+3BQ8S1oRPCaEQ7mLa9c+jPHG5r4EPA286soo43BYQMea1K26ciTSLkEdUYpIuY+sro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ctaK8n/c; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ctaK8n/c" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-3863703258fso345204f8f.1 for ; Wed, 29 Jan 2025 03:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148704; x=1738753504; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Cdc1cATkxj+NRQremP6tEug4vIFfF8rLsJGQkTSIG7w=; b=ctaK8n/cGXbZUQJsCsEeJAX1kstrN1ZAO4b+dRNxj9Bsm0Lt0hC9j+jlAdPbK7F99I JAe+aES1tFjFYG51ASECBQM+3qpKJGlbIPjyeRCYtDQ5KP5V3qhq37qKpLBJ3HQQz330 oJ9uWH4T8nbQkEuYDsdhAtu8Blp5am4lSKl8Y3u7YMUBsExsD51duhau+RsCUb2KlgVU YqYAFApmgnwjlUSVJF7ZgPE6pKUBoZr0OgG5zrnMkoFyX7NYVsCBJwKB7KlKPpUZe115 zuWoCHaDV/K+9P5EUJVQtUuKI6c8GoR5TRujlUgiUQ4yisberOTWVTxbMcT5gCmvKycm cJow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148704; x=1738753504; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cdc1cATkxj+NRQremP6tEug4vIFfF8rLsJGQkTSIG7w=; b=o+BiYvU9AMNl/FDg8MNIiVXwQkD/CdVXIr/Y1VMJKcqSfrfxgdwfPpPLGG5y7mb7OT H4nYzvOym1eQm74iIUKTMMGS8KhCczU0ZT00LybI7s+TsOo0+/whMGr2dDH76nElZQcJ Rxukk2l3d6apk3UQ6O/brNwfpHNJZnVUDlJtwFuormsxPK1g4k1b5P+FCw6ou1azlQ1u QuCdRW0NNI3tZ1/Tpq6QXaNt1zAe0adC3PfasslDFlPobZqS9fmpcIEnB4UN/G24eb8A fa5rjdeAS/D2O3I6vnjBLrRK/AGBtUi56Fhhy62aMpEsOAssarGNgG6pO5BSlMtPoQQm ZZEg== X-Forwarded-Encrypted: i=1; AJvYcCVZuURaepW1abnSYEVL//DPiJHaWC/pzlVdoFTbFVdP8uaPPuZiTOwWM7nGXU/GoLX4ncQKYpCjn/y8GgE=@vger.kernel.org X-Gm-Message-State: AOJu0Yz0Vd/KbMn0qkeSwGn9Uy/rdmdc+tpnSVDa/sNurPNfFEFBIBlu cJp3bCbwQirDCwfGE+P6spOzktbighV+gdKQBIviAb8otOd9QzNSjYFvDV5pEK8= X-Gm-Gg: ASbGncsTQA3GtM5Ez9NttMfnVk87DWvTB5FOItEPXb7Olh31Jhmme2RQua97TVHv9LO pjMhUZn+8LAUIA5UqQtnFx5YtDpbk3Bzc6Rvb8ux6uurSTfJZMwTIayCVGCfwBksY11CPUdoosu 4YclWuQ5MhaN/69wqPxNyih+wS3cVIRKsRnhjy7A0VT5WsKuI8Fl5lhKPh0NUIRpwWET2bNplKD vhGYfEEv9fy69NhZhaB3AnVWqemgdWjtGQ8USmsLITsYNsjJnqYmChybcBnvEUkwsgwtzOR+NSk rEix0iLw+BjxFax0NO6V25+Anfa11SfBu6CJFhcGm0HEQxzRj1imvOlukQseZNpJ0EcG/sc= X-Google-Smtp-Source: AGHT+IFaDLpWVjFWIu1Y+Qyim7g9TKgeSUYK0sY4eBsggvgAlH7UPWWj1NlDTMMXxX0rHSkDBiAViQ== X-Received: by 2002:a5d:6481:0:b0:386:34af:9bae with SMTP id ffacd0b85a97d-38c49a051c8mr5706558f8f.4.1738148703815; Wed, 29 Jan 2025 03:05:03 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:00 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:04 +0100 Subject: [PATCH v3 03/10] iio: adc: ad7606: fix wrong scale available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-3-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Fix wrong scale available list since only one value is returned: ... iio:device1: ad7606b (buffer capable) 8 channels found: voltage0: (input, index: 0, format: le:S16/16>>0) 2 channel-specific attributes found: attr 0: scale value: 0.305176 attr 1: scale_available value: 0.076293 Fix as: voltage0: (input, index: 0, format: le:S16/16>>0) 2 channel-specific attributes found: attr 0: scale value: 0.305176 attr 1: scale_available value: 0.076293 0.152588 0.305176 Fixes: 97c6d857041d ("iio: adc: ad7606: rework scale-available to be static= ") Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index d8e3c7a43678..d39354afd539 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -1047,7 +1047,7 @@ static int ad7606_read_avail(struct iio_dev *indio_de= v, =20 cs =3D &st->chan_scales[ch]; *vals =3D (int *)cs->scale_avail; - *length =3D cs->num_scales; + *length =3D cs->num_scales * 2; *type =3D IIO_VAL_INT_PLUS_MICRO; =20 return IIO_AVAIL_LIST; --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0CB81D90DB for ; Wed, 29 Jan 2025 11:05:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148710; cv=none; b=jrIrIu2p1u53oGcFCsnlPkv36Z4kIydMzdxVkz/pbDkjhxdAeZ7rk8fYfTNEO5fTqRlQSu0WjnM0Kcph2AuIO/0AVODZ08A7UtfzIqpmySaSv4gjJspc+Oxk5MxdDD0woWtoIVDAJVHbF54I0BXzVHF5P/LB7sApvk2pb1EmX+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148710; c=relaxed/simple; bh=dioqZv2txBsr2G2NsI3KTjuvSsHBK1WMQvxJwpSgCpc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PppkdLH4hDa6JRqI7ureRTS6wo/5W+DGDBwH8pqAkvoTJAqEcSyDNHKRMcZjjLS9X25ywUDm6wbDU2nb5iMBKfuTHzK18r/IOe9KnITR1XPbmnBL3DwYUBHqkKAZJ5Of1Az5HxQESmN4Bn7NTUyerM5PkTw2065phx7XvUxjUaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Bz4/49AJ; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Bz4/49AJ" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-385d7f19f20so3359834f8f.1 for ; Wed, 29 Jan 2025 03:05:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148707; x=1738753507; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wlrP600R/ci5wFmyR+m1ecPzb5qUkdneDDlwcUEYxOc=; b=Bz4/49AJauD3c1+DEMoSQiC3Xk7fs9jDbGBSu3wh7rpGRxNCqMJwGm7ju8Uh9SYXDR kEbg/tC1MnZZJWPFYjIMzyaoS0yhHrhy1TSjyg+BhZCGCwta12lRMEBtKkFP3T2FbDBw jfaEFSG6A1jYqCPOK587causGRetL2/mhatMG4uRoaQJizw4olV2GlrkoCkgad+PqfhM h6DK0uXNCF/nMUaXrMdCIUbB/MduVNd+F/bGbLI67v0xV5O1J/IYyNfuRxwumu45YH7+ MBcMC5NtFm1dunSlK9+99ugEgMDi3QSN7BqtXtKK9ljl2m5Q+CaVUiWOoxfzu250Rk4I PMiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148707; x=1738753507; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wlrP600R/ci5wFmyR+m1ecPzb5qUkdneDDlwcUEYxOc=; b=vCA7tbzCBOrS3u60LZNvSgMVrZtNpP5DESoDM1HiYLi8pAJ+izPBSAK4SPFLuTXAZA 1zUs3enkYtvRQ7VRpeayKbSZ62C5pudqYEKzLl4H9JvUjAyuYQO9Hl8HjV9e0UPglILN ZpSQmlYoXr9vnu97zkrK1jvMTDn79sQxQ7uwhv4nLVC/JlYJtgUaOCZ6p4jaFl4FmDNn J7NaA106zzsGFLr8cRXfNa/b4B9S2PaJ5U4Kgt8p/zGqdP2klWIXdbpeA47Z33R2FFy7 9yummf+TKLZR2QWp3GqsaOOHBqT1psez3fvGitHALxgjeM8+oQrn+Xafh7HCY7UCihEV MYAA== X-Forwarded-Encrypted: i=1; AJvYcCXX9pz9Q0GDwWSkPl/kGgu8UCzM9SbPSa00c1/FkF10Va4CFHtW9YELUOZpUQSEFS2v9KCoV6ssgdYhP9s=@vger.kernel.org X-Gm-Message-State: AOJu0YxBWwoszn1rKwjclTFo+7ELMcpaPQ6Y1YbRrJsIf5Tf9rmNyJSU 4ysHlycxP9WyopiW254do0XKzJsMCQjo3ofwLoSocBVdS9G5o8b1TljD/a20C6E= X-Gm-Gg: ASbGnctBs1zzzKc7apSloi1vH/bhkLSso1SMVTk3dF0bvuBMYHLOvsT1ohcazNXHcK2 dC7QmemkTtIYMsYS5bbuIT55SbN4AL0CLQahlt+3rIKxLGNjYp45W6Ov2wLLT4trpNWKN0zGrA2 VZOvm8q0vO+Ur2aprZnqQOB82NsBliosKvgipiO70eZWff1KIqmpJS1C/8UHZQF685AutQ7ZMIf HMxL2JNmSAK4IuNwy0KJowrskKNk1l3Mj9BHcqEzKBYuwYUAHfoKhB6RldeI4Jzbi4p1VWcgB4J TTszWX1DYni/VgmaQa2R54QjdjPtfWvJ8pCOyWhGMsF85COiyh/dtrGjKUgWzLSmKOHKQCk= X-Google-Smtp-Source: AGHT+IE2sAMHKOfuQ1fuQ2nuVuYnw/aDn5EAlessm0idPWhiV/TrPf3r9aU7XQvRQSZJ/cTuX/bYWw== X-Received: by 2002:a5d:6149:0:b0:386:373f:47c4 with SMTP id ffacd0b85a97d-38c520b0473mr1757557f8f.49.1738148706878; Wed, 29 Jan 2025 03:05:06 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:05 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:05 +0100 Subject: [PATCH v3 04/10] iio: adc: ad7606: move the software mode configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-4-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols This is a preparation for the intoduction of the sofware functions in the iio backend version of the driver. The software mode configuration must be executed once the channels are configured, and the number of channels is known. This is not the case before iio-backend's configuration is called, and iio backend version of the driver does not have a timestamp channel. Also the sw_mode_config callback is configured during the iio-backend configuration. For clarity purpose, I moved the entire block instead of just the concerned function calls. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index d39354afd539..376c808df11c 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -1246,17 +1246,6 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, return -ERESTARTSYS; } =20 - st->write_scale =3D ad7606_write_scale_hw; - st->write_os =3D ad7606_write_os_hw; - - ret =3D ad7606_sw_mode_setup(indio_dev); - if (ret) - return ret; - - ret =3D ad7606_chan_scales_setup(indio_dev); - if (ret) - return ret; - /* If convst pin is not defined, setup PWM. */ if (!st->gpio_convst) { st->cnvst_pwm =3D devm_pwm_get(dev, NULL); @@ -1334,6 +1323,17 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, return ret; } =20 + st->write_scale =3D ad7606_write_scale_hw; + st->write_os =3D ad7606_write_os_hw; + + ret =3D ad7606_sw_mode_setup(indio_dev); + if (ret) + return ret; + + ret =3D ad7606_chan_scales_setup(indio_dev); + if (ret) + return ret; + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606"); --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F2441D90A5 for ; Wed, 29 Jan 2025 11:05:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148713; cv=none; b=JJw+SiWcP1ZMXqiuw56aXtRurkAsNrIqm4G7unciVCvZfcU8pQKsgScGd/otbuVQBAaA2URxJLbkctlx8Pw7kiK1BI6f787iVJlDhUbOXro1KZ2nXv4Lp/nlUd8JBiN/ARjGKe3nDqQ+x46l+zVT+phpwGhORw945kOXF++wEaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148713; c=relaxed/simple; bh=85OlqVH97K7F9YU3PJts40Anjk8hAqk1vgt8dqfrDhg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gV2JLb57i7tTw0MKdbPPNxuLqEAzI49gToVRWYU//M0atCaBXgOTjYTAeeeGdCPoJhdc+DFc7ttHw8jlz8qm42rvktf0r1Gpa3T6afVA1A8iC8XcljIWfb6vjDsV6J5XI6QH88SJ7/DZjN4YVPHhiHvXOIl6OriVhK9oC+GI8K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Dhuos5mH; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Dhuos5mH" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-385e3621518so3499339f8f.1 for ; Wed, 29 Jan 2025 03:05:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148710; x=1738753510; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pHAR9w6iE1kUg7TAE0D6ak7vDA8Cy7dNc7XiaEG+akw=; b=Dhuos5mHGVy/ZK6SvHApGYKxSxGLAotbK9tcMRMzgzeHAEWQXyWSK8bHZY7vP456kE vYj1Q06rp+PmusR1O7XrvBraiZvbToQvYvcH9BS/qc6bdITe7wUeYy5pdCCuQd0dqeo4 WjSYtpSjtHQzjFHLvZ8AU0IIQIbyxO9CFZUoP3NJYs2TCDg5z8t4h7D2lQa+tejYrJUu FiTQ8pcQgYiyTd0g5H2/K7c65zf0I1cmzdo0CxGv2ScD1fjuxqxYyfdRD1F2cpX+xtvT m17MyI3Exz69QsNLO6dSFAi4b2v85nfHNrXCguy0DMRwb/5l39IXwh5X7+JZPoKCLWNu a4Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148710; x=1738753510; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pHAR9w6iE1kUg7TAE0D6ak7vDA8Cy7dNc7XiaEG+akw=; b=RCXrPLW6nlL1ZC+3a2EquYRh63OBfqI6NuedlVsDMK6m6R7tbb/baAh2p5sT0rdGPH Bo7CmezG7fXGcwjF+/4160FZXSdYl0GGojc88gKGQQRo6uKkjoKlqhmTOZRmJeiJhZcn hJ6lPKYH8wvmcdFLsO75SExmgBUCoN8LIm6cl7PWdSgwwIb7aHgevKCrEpeZRQuLh0L1 RoNPsyA18gf/skpFDSs3H7hspnjOg8ykedECytv6UF5v6+H5ubkh+rrobH5Aa/UcWY2Q XgPacA3D6/6HgjBq2KdOiFI6KNcC0Vpjo4GqSV5bIMtcpVGho6afaxMaeIRGwbna3tTA E+Yw== X-Forwarded-Encrypted: i=1; AJvYcCVdx4iYzajiF4WUHnXPp8pUxcVv9f3imR/8SknOaHMcn4V91t2tSjfTk/kTuenu/XtOuIgRB9Bh/+h+H7k=@vger.kernel.org X-Gm-Message-State: AOJu0YxN+ZQiCIri3NAOGLz/1ehEB7VEY6+qQEQzPnj43TUW20zLk7od m7ublHe9qrgu8VWwnjax2YAEQd0SxFUtyWntkDCMtwCk5mrRe2RtTecLPt/VC5Q= X-Gm-Gg: ASbGncuM0LhJ8RR3N8NN3FCv5skYP5w/R2C0lV28qIgMarowgRqYs690kIxYDtBnLCE StDUReAz+5Ru8EJ5ALsIhBHaF3mSmYqHPA9vh9MeQjBAFu9MyQv00ug0s920Q3hV/pn4QP5xsQP vi4uLEWveKV1hoaxW8J7uO6l01Rzt15rCT6rcaOj10io/Mmq94Nna3Xi2v7rmAlYpvznx9/qfaa QNeHT5UUnYsI2wdc5ItOOogDttFKjLGN1Z75vmboFtZ6SKXcErLooEf1X2YPORaPmFUMv+KzVZz nw/fHjWjDR/CUec2TDL15Lm0zoW48EYQsiqbU7BFjYBgSotZurSNGCu439tHU4FS96KNV4k= X-Google-Smtp-Source: AGHT+IFnISRAdIOu2I025O7IEY3zw9Th1g5UVnXU5gSxkPBoqoRfUsE5SpFijUzs9cafLVfb91opuQ== X-Received: by 2002:a05:6000:4013:b0:385:f631:612 with SMTP id ffacd0b85a97d-38c5195f2e5mr2251088f8f.17.1738148709667; Wed, 29 Jan 2025 03:05:09 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:08 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:06 +0100 Subject: [PATCH v3 05/10] iio: adc: ad7606: move software functions into common file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-5-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols Since the register are always the same, whatever bus is used, moving the software functions into the main file avoids the code to be duplicated in both SPI and parallel version of the driver. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 133 ++++++++++++++++++++++++++++++++++++++-= -- drivers/iio/adc/ad7606.h | 37 ++++++++++-- drivers/iio/adc/ad7606_spi.c | 137 +--------------------------------------= ---- 3 files changed, 158 insertions(+), 149 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 376c808df11c..7985570ed152 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -85,6 +85,10 @@ static const unsigned int ad7606_oversampling_avail[7] = =3D { 1, 2, 4, 8, 16, 32, 64, }; =20 +static const unsigned int ad7606b_oversampling_avail[9] =3D { + 1, 2, 4, 8, 16, 32, 64, 128, 256, +}; + static const unsigned int ad7616_oversampling_avail[8] =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; @@ -187,6 +191,8 @@ static int ad7608_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan, int ch); static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); +static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); =20 const struct ad7606_chip_info ad7605_4_info =3D { .channels =3D ad7605_channels, @@ -239,6 +245,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -250,6 +257,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -294,6 +302,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .oversampling_avail =3D ad7606_oversampling_avail, .oversampling_num =3D ARRAY_SIZE(ad7606_oversampling_avail), .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, + .sw_setup_cb =3D ad7606b_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -307,6 +316,7 @@ const struct ad7606_chip_info ad7616_info =3D { .oversampling_num =3D ARRAY_SIZE(ad7616_oversampling_avail), .os_req_reset =3D true, .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, + .sw_setup_cb =3D ad7616_sw_mode_setup, }; EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606"); =20 @@ -1138,16 +1148,118 @@ static const struct iio_trigger_ops ad7606_trigger= _ops =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) +static int ad7606_write_mask(struct ad7606_state *st, unsigned int addr, + unsigned long mask, unsigned int val) +{ + int readval; + + readval =3D st->bops->reg_read(st, addr); + if (readval < 0) + return readval; + + readval &=3D ~mask; + readval |=3D val; + + return st->bops->reg_write(st, addr, readval); +} + +static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int ch_addr, mode, ch_index; =20 - st->sw_mode_en =3D st->bops->sw_mode_config && - device_property_present(st->dev, "adi,sw-mode"); - if (!st->sw_mode_en) - return 0; + /* + * Ad7616 has 16 channels divided in group A and group B. + * The range of channels from A are stored in registers with address 4 + * while channels from B are stored in register with address 6. + * The last bit from channels determines if it is from group A or B + * because the order of channels in iio is 0A, 0B, 1A, 1B... + */ + ch_index =3D ch >> 1; + + ch_addr =3D AD7616_RANGE_CH_ADDR(ch_index); + + if ((ch & 0x1) =3D=3D 0) /* channel A */ + ch_addr +=3D AD7616_RANGE_CH_A_ADDR_OFF; + else /* channel B */ + ch_addr +=3D AD7616_RANGE_CH_B_ADDR_OFF; + + /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ + mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); =20 - indio_dev->info =3D &ad7606_info_sw_mode; + return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), + mode); +} + +static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + AD7616_OS_MASK, val << 2); +} + +static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return ad7606_write_mask(st, AD7606_RANGE_CH_ADDR(ch), + AD7606_RANGE_CH_MSK(ch), + AD7606_RANGE_CH_MODE(ch, val)); +} + +static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + + return st->bops->reg_write(st, AD7606_OS_MODE, val); +} + +static int ad7616_sw_mode_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + int ret; + + /* + * Scale can be configured individually for each channel + * in software mode. + */ + + st->write_scale =3D ad7616_write_scale_sw; + st->write_os =3D &ad7616_write_os_sw; + + ret =3D st->bops->sw_mode_config(indio_dev); + if (ret) + return ret; + + /* Activate Burst mode and SEQEN MODE */ + return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + AD7616_BURST_MODE | AD7616_SEQEN_MODE, + AD7616_BURST_MODE | AD7616_SEQEN_MODE); +} + +static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + DECLARE_BITMAP(os, 3); + + bitmap_fill(os, 3); + /* + * Software mode is enabled when all three oversampling + * pins are set to high. If oversampling gpios are defined + * in the device tree, then they need to be set to high, + * otherwise, they must be hardwired to VDD + */ + if (st->gpio_os) { + gpiod_set_array_value(st->gpio_os->ndescs, st->gpio_os->desc, + st->gpio_os->info, os); + } + /* OS of 128 and 256 are available only in software mode */ + st->oversampling_avail =3D ad7606b_oversampling_avail; + st->num_os_ratios =3D ARRAY_SIZE(ad7606b_oversampling_avail); + + st->write_scale =3D ad7606_write_scale_sw; + st->write_os =3D &ad7606_write_os_sw; =20 return st->bops->sw_mode_config(indio_dev); } @@ -1326,9 +1438,12 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, st->write_scale =3D ad7606_write_scale_hw; st->write_os =3D ad7606_write_os_hw; =20 - ret =3D ad7606_sw_mode_setup(indio_dev); - if (ret) - return ret; + st->sw_mode_en =3D st->chip_info->sw_setup_cb && + device_property_present(st->dev, "adi,sw-mode"); + if (st->sw_mode_en) { + indio_dev->info =3D &ad7606_info_sw_mode; + st->chip_info->sw_setup_cb(indio_dev); + } =20 ret =3D ad7606_chan_scales_setup(indio_dev); if (ret) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 8778ffe515b3..7a044b499cfe 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -10,6 +10,36 @@ =20 #define AD760X_MAX_CHANNELS 16 =20 +#define AD7616_CONFIGURATION_REGISTER 0x02 +#define AD7616_OS_MASK GENMASK(4, 2) +#define AD7616_BURST_MODE BIT(6) +#define AD7616_SEQEN_MODE BIT(5) +#define AD7616_RANGE_CH_A_ADDR_OFF 0x04 +#define AD7616_RANGE_CH_B_ADDR_OFF 0x06 +/* + * Range of channels from a group are stored in 2 registers. + * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. + * For channels from second group(8-15) the order is the same, only with + * an offset of 2 for register address. + */ +#define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) +/* The range of the channel is stored in 2 bits */ +#define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) +#define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) + +#define AD7606_CONFIGURATION_REGISTER 0x02 +#define AD7606_SINGLE_DOUT 0x00 + +/* + * Range for AD7606B channels are stored in registers starting with addres= s 0x3. + * Each register stores range for 2 channels(4 bits per channel). + */ +#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) +#define AD7606_RANGE_CH_MODE(ch, mode) \ + ((GENMASK(3, 0) & (mode)) << (4 * ((ch) & 0x1))) +#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) +#define AD7606_OS_MODE 0x08 + #define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, bits) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -71,6 +101,7 @@ struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan, int ch); +typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); =20 /** * struct ad7606_chip_info - chip specific information @@ -80,6 +111,7 @@ typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *i= ndio_dev, * @num_channels: number of channels * @num_adc_channels the number of channels the ADC actually inputs. * @scale_setup_cb: callback to setup the scales for each channel + * @sw_setup_cb: callback to setup the software mode if available. * @oversampling_avail pointer to the array which stores the available * oversampling ratios. * @oversampling_num number of elements stored in oversampling_avail array @@ -94,6 +126,7 @@ struct ad7606_chip_info { unsigned int num_adc_channels; unsigned int num_channels; ad7606_scale_setup_cb_t scale_setup_cb; + ad7606_sw_setup_cb_t sw_setup_cb; const unsigned int *oversampling_avail; unsigned int oversampling_num; bool os_req_reset; @@ -206,10 +239,6 @@ struct ad7606_bus_ops { int (*reg_write)(struct ad7606_state *st, unsigned int addr, unsigned int val); - int (*write_mask)(struct ad7606_state *st, - unsigned int addr, - unsigned long mask, - unsigned int val); int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *s= can_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index e2c147525706..885bf0b68e77 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -15,36 +15,6 @@ =20 #define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */ =20 -#define AD7616_CONFIGURATION_REGISTER 0x02 -#define AD7616_OS_MASK GENMASK(4, 2) -#define AD7616_BURST_MODE BIT(6) -#define AD7616_SEQEN_MODE BIT(5) -#define AD7616_RANGE_CH_A_ADDR_OFF 0x04 -#define AD7616_RANGE_CH_B_ADDR_OFF 0x06 -/* - * Range of channels from a group are stored in 2 registers. - * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. - * For channels from second group(8-15) the order is the same, only with - * an offset of 2 for register address. - */ -#define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) -/* The range of the channel is stored in 2 bits */ -#define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) -#define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) - -#define AD7606_CONFIGURATION_REGISTER 0x02 -#define AD7606_SINGLE_DOUT 0x00 - -/* - * Range for AD7606B channels are stored in registers starting with addres= s 0x3. - * Each register stores range for 2 channels(4 bits per channel). - */ -#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) -#define AD7606_RANGE_CH_MODE(ch, mode) \ - ((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1))) -#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) -#define AD7606_OS_MODE 0x08 - static const struct iio_chan_spec ad7616_sw_channels[] =3D { IIO_CHAN_SOFT_TIMESTAMP(16), AD7616_CHANNEL(0), @@ -89,10 +59,6 @@ static const struct iio_chan_spec ad7606c_18_sw_channels= [] =3D { AD7606_SW_CHANNEL(7, 18), }; =20 -static const unsigned int ad7606B_oversampling_avail[9] =3D { - 1, 2, 4, 8, 16, 32, 64, 128, 256 -}; - static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp) { /* @@ -194,118 +160,20 @@ static int ad7606_spi_reg_write(struct ad7606_state = *st, return spi_write(spi, &st->d16[0], sizeof(st->d16[0])); } =20 -static int ad7606_spi_write_mask(struct ad7606_state *st, - unsigned int addr, - unsigned long mask, - unsigned int val) -{ - int readval; - - readval =3D st->bops->reg_read(st, addr); - if (readval < 0) - return readval; - - readval &=3D ~mask; - readval |=3D val; - - return st->bops->reg_write(st, addr, readval); -} - -static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - unsigned int ch_addr, mode, ch_index; - - - /* - * Ad7616 has 16 channels divided in group A and group B. - * The range of channels from A are stored in registers with address 4 - * while channels from B are stored in register with address 6. - * The last bit from channels determines if it is from group A or B - * because the order of channels in iio is 0A, 0B, 1A, 1B... - */ - ch_index =3D ch >> 1; - - ch_addr =3D AD7616_RANGE_CH_ADDR(ch_index); - - if ((ch & 0x1) =3D=3D 0) /* channel A */ - ch_addr +=3D AD7616_RANGE_CH_A_ADDR_OFF; - else /* channel B */ - ch_addr +=3D AD7616_RANGE_CH_B_ADDR_OFF; - - /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ - mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); - return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), - mode); -} - -static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER, - AD7616_OS_MASK, val << 2); -} - -static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_spi_write_mask(st, - AD7606_RANGE_CH_ADDR(ch), - AD7606_RANGE_CH_MSK(ch), - AD7606_RANGE_CH_MODE(ch, val)); -} - -static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) -{ - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_spi_reg_write(st, AD7606_OS_MODE, val); -} - static int ad7616_sw_mode_config(struct iio_dev *indio_dev) { - struct ad7606_state *st =3D iio_priv(indio_dev); - /* * Scale can be configured individually for each channel * in software mode. */ indio_dev->channels =3D ad7616_sw_channels; =20 - st->write_scale =3D ad7616_write_scale_sw; - st->write_os =3D &ad7616_write_os_sw; - - /* Activate Burst mode and SEQEN MODE */ - return st->bops->write_mask(st, - AD7616_CONFIGURATION_REGISTER, - AD7616_BURST_MODE | AD7616_SEQEN_MODE, - AD7616_BURST_MODE | AD7616_SEQEN_MODE); + return 0; } =20 static int ad7606B_sw_mode_config(struct iio_dev *indio_dev) { struct ad7606_state *st =3D iio_priv(indio_dev); - DECLARE_BITMAP(os, 3); - - bitmap_fill(os, 3); - /* - * Software mode is enabled when all three oversampling - * pins are set to high. If oversampling gpios are defined - * in the device tree, then they need to be set to high, - * otherwise, they must be hardwired to VDD - */ - if (st->gpio_os) { - gpiod_set_array_value(st->gpio_os->ndescs, - st->gpio_os->desc, st->gpio_os->info, os); - } - /* OS of 128 and 256 are available only in software mode */ - st->oversampling_avail =3D ad7606B_oversampling_avail; - st->num_os_ratios =3D ARRAY_SIZE(ad7606B_oversampling_avail); - - st->write_scale =3D ad7606_write_scale_sw; - st->write_os =3D &ad7606_write_os_sw; =20 /* Configure device spi to output on a single channel */ st->bops->reg_write(st, @@ -350,7 +218,6 @@ static const struct ad7606_bus_ops ad7616_spi_bops =3D { .read_block =3D ad7606_spi_read_block, .reg_read =3D ad7606_spi_reg_read, .reg_write =3D ad7606_spi_reg_write, - .write_mask =3D ad7606_spi_write_mask, .rd_wr_cmd =3D ad7616_spi_rd_wr_cmd, .sw_mode_config =3D ad7616_sw_mode_config, }; @@ -359,7 +226,6 @@ static const struct ad7606_bus_ops ad7606b_spi_bops =3D= { .read_block =3D ad7606_spi_read_block, .reg_read =3D ad7606_spi_reg_read, .reg_write =3D ad7606_spi_reg_write, - .write_mask =3D ad7606_spi_write_mask, .rd_wr_cmd =3D ad7606B_spi_rd_wr_cmd, .sw_mode_config =3D ad7606B_sw_mode_config, }; @@ -368,7 +234,6 @@ static const struct ad7606_bus_ops ad7606c_18_spi_bops = =3D { .read_block =3D ad7606_spi_read_block18to32, .reg_read =3D ad7606_spi_reg_read, .reg_write =3D ad7606_spi_reg_write, - .write_mask =3D ad7606_spi_write_mask, .rd_wr_cmd =3D ad7606B_spi_rd_wr_cmd, .sw_mode_config =3D ad7606c_18_sw_mode_config, }; --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6F091BC062 for ; Wed, 29 Jan 2025 11:05:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148716; cv=none; b=ZHr+IJ1LLmmcmPFJ8ayke0f7SY48y8Bt6uxKJzlWPQHUQ5DPkYnsnaXUPLl00QQCSy84rwBEUqfLvdoRf4eoyErY0nC6gCdkLcVS9sS6ltcJV4LmKWQA0o+LytMImo3gbV86uXBixjqtVOMQIl/dU4fCZeiced51M8tBOhfLVG8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148716; c=relaxed/simple; bh=mPqWiYHTVbxQ1ZYyr5/FMNCEArrrEDwzZrloBMMEgyA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qnqTkQqi1oayCWoANWaqCsjOPoFIg2lHgVM0UsIF0Qw5hLnSezxitXMVVlhJahDoetVd+pKFli8w8DRsOM/638u/94YhE4rWzB7N8tyj/TRbRrAkvYvQId8Vi3XBaCGDztgezBVAYfesqUS2TbyJgO90IaihEQaoZOMI3aLAnZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=hg8dbtUs; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="hg8dbtUs" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-386329da1d9so3521942f8f.1 for ; Wed, 29 Jan 2025 03:05:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148713; x=1738753513; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oB16y1gR9CriA2xIIhmFJG7RqN1ERbrsdfXmfj1Q/Eg=; b=hg8dbtUs3ej2s8+8uDCPZP696mOFtiureoxZPRDgnZFG+3poUzQF8iua9CSF8unCT1 hAREj16yyzC4B9Ox5DiC/1W6Ooh8vGxpMLmI/ko2BvkED6xuOW8cZMC/z68GXSg8UoI/ 8ckm6diKfkBe3CtnebTVNcsCG1XRnNFkB/Lc/V8WabSSdo0Z/rmZjdvOpqK+GFNt5DzQ kLhGAqT+c4/2yb1Fu++S0yRmi5m7ocwUPFfEP4r0ddtTWCQavwgewzhdqvJIj39WU+no 7oBN3DFGZdtnmL/GO/tTcU58bAZIZa0Toa7QqHVGwcExHsOwJE1oY9dvr6vnHpnHCgla yorA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148713; x=1738753513; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oB16y1gR9CriA2xIIhmFJG7RqN1ERbrsdfXmfj1Q/Eg=; b=As5q42zJeOpL7c8g3vhYH9eIL8DuDeyOZ48zC5IrmCeMFN8pSb7qupTMotYxte0N4/ 2atJ0rFyhOJCSnMFri9AvtmQhDrXUXJvYgWO6bPkRrfIZJHPiIgIOCdHc/QuJkQrOOGK wnTdCy+uQLs76uJ7BgAKoM1i8cFVvaDxPfhCtbKygaQdJl5zkXO/lxJV+bCf9uk7PYLJ UGwE0drLjZlLzHhphz7eSu7knasVFxBJ+anQHiITfY7yVH7hsiHbL9RmkDRciKdSBt76 +Wa4A3g3k8zyKt3hZEoThBgeiMTCCh4CjN6p9DkvvuZsf3thhaENmlU+TEw/BhiS8CNW M8nQ== X-Forwarded-Encrypted: i=1; AJvYcCXQzA/GwPLvqP0UoSdHPVnQukPnf8KabsCAcwrIpz7D3tv3fF9z0CIrMJM3gmabq7L4x2z3BgmKPWwOrO4=@vger.kernel.org X-Gm-Message-State: AOJu0YzXQCv2joLrnDtcORteIs/oT/miiPwjDxXSPNjp7ZLpJBy8Tsp1 DN5IH5+V6KopLuPTkZfbsycsEH+pkiS9E05pfqOZSlp1tsBViQpmYMXnjTXTc9s= X-Gm-Gg: ASbGnct/gjoaj58dJYpqN3zV9Yf6hdFs/iSFfJ+C35IfEcsNBTv3zLJpQ3b4dZ3K757 KDEtMsVir5UlXFug09Ko3cnqkrJ5LLmxaHeTe3CMNQJvk3q1zcbJHWJhkJcnqAw9GrQjCiTvf9q +13q4tp6hARA9PbF3QVoe2PRu47ykx5Tgx2j5R8u7y0JfHUmRhNuPkg4kfOJ5CZEm4B6XCgPJEj J8xJl+OFxQ1RG5jXLtfxFZMzye1xgDMr7wr2Jh37y6Db9Q24zcSMmWluvFmesrHVv4HP8wh+Zg1 8d7j26XkBv3dz7OQBVbeXSKN7dPpX0fUPvkKyfnFkc32wyvjqpHoBmwLV+di+AhCdF3NmDY= X-Google-Smtp-Source: AGHT+IE2fvUTplc629GXhMiYkYYmY7/ekjLGkd6x/Utm4fEUGlUkylM4nyLFo8l3fkyBWJPLc/U7HQ== X-Received: by 2002:a05:6000:1a41:b0:38c:1281:260d with SMTP id ffacd0b85a97d-38c51b5ee9fmr1571798f8f.31.1738148712977; Wed, 29 Jan 2025 03:05:12 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:11 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:07 +0100 Subject: [PATCH v3 06/10] iio: adc: adi-axi-adc: add platform children support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-6-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols This is a preparation for the next commit adding support for register read and write functions on AD7606. Since sometimes a bus will be used, it has been agreed during ad3552's driver implementation that the device's driver bus is the backend, whose device node will be a child node. To provide the special callbacks for setting the register, axi-adc needs to pass them to the child device's driver through platform data. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606_bus_iface.h | 16 ++++++++ drivers/iio/adc/adi-axi-adc.c | 84 ++++++++++++++++++++++++++++++++++= ---- 2 files changed, 91 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad7606_bus_iface.h b/drivers/iio/adc/ad7606_bu= s_iface.h new file mode 100644 index 000000000000..d8d39822e2a9 --- /dev/null +++ b/drivers/iio/adc/ad7606_bus_iface.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2010-2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre, SAS + */ +#ifndef __LINUX_PLATFORM_DATA_AD7606_H__ +#define __LINUX_PLATFORM_DATA_AD7606_H__ + +struct iio_backend; + +struct ad7606_platform_data { + int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val); + int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val); +}; + +#endif /* __LINUX_PLATFORM_DATA_AD7606_H__ */ diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index c7357601f0f8..0923565cf5bb 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -80,7 +80,18 @@ ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ ADI_AXI_REG_CHAN_CTRL_ENABLE) =20 +struct axi_adc_info { + unsigned int version; + const struct iio_backend_info *backend_info; + bool bus_controller; + const void *pdata; + unsigned int pdata_sz; +}; + struct adi_axi_adc_state { + /* Target ADC platform device */ + struct platform_device *adc_pdev; + const struct axi_adc_info *info; struct regmap *regmap; struct device *dev; /* lock to protect multiple accesses to the device registers */ @@ -325,6 +336,38 @@ static const struct regmap_config axi_adc_regmap_confi= g =3D { .reg_stride =3D 4, }; =20 +static void axi_adc_child_remove(void *data) +{ + platform_device_unregister(data); +} + +static int axi_adc_create_platform_device(struct adi_axi_adc_state *st, + struct fwnode_handle *child) +{ + struct platform_device_info pi =3D { + .parent =3D st->dev, + .name =3D fwnode_get_name(child), + .id =3D PLATFORM_DEVID_AUTO, + .fwnode =3D child, + .data =3D st->info->pdata, + .size_data =3D st->info->pdata_sz, + }; + struct platform_device *pdev; + int ret; + + pdev =3D platform_device_register_full(&pi); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + ret =3D devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev); + if (ret) + return ret; + + st->adc_pdev =3D pdev; + + return 0; +} + static const struct iio_backend_ops adi_axi_adc_ops =3D { .enable =3D axi_adc_enable, .disable =3D axi_adc_disable, @@ -348,7 +391,6 @@ static const struct iio_backend_info adi_axi_adc_generi= c =3D { =20 static int adi_axi_adc_probe(struct platform_device *pdev) { - const unsigned int *expected_ver; struct adi_axi_adc_state *st; void __iomem *base; unsigned int ver; @@ -370,8 +412,8 @@ static int adi_axi_adc_probe(struct platform_device *pd= ev) return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap), "failed to init register map\n"); =20 - expected_ver =3D device_get_match_data(&pdev->dev); - if (!expected_ver) + st->info =3D device_get_match_data(&pdev->dev); + if (!st->info) return -ENODEV; =20 clk =3D devm_clk_get_enabled(&pdev->dev, NULL); @@ -391,12 +433,13 @@ static int adi_axi_adc_probe(struct platform_device *= pdev) if (ret) return ret; =20 - if (ADI_AXI_PCORE_VER_MAJOR(ver) !=3D ADI_AXI_PCORE_VER_MAJOR(*expected_v= er)) { + if (ADI_AXI_PCORE_VER_MAJOR(ver) !=3D + ADI_AXI_PCORE_VER_MAJOR(st->info->version)) { dev_err(&pdev->dev, "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", - ADI_AXI_PCORE_VER_MAJOR(*expected_ver), - ADI_AXI_PCORE_VER_MINOR(*expected_ver), - ADI_AXI_PCORE_VER_PATCH(*expected_ver), + ADI_AXI_PCORE_VER_MAJOR(st->info->version), + ADI_AXI_PCORE_VER_MINOR(st->info->version), + ADI_AXI_PCORE_VER_PATCH(st->info->version), ADI_AXI_PCORE_VER_MAJOR(ver), ADI_AXI_PCORE_VER_MINOR(ver), ADI_AXI_PCORE_VER_PATCH(ver)); @@ -408,6 +451,26 @@ static int adi_axi_adc_probe(struct platform_device *p= dev) return dev_err_probe(&pdev->dev, ret, "failed to register iio backend\n"); =20 + if (st->info->bus_controller) { + device_for_each_child_node_scoped(&pdev->dev, child) { + int val; + + /* Processing only reg 0 node */ + ret =3D fwnode_property_read_u32(child, "reg", &val); + if (ret || val !=3D 0) + continue; + + ret =3D fwnode_property_read_u32(child, "io-backends", + &val); + if (ret) + continue; + + ret =3D axi_adc_create_platform_device(st, child); + if (ret) + return ret; + } + } + dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", ADI_AXI_PCORE_VER_MAJOR(ver), ADI_AXI_PCORE_VER_MINOR(ver), @@ -416,11 +479,14 @@ static int adi_axi_adc_probe(struct platform_device *= pdev) return 0; } =20 -static unsigned int adi_axi_adc_10_0_a_info =3D ADI_AXI_PCORE_VER(10, 0, '= a'); +static const struct axi_adc_info adc_generic =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &adi_axi_adc_generic, +}; =20 /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { - { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adi_axi_adc_10_0_a_inf= o }, + { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, { /* end of list */ } }; MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6431DE2B2 for ; Wed, 29 Jan 2025 11:05:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148718; cv=none; b=Kie/uuSnyesJMWw5m6aOJOMu7eUbg3leBOVRAdiQ70TQYcdoZvsLk7H1fQRfhglUzI5OqWP3mQ/OUdYxE+t317IL9/sxBgcmZCxYEPB32NY7hRp9LRARbNTF/20tKwegiqPUw20DASJqWNXm2knaCy5ylOs8bizKATAo1MoGjVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148718; c=relaxed/simple; bh=waFUc7Y98lVcelQdxEeSHTjUKlAPBIkUFiT/B2RzsUU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ObZm2Tarzb3mHJcV7LdqSuTm7wWddxp1ydwfikt7SWrpjgQMG4C8TyKmqy7r97j2OxCLjmObt0TR157aJ0/ZTi2vtvnkK2ujcYPmHNpw0f1BeV7P9FSqY66j/dHoU54DPxnWEhaxuiwvV7e2GNepUQhrIQlxaq/REdvz3LQs35U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=hWNvhJ7W; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="hWNvhJ7W" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-385de59c1a0so3878501f8f.2 for ; Wed, 29 Jan 2025 03:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148715; x=1738753515; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=joYblRHTZ8apOwpe6Vq3h7ChVrXqa2XFvM8jV4cZmtQ=; b=hWNvhJ7Wwm0y4WZjdosXn3Jmv+rz6z4noxChVoP1HEk3gw8Js0NGg3RtbsmhJ4pK/R NHaYH5sZaBZ2PaW/LbDAyYxkq71i9OQaTScUgZHA1ZWNUKPZOWTfsie850urmd2ygVpb MCBn92cTES43QLAml3xWzDsEaPvzaKyr48m3ZDbtTeWfYyF3WZFyRQt0UF+uIDWnr7gd BwIxt3CLQSgRyX53Xgvtb76IoZins+wnsjeTABR19JFljJPXhkE8vgpQMz3RcnWIwyMX NLXMNAyNgIPMgxh0N9VT6hw1/IOtAW15jVDQBUamAGzStYaFigR3L3BbYoUgfrROOCi8 AqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148715; x=1738753515; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=joYblRHTZ8apOwpe6Vq3h7ChVrXqa2XFvM8jV4cZmtQ=; b=qNHwr2UDQh6N2/Ax9cavygufKVtAO0CJDsyuRPWns7QfJGKFtrJlK3b4jyLcra1M01 JHfo0vKG/rf6B3beebqqG/KOlEHdKaqn28xDv5s6nbdHyEUUIRpJBnYdazBi0CZD39g5 5tjSbFgKJJLmK3OZ+ZRYJZ6855id/+cYFrHpkm45hy8PgRrNqYmxif+3C8ZzvMSwppvA KQL4H6yyIvyTx9P0oHVnMBC2u927tk0GfNFjyxZsE4swJJ4SLewKoPAQQFZphFaJvShf 6SMkjYbjVQ7uWv+l9ZwhxM1vzWOqMv6FDivDtAO1chtIXjOVKo+GTwbnGryXcKeuz2i+ GKNg== X-Forwarded-Encrypted: i=1; AJvYcCUsWJGQdBqHhmS4UPcgJ8FtxnqRKo2bBH43jMcCt426+x1zjM1R+ilDoXmOK21FFh5qx63T0nxOd00tfNs=@vger.kernel.org X-Gm-Message-State: AOJu0YxXaOFSWXtIcTPTV0elhtZ1SxCnpxeucyQL6sVnKickII6Ykv45 R8klgz4WUCeTiy/GQZC4jYASfZH3cmrZnW+72MqMK3XwjdJ/fy3OpeEpgjsQhZs= X-Gm-Gg: ASbGncutS2GszEtiHTm6+mGNyrs0cFWh3zY4YWd+TCYv7mT0vqmWKaTwed3PKeXY/3H rSf4ga1bKPhs0I+zNtCjsrBNhIzNahYJYfa579iasgWIGxtq33I0kuBf2B6FK7acOtsjAljoVvE dra3jYAYZPV0mdi+WcUUcdFH/fLeXqC4OFysh0/flbOenngpbUz2P469sZdXcOpw6D5LDDMBibA HIrbjRP67+Ok4zD8dVE3dX9jbXYbNLA7jC91N96zytXdvXvEE/iL2949XL57umsIfnP/Xz4z6aB ArTP7FeyJP2Gj8YQROIEMI4yebdvrnxsFSJNOS6CUKpbg0Z1TviMiebElYhHsTlKl/gfYBU= X-Google-Smtp-Source: AGHT+IHiMbOiYeOXFJU+/sYQ6d/SHusLAP//Q35lqgWeMJj2FLezKvdhAFo4grov+EgNrSzdFbLeRA== X-Received: by 2002:a5d:47c9:0:b0:38b:da31:3e3c with SMTP id ffacd0b85a97d-38c5194c567mr1967009f8f.20.1738148714791; Wed, 29 Jan 2025 03:05:14 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:14 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:08 +0100 Subject: [PATCH v3 07/10] iio: adc: adi-axi-adc: add support for AD7606 register writing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-7-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols Since we must access the bus parallel bus using a custom procedure, let's add a specialized compatible, and define specialized callbacks for writing the registers using the parallel interface. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- drivers/iio/adc/adi-axi-adc.c | 100 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 0923565cf5bb..aaeb445a8a3e 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -27,6 +27,7 @@ #include #include =20 +#include "ad7606_bus_iface.h" /* * Register definitions: * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map @@ -73,6 +74,12 @@ #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) =20 +#define ADI_AXI_REG_CONFIG_WR 0x0080 +#define ADI_AXI_REG_CONFIG_RD 0x0084 +#define ADI_AXI_REG_CONFIG_CTRL 0x008c +#define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 +#define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 + #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 =20 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ @@ -80,6 +87,10 @@ ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ ADI_AXI_REG_CHAN_CTRL_ENABLE) =20 +#define ADI_AXI_REG_READ_BIT 0x8000 +#define ADI_AXI_REG_ADDRESS_MASK 0xff00 +#define ADI_AXI_REG_VALUE_MASK 0x00ff + struct axi_adc_info { unsigned int version; const struct iio_backend_info *backend_info; @@ -313,6 +324,81 @@ static struct iio_buffer *axi_adc_request_buffer(struc= t iio_backend *back, return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); } =20 +static int axi_adc_raw_write(struct iio_backend *back, void *buf, unsigned= int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 data; + + data =3D *(u32 *)(buf); + + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, data); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_WRITE); + usleep_range(50, 100); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int axi_adc_raw_read(struct iio_backend *back, void *buf, unsigned = int len) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 *bdata =3D buf; + + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, + ADI_AXI_REG_CONFIG_CTRL_READ); + usleep_range(50, 100); + regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, bdata); + regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); + usleep_range(50, 100); + + return 0; +} + +static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* + * The address is written on the highest weight byte, and the MSB set + * at 1 indicates a read operation. + */ + buf =3D FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT; + axi_adc_raw_write(back, &buf, sizeof(buf)); + axi_adc_raw_read(back, val, 4); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + return 0; +} + +static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val) +{ + struct adi_axi_adc_state *st =3D iio_backend_get_priv(back); + u32 buf; + + guard(mutex)(&st->lock); + + /* Write any register to switch to register mode */ + buf =3D 0xaf00; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + buf =3D FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | + FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val); + axi_adc_raw_write(back, &buf, sizeof(buf)); + + /* Write 0x0 on the bus to get back to ADC mode */ + buf =3D 0; + axi_adc_raw_write(back, &buf, sizeof(buf)); + + return 0; +} + static void axi_adc_free_buffer(struct iio_backend *back, struct iio_buffer *buffer) { @@ -484,9 +570,23 @@ static const struct axi_adc_info adc_generic =3D { .backend_info =3D &adi_axi_adc_generic, }; =20 +static const struct ad7606_platform_data ad7606_pdata =3D { + .bus_reg_read =3D ad7606_bus_reg_read, + .bus_reg_write =3D ad7606_bus_reg_write, +}; + +static const struct axi_adc_info adc_ad7606 =3D { + .version =3D ADI_AXI_PCORE_VER(10, 0, 'a'), + .backend_info =3D &adi_axi_adc_generic, + .bus_controller =3D true, + .pdata =3D &ad7606_pdata, + .pdata_sz =3D sizeof(ad7606_pdata), +}; + /* Match table for of_platform binding */ static const struct of_device_id adi_axi_adc_of_match[] =3D { { .compatible =3D "adi,axi-adc-10.0.a", .data =3D &adc_generic }, + { .compatible =3D "adi,axi-ad7606x", .data =3D &adc_ad7606 }, { /* end of list */ } }; MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 426581DE2B3 for ; Wed, 29 Jan 2025 11:05:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148721; cv=none; b=gq3lRwmN+aDzSvXwRY2wbx+VBuGj/AOhxqvltuxtEhikfzmfYUl4q46S6SO4550WoTbT+0zj2lh5FHxQ/FUpMXBoZDyUCTXOh0girPqXN6PKlkBPCDZI3uvlLLNRGlcHSaaDHMtPV2IQQhTZzFON1ioiBx5XAe1qVWhYMKPVWr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148721; c=relaxed/simple; bh=8XBbCyrVrmKJI/qd66kNWiIMy1Am9etQvCwfxj2mcHU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CftngDt/POa8n4awjfo19Jjw/5QDF5PtVhJDIpggcAEZiERa5ALzKpHcYPjE5MNpnWtRNC9Xe350kUBsdiLZZouOFduH+OCfp6REkF+aJXVDWn9RR/RCr+06nOrWvmFF1P3CUkc5ABXITuxsNuWyod+PxdoMJxVfu/nVQUoloJg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=nhxfWChB; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="nhxfWChB" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-388cae9eb9fso3971785f8f.3 for ; Wed, 29 Jan 2025 03:05:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148717; x=1738753517; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v4USs6/6zKuF/MdKgpjuvTHhJcap7IwLMSXMnTU59Qc=; b=nhxfWChBOY6waDGjbWTdSGOh70nwtl2RZrXoL6PSKyrAJIYejKHHsaB0zXGbEF2mrU RGnommZ2U3cWLkuC7PMPl2Mn/oiyOhFavDYc4/53agfqvLRF7JnX4vnW6ZWPEFmF2sD+ OBuEr8TbLlUCLKuHng25w2gH3a6nW9O1pxBa7sRMOqB0tbii1Q4JnJqq2u0kIbEYb/1G 4FnjU/fDvsqDgMnFrzY93pNCv8cv8zIQb9n/YxeApHIe1R/TOqGygfCIjFmKp0IQ0tJ2 C0xwfutg7T8rwnAvd0FV8WJvAHhHWsYPW9tN0BYtuzaXnakIuy2E6dAtGVHkiqNvkDy3 Qi0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148717; x=1738753517; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v4USs6/6zKuF/MdKgpjuvTHhJcap7IwLMSXMnTU59Qc=; b=tzbCOcuCDImEx7N21SHo8/UKyGyMn1oAGDDbOK/dhYbVg7AJziv4tTNVPu+ssZTZ+b GOmd8I0WQbm+hHVnNu693+S7EvMXjs/PusrJryplYCwMmEeInJTUpg9WuLiqu8DKctJJ 8a7up9DwxM8BsqkFx33eqlswoT7DmxGH2rivfLq58IeYnMjTYSCAm2kBPJUSoctkPCx6 RdXFAGsGjAXiGrvahd40iH8k1QbrLAbC/zp5cas9nuw42fYjD5lMXjjsn60rdUHfdcq5 1TE8J6SXTHrgw7OMcN/fxIcoJlt6787+azKFpcSHhAz46MUY1YIOhiKIbMtioR4lQHQZ njhw== X-Forwarded-Encrypted: i=1; AJvYcCVBxN5N/WW+V42nlnkv2HoUdOnJdGo+wyqAp7cj+JZ0TQTqT7OcVT0owh/A3O64SvtHGiKsfzIZZflr+uI=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7kwC47WqQEUziuEcSmHtqYrfjR+Z7T3ca0J8o29lilbRNV+Kr AIfVr292x/ovlSUswBMEOS2V5lTQ7FVBzl77vFhSe1B04MjYntDnhUqs8w/W89s= X-Gm-Gg: ASbGncvSSZ7Hm79CJUzx1SKsl/FaPvwzS+msATmmMvXbnkb1UlzSpc7X4209fS/0hhU 4QnefNkLUcw8S3Kl4656lhr2SEUKiN7eOtsPbTO5jI26Y42lUGpTB4bqg6gCyofAvN2oPAPE9NM RbOis4T+/i1YL/XDaPWWS+PZF+wITPMdsvFHd89XZu6z9uk8tj+/c7ZycbS7YTptJ1/qJTiUQOZ 07KMkpV0mflpsfGUcKQxNe787+4A+t4gy5y5I4t55wEafVILeWItsrktGV17nHbZgurKQpF8kFA VIGAB0OUHKE0bDP380vfDuFZ/0j0f8IKSRaBCAjy91odYepIHXMNPsUx/JeS3FzTM0/I4pw= X-Google-Smtp-Source: AGHT+IGolhfktI6yJtpPuzV602TdVTTUqp9HJAQtBCrT/Ivw8RnYbrotdjfaGHytbagwJUpgq0rX1g== X-Received: by 2002:a5d:5846:0:b0:385:f4db:e33b with SMTP id ffacd0b85a97d-38c51966b85mr2380865f8f.21.1738148717359; Wed, 29 Jan 2025 03:05:17 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:16 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:09 +0100 Subject: [PATCH v3 08/10] iio: adc: ad7606: change r/w_register signature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-8-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols The register read/write with IIO backend will require to claim the direct mode, and doing so requires passing the corresponding iio_dev structure. So we need to modify the function signature to pass the iio_dev structure. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.c | 25 +++++++++++-------------- drivers/iio/adc/ad7606.h | 8 ++++---- drivers/iio/adc/ad7606_spi.c | 8 +++++--- 3 files changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 7985570ed152..4a7fc6f192c6 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -574,13 +574,13 @@ static int ad7606_reg_access(struct iio_dev *indio_de= v, guard(mutex)(&st->lock); =20 if (readval) { - ret =3D st->bops->reg_read(st, reg); + ret =3D st->bops->reg_read(indio_dev, reg); if (ret < 0) return ret; *readval =3D ret; return 0; } else { - return st->bops->reg_write(st, reg, writeval); + return st->bops->reg_write(indio_dev, reg, writeval); } } =20 @@ -1148,24 +1148,24 @@ static const struct iio_trigger_ops ad7606_trigger_= ops =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static int ad7606_write_mask(struct ad7606_state *st, unsigned int addr, +static int ad7606_write_mask(struct iio_dev *indio_dev, unsigned int addr, unsigned long mask, unsigned int val) { + struct ad7606_state *st =3D iio_priv(indio_dev); int readval; =20 - readval =3D st->bops->reg_read(st, addr); + readval =3D st->bops->reg_read(indio_dev, addr); if (readval < 0) return readval; =20 readval &=3D ~mask; readval |=3D val; =20 - return st->bops->reg_write(st, addr, readval); + return st->bops->reg_write(indio_dev, addr, readval); } =20 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { - struct ad7606_state *st =3D iio_priv(indio_dev); unsigned int ch_addr, mode, ch_index; =20 /* @@ -1187,23 +1187,20 @@ static int ad7616_write_scale_sw(struct iio_dev *in= dio_dev, int ch, int val) /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ mode =3D AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); =20 - return ad7606_write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), + return ad7606_write_mask(indio_dev, ch_addr, AD7616_RANGE_CH_MSK(ch_index= ), mode); } =20 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) { - struct ad7606_state *st =3D iio_priv(indio_dev); =20 - return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + return ad7606_write_mask(indio_dev, AD7616_CONFIGURATION_REGISTER, AD7616_OS_MASK, val << 2); } =20 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int va= l) { - struct ad7606_state *st =3D iio_priv(indio_dev); - - return ad7606_write_mask(st, AD7606_RANGE_CH_ADDR(ch), + return ad7606_write_mask(indio_dev, AD7606_RANGE_CH_ADDR(ch), AD7606_RANGE_CH_MSK(ch), AD7606_RANGE_CH_MODE(ch, val)); } @@ -1212,7 +1209,7 @@ static int ad7606_write_os_sw(struct iio_dev *indio_d= ev, int val) { struct ad7606_state *st =3D iio_priv(indio_dev); =20 - return st->bops->reg_write(st, AD7606_OS_MODE, val); + return st->bops->reg_write(indio_dev, AD7606_OS_MODE, val); } =20 static int ad7616_sw_mode_setup(struct iio_dev *indio_dev) @@ -1233,7 +1230,7 @@ static int ad7616_sw_mode_setup(struct iio_dev *indio= _dev) return ret; =20 /* Activate Burst mode and SEQEN MODE */ - return ad7606_write_mask(st, AD7616_CONFIGURATION_REGISTER, + return ad7606_write_mask(indio_dev, AD7616_CONFIGURATION_REGISTER, AD7616_BURST_MODE | AD7616_SEQEN_MODE, AD7616_BURST_MODE | AD7616_SEQEN_MODE); } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 7a044b499cfe..eca7ea99e24d 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -235,10 +235,10 @@ struct ad7606_bus_ops { int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); int (*read_block)(struct device *dev, int num, void *data); int (*sw_mode_config)(struct iio_dev *indio_dev); - int (*reg_read)(struct ad7606_state *st, unsigned int addr); - int (*reg_write)(struct ad7606_state *st, - unsigned int addr, - unsigned int val); + int (*reg_read)(struct iio_dev *indio_dev, unsigned int addr); + int (*reg_write)(struct iio_dev *indio_dev, + unsigned int addr, + unsigned int val); int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *s= can_mask); u16 (*rd_wr_cmd)(int addr, char isWriteOp); }; diff --git a/drivers/iio/adc/ad7606_spi.c b/drivers/iio/adc/ad7606_spi.c index 885bf0b68e77..15bfa7a427d9 100644 --- a/drivers/iio/adc/ad7606_spi.c +++ b/drivers/iio/adc/ad7606_spi.c @@ -124,8 +124,9 @@ static int ad7606_spi_read_block18to32(struct device *d= ev, return spi_sync_transfer(spi, &xfer, 1); } =20 -static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) +static int ad7606_spi_reg_read(struct iio_dev *indio_dev, unsigned int add= r) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct spi_device *spi =3D to_spi_device(st->dev); struct spi_transfer t[] =3D { { @@ -148,10 +149,11 @@ static int ad7606_spi_reg_read(struct ad7606_state *s= t, unsigned int addr) return be16_to_cpu(st->d16[1]); } =20 -static int ad7606_spi_reg_write(struct ad7606_state *st, +static int ad7606_spi_reg_write(struct iio_dev *indio_dev, unsigned int addr, unsigned int val) { + struct ad7606_state *st =3D iio_priv(indio_dev); struct spi_device *spi =3D to_spi_device(st->dev); =20 st->d16[0] =3D cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) | @@ -176,7 +178,7 @@ static int ad7606B_sw_mode_config(struct iio_dev *indio= _dev) struct ad7606_state *st =3D iio_priv(indio_dev); =20 /* Configure device spi to output on a single channel */ - st->bops->reg_write(st, + st->bops->reg_write(indio_dev, AD7606_CONFIGURATION_REGISTER, AD7606_SINGLE_DOUT); =20 --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DD8E1DE892 for ; Wed, 29 Jan 2025 11:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148722; cv=none; b=C5wiaYuu0GgOaSRZ00sRODehbhmZmB2OmEmCKYzuVL783wQIPSf2/ymMdDDUtv7tOUB5HIH5LHAAjPjOHOt/rTYWuPg778wXcUfiaUFmffSPoNE9/9QIUnA5WmB5OsggjronlRimD+l54jcxITsF+pDsEmv5sPSNqoocQdilSKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148722; c=relaxed/simple; bh=YPCClW4zgeQ61rrLflVkDPfGzAFfF6xsFYHv7CQfSZY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rfys+nB60WIdduCDsuymCvjKvmeBcKMg92XwDORfjKJsR0fahTVTj1Id6GRd6pU9f0iAzM84+vYc3DAHLehVxwYS1d17ojKdMLzdpd/Y2Ta2cxB3NG7e8xMuw761xIslw+W/xBUNudlxKpgQ8R0q+W2r24iHSTEy/ytUqNTbB0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=UvUu/r3T; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="UvUu/r3T" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-38be3bfb045so400848f8f.0 for ; Wed, 29 Jan 2025 03:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148719; x=1738753519; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XLkzkT5XO+iBeguDxTbZiSb8sV8dMk0q4xA/rqr+DXo=; b=UvUu/r3TI84tSIMlPxXg+NAa1n4irVgu790eu1XoaaC8Q/nFUwwj0jXE25G7ER0RSg LAH7md/ntxH668tzRJmLJ2UzRMpv8kmNhD9cPgfyj3jxId6yzqMf+inyFe71BHjQGxoG 4DOSHCLIqLrg4aLkLwh0r1YAcjEH/UFi33i5QhND5bBHURvBzUBsJrUPNTcF+t9Nw9pm zBml2OtDM7XrcODPWIjQVm0/BFMmRbZVOzEt1tdSRsQEOtCN+c5AfvfyQ1S0/6iA+Slt J4C8Rr9QJ9SSkoAWiYE4mlT0G3qdr8K6ho4/ForU0o3MXp+7MMGnKiM197zbiUg2HuDR 61EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148719; x=1738753519; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XLkzkT5XO+iBeguDxTbZiSb8sV8dMk0q4xA/rqr+DXo=; b=Yf2rKKHex5rTYzbRnU3hzZg2bMRs+NOd46iW2iOAV8VxHXFxF75AwgdohOed3SQFwF 1ZrZFC8FrcrVhB4z3Wiu3S0gmAvGThWgIqmTBti86PaHMLAwR9oKh58vgY60uBPDLtNE pxxyY+bbPjXc0dOeLOzbF1XrM26bbY8CyuEBFSrgagJhnVL91VuFP9K58lIRZMurrcpk kvSXvFodPEMsukpleCfbGQPqgWURrmMbm9ZW/1b2kEiJEqOa8j7wsvBoyAROTOhtqSE7 COe3KaY9ORo3a38Vy3uwo1iRqJ4IvjAlmaTrXbAnjB+i0C3hsMVLsRWulCD8GfyYwz3Z mxqA== X-Forwarded-Encrypted: i=1; AJvYcCUIF+F//QSh6bfKjLlMemdvXXPEmry59uvAPGQbFWWfEib3t6b0L6rZSbSZ6VZNK1HieL2v/gcUPAvId84=@vger.kernel.org X-Gm-Message-State: AOJu0YwzsPVuXPN4/7LOs2X644giH/8eP6jagQ+MoN2wJRIN3VAQO6Rw IBs7sZJrySSRKjqtHGeH95tCmKmwhTll/ZpVv2H4Cdt9cKlMMUwacN2PUyOth2w= X-Gm-Gg: ASbGncvCT56Q52Vv1100lMlCU4HJ+dxp0Bq3vxB4btq9MA6dTE+Q5h/mz+E7BSKGqQt Q8pf9axMXZHYDEmOJVQyu2LZx7Pgvc5cKivhAe+JAHHcFZyZU+Dp/Gt+vnF+s4kzIg9hDTkEaCb 141J6IzXh/hMACyr3yANMdSmD0u8KwS6usbkc4UrS50LHbvH2RknLxI6YIaQaPEYwM3fEFRv2NW +MJmBOAvulW0CN8b4RJdymbFUMr8HV9cb/BwkFOKQODVRx9/fqAXHMEmdoc9l3Stslzl5BrCpEz HJ0WaIROry/drS4l0c22RWDzCoqdpuif9nfs6mK/3NSDlFwCP8Cc7quuAZgfFBs8XsPqmwQ= X-Google-Smtp-Source: AGHT+IG+Y/hClmvuFWBStq6SoVuXgTOfZQ1xjWjuVlZ4Fue0ovn868o3oc9Anwnh1Wp/qOGiOltCvg== X-Received: by 2002:a05:6000:1f81:b0:38a:a019:30dd with SMTP id ffacd0b85a97d-38c50fe7e90mr2213273f8f.8.1738148719160; Wed, 29 Jan 2025 03:05:19 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:18 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:10 +0100 Subject: [PATCH v3 09/10] iio: adc: ad7606: change channel macros parameters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-9-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols Add the possibility to pass the *_available parameters to the main macro. This is a preparation to add the new channels for software mode and hardware mode in iio backend mode more easily. Signed-off-by: Guillaume Stols --- drivers/iio/adc/ad7606.h | 51 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index eca7ea99e24d..ada8065fba4e 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,37 +40,19 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 -#define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, bits) { \ +#define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, \ + mask_sep_avail, mask_all_avail, bits) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ .channel =3D num, \ .address =3D num, \ .info_mask_separate =3D mask_sep, \ + .info_mask_separate_available =3D \ + mask_sep_avail, \ .info_mask_shared_by_type =3D mask_type, \ .info_mask_shared_by_all =3D mask_all, \ - .scan_index =3D num, \ - .scan_type =3D { \ - .sign =3D 's', \ - .realbits =3D (bits), \ - .storagebits =3D (bits) > 16 ? 32 : 16, \ - .endianness =3D IIO_CPU, \ - }, \ -} - -#define AD7606_SW_CHANNEL(num, bits) { \ - .type =3D IIO_VOLTAGE, \ - .indexed =3D 1, \ - .channel =3D num, \ - .address =3D num, \ - .info_mask_separate =3D \ - BIT(IIO_CHAN_INFO_RAW) | \ - BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_separate_available =3D \ - BIT(IIO_CHAN_INFO_SCALE), \ - .info_mask_shared_by_all =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + mask_all_avail, \ .scan_index =3D num, \ .scan_type =3D { \ .sign =3D 's', \ @@ -80,14 +62,30 @@ }, \ } =20 +#define AD7606_SW_CHANNEL(num, bits) \ + AD760X_CHANNEL(num, \ + /* mask separate */ \ + BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask type */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + /* mask all */ \ + 0, \ + /* mask separate available */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask all available */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + bits) + #define AD7605_CHANNEL(num) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ - BIT(IIO_CHAN_INFO_SCALE), 0, 16) + BIT(IIO_CHAN_INFO_SCALE), 0, 0, 0, 16) =20 #define AD7606_CHANNEL(num, bits) \ AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ BIT(IIO_CHAN_INFO_SCALE), \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), bits) + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 0, 0, bits) =20 #define AD7616_CHANNEL(num) AD7606_SW_CHANNEL(num, 16) =20 @@ -95,7 +93,8 @@ AD760X_CHANNEL(num, 0, \ BIT(IIO_CHAN_INFO_SCALE), \ BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 16) + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 0, 0, 16) =20 struct ad7606_state; =20 --=20 2.47.0 From nobody Tue Feb 10 09:42:33 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A38471BDA91 for ; Wed, 29 Jan 2025 11:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148725; cv=none; b=lr+teKDh+54HfzjcxGbu39IduuCW3tSrY2Si3SQg1IrHGWMe3p9g2cvx7KbBw+dwIKiHwsXD6uUP3GUDheroK3yVK/UxyfEMIXzsbFWpW5yP/PQO47EYV0ZLWt5c6G5CoRnA6NSNPpL1j8rRV8+YO+S1iZ8e5ZAxKWoKMS/Wp8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738148725; c=relaxed/simple; bh=yGd3st0BkkdBB9o/zs3cfRwhrC8hQZbOG6AfbocTdgI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sN1BS5/xUUiUWEmpt9hhhluVNg3yC1ltTzUztMGGRmui3TlCV/3fIkTBUMvtx6FvtKlnWBqD9oZej5ldRlqg3mkSd/cDJ6O9Wh70k/O6uaC6w18omXAS4rYkgFPbY8PvhIaRuNoPxTqsHbVBTMRELFeCFufh1/cT29v46JRM8w0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=BIH8wq8l; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="BIH8wq8l" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-385f07cd1a4so6436215f8f.1 for ; Wed, 29 Jan 2025 03:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1738148721; x=1738753521; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=o8oP5qhY3kGRjXifVrWrcQBHp7bMw7gjCvgp2Jodwtk=; b=BIH8wq8lGQoPZenuexFJMIg0K90mYzdXpYhm1eGDvNlhCOJu8MGI6B+Mlj1XYBM+wj UzHLg/dNKTMJpX6gQZbdiYaynB+fSSQ1OaM+9dYTFG1+Jw3/mGMi0DrU1dSgnvZ3N5XL Dq36VJ/XdeqFty4iGER4FIpGEYd+/1KBJcX0C8nGjClAACXcyzrfAnsmqumEefQPMtQn 2TJrG8GaM5M7N4HFWQmX17iiFyEOH6E3ff5xHUQLORqcedqfZE+5oPLsWLbC3r0NpSka /HyfNDBLUYT/HNUW4cobE5LLlDEun3HmOIzllKQQK3UIDBD0Y8B12XmWOWqyRnJMRED2 Jt3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738148721; x=1738753521; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o8oP5qhY3kGRjXifVrWrcQBHp7bMw7gjCvgp2Jodwtk=; b=I7UuROh46Wz/WXXacQ3DqF8x5xS/NXEXiKO6kBPIRDNO8eJ2h4WHYrQ3ji4qTEedOs KvEZ1ATkH9xMeZbcvwbikVRbbZ9LfFG6SedDHjefleK+GVVw3B0HJrIi2HfBgq/iSvRV QfX27v+lZirv4Aht90mmGfTfjoVxEG7R7k7GOepLbsf83A1FaQXCKkJ2YzLWvz1KvIU+ hO/wwCC5x/bOEaW9lpz9epAns9jnI+FIMlREMpRlSNNTvO159LMTmuixyfod/kGiijdc QtFfNHI3XW98/+4XMWOsOK1Skwt1xLrCwrtWA7jGPlI2fRW79IhJ4JaF6V8NHC2Q4xSI 21EQ== X-Forwarded-Encrypted: i=1; AJvYcCWvPu9SsVv4hmicDg66fHdR5lSI0NW/fQTijeikQ8Qo7SAyqLpACNJodrxWsNR4C7atzEJU6L0qLCocsrs=@vger.kernel.org X-Gm-Message-State: AOJu0YxtORtPnIOFucUsl6RXprlyjCBBfNQ13Cwrp+7IPOCrALW/gCBb KwQ4bu9Eb5QIIxPlFdK5/vV2Tcc7emuvulJUarfyqENWhh5o65Z1niTWo6WSVdo= X-Gm-Gg: ASbGncsZMQAOPqKVuTmxMCiP6HF/ilfeseKM/vqS7tS+a1D/H0bOhdyCsSvzBAqW6Wo gkQEmBApiM3tBdYpW7okR7oH7lmYqIjy2B2lYpH4Sn4rr0mL9E75ldJdg4NVK6a5qx1DoiA+RcC oADgn+1rQpsiqoGgiJQmsyryCHK4cEhV/vCf9uv0zKzAwSFL0hDqAcICwLbe541Tyk0rhE+bPsa hzlIiwEw3vEBsZFhqXphETO5YzrYZHFUSARkcwsGldCahKqjGE4/Js/u3/T69U/xirHwvW0Cys8 70wiPcDbdrvFfhYlAHTPQLoF6vocHSQnlwhvi1831hPVYvDYvF+BkxUlMgFR2W+QS3jAMlw= X-Google-Smtp-Source: AGHT+IHadqyHkH/s7Way2NtX7ywZbXEZrfjSOuv9RTHy7FYZlK0lZd7rr92W3A4jsI/0idbvpy2Bhw== X-Received: by 2002:a05:6000:1788:b0:386:459f:67e0 with SMTP id ffacd0b85a97d-38c5194d438mr2585149f8f.21.1738148720850; Wed, 29 Jan 2025 03:05:20 -0800 (PST) Received: from [127.0.1.1] (host-95-245-235-245.retail.telecomitalia.it. [95.245.235.245]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a17d7a7sm17107364f8f.32.2025.01.29.03.05.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 03:05:20 -0800 (PST) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Wed, 29 Jan 2025 12:03:11 +0100 Subject: [PATCH v3 10/10] iio: adc: ad7606: add support for writing registers when using backend Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-10-c3aec77c0ab7@baylibre.com> References: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> In-Reply-To: <20250129-wip-bl-ad7606_add_backend_sw_mode-v3-0-c3aec77c0ab7@baylibre.com> To: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandru Ardelean , David Lechner Cc: Jonathan Cameron , linux-fbdev@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Guillaume Stols , Angelo Dureghello X-Mailer: b4 0.14.1 From: Guillaume Stols Add the logic for effectively enabling the software mode for the iio-backend, i.e. enabling the software mode channel configuration and implementing the register writing functions. Signed-off-by: Guillaume Stols Co-developed-by: Angelo Dureghello Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.h | 15 ++++++++++ drivers/iio/adc/ad7606_par.c | 69 ++++++++++++++++++++++++++++++++++++++++= +--- 2 files changed, 80 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index ada8065fba4e..9da39c2d5d53 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -96,6 +96,21 @@ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 0, 0, 16) =20 +#define AD7606_BI_SW_CHANNEL(num) \ + AD760X_CHANNEL(num, \ + /* mask separate */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask type */ \ + 0, \ + /* mask all */ \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + /* mask separate available */ \ + BIT(IIO_CHAN_INFO_SCALE), \ + /* mask all available */ \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + 16) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, diff --git a/drivers/iio/adc/ad7606_par.c b/drivers/iio/adc/ad7606_par.c index 64733b607aa8..19d93ae49e1d 100644 --- a/drivers/iio/adc/ad7606_par.c +++ b/drivers/iio/adc/ad7606_par.c @@ -19,6 +19,7 @@ #include =20 #include "ad7606.h" +#include "ad7606_bus_iface.h" =20 static const struct iio_chan_spec ad7606b_bi_channels[] =3D { AD7606_BI_CHANNEL(0), @@ -31,7 +32,19 @@ static const struct iio_chan_spec ad7606b_bi_channels[] = =3D { AD7606_BI_CHANNEL(7), }; =20 -static int ad7606_bi_update_scan_mode(struct iio_dev *indio_dev, const uns= igned long *scan_mask) +static const struct iio_chan_spec ad7606b_bi_sw_channels[] =3D { + AD7606_BI_SW_CHANNEL(0), + AD7606_BI_SW_CHANNEL(1), + AD7606_BI_SW_CHANNEL(2), + AD7606_BI_SW_CHANNEL(3), + AD7606_BI_SW_CHANNEL(4), + AD7606_BI_SW_CHANNEL(5), + AD7606_BI_SW_CHANNEL(6), + AD7606_BI_SW_CHANNEL(7), +}; + +static int ad7606_par_bus_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) { struct ad7606_state *st =3D iio_priv(indio_dev); unsigned int c, ret; @@ -48,7 +61,8 @@ static int ad7606_bi_update_scan_mode(struct iio_dev *ind= io_dev, const unsigned return 0; } =20 -static int ad7606_bi_setup_iio_backend(struct device *dev, struct iio_dev = *indio_dev) +static int ad7606_par_bus_setup_iio_backend(struct device *dev, + struct iio_dev *indio_dev) { struct ad7606_state *st =3D iio_priv(indio_dev); unsigned int ret, c; @@ -86,9 +100,56 @@ static int ad7606_bi_setup_iio_backend(struct device *d= ev, struct iio_dev *indio return 0; } =20 +static int ad7606_par_bus_reg_read(struct iio_dev *indio_dev, unsigned int= addr) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + int val, ret; + struct ad7606_platform_data *pdata =3D st->dev->platform_data; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D pdata->bus_reg_read(st->back, addr, &val); + + iio_device_release_direct_mode(indio_dev); + if (ret < 0) + return ret; + + return val; +} + +static int ad7606_par_bus_reg_write(struct iio_dev *indio_dev, + unsigned int addr, unsigned int val) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + struct ad7606_platform_data *pdata =3D st->dev->platform_data; + int ret; + + ret =3D iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret =3D pdata->bus_reg_write(st->back, addr, val); + + iio_device_release_direct_mode(indio_dev); + + return ret; +} + +static int ad7606_par_bus_sw_mode_config(struct iio_dev *indio_dev) +{ + indio_dev->channels =3D ad7606b_bi_sw_channels; + + return 0; +} + static const struct ad7606_bus_ops ad7606_bi_bops =3D { - .iio_backend_config =3D ad7606_bi_setup_iio_backend, - .update_scan_mode =3D ad7606_bi_update_scan_mode, + .iio_backend_config =3D ad7606_par_bus_setup_iio_backend, + .update_scan_mode =3D ad7606_par_bus_update_scan_mode, + .reg_read =3D ad7606_par_bus_reg_read, + .reg_write =3D ad7606_par_bus_reg_write, + .sw_mode_config =3D ad7606_par_bus_sw_mode_config, }; =20 static int ad7606_par16_read_block(struct device *dev, --=20 2.47.0