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Wed, 29 Jan 2025 07:08:16 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1c3994sm17011531f8f.81.2025.01.29.07.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 07:08:16 -0800 (PST) From: Neil Armstrong Date: Wed, 29 Jan 2025 16:08:15 +0100 Subject: [PATCH v2] arm64: dts: qcom: sm8650: add all 8 coresight ETE nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250129-topic-sm8650-upstream-add-all-coresight-cpus-v2-1-c62549307e01@linaro.org> X-B4-Tracking: v=1; b=H4sIAF5EmmcC/53NQQ6DIBCF4asY1p0GUKl21Xs0LiiMOokKATRtj Hcv9Qhd/m/xvp1FDISR3YudBdwokltyyEvBzKiXAYFsbia5rLmQLSTnyUCcG1VzWH1MAfUM2lr Q0wTGBYw0jAmMXyPoshKN4upV1hXLlz5gT++Te3a5R4rJhc+pb+K3/gltAgS0qm2VLW+2b/Ax0 aKDu7owsO44ji9SXFDO6QAAAA== X-Change-ID: 20250129-topic-sm8650-upstream-add-all-coresight-cpus-a3418606b354 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yuanfang Zhang Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Only CPU0 Embedded Trace Extension (ETE) was added, but there's one for all 8 CPUs, so add the missing ones. Fixes: 256e6937e48a ("arm64: dts: qcom: sm8650: Add coresight nodes") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- Changes in v2: - fixed the 7/8 cpu wording - added the sm8650 prefix - add review tag - Link to v1: https://lore.kernel.org/r/20250129-topic-sm8650-upstream-add-= all-coresight-cpus-v1-1-96996d37df8e@linaro.org --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 163 +++++++++++++++++++++++++++++++= +++- 1 file changed, 161 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..d925d5e2c8182d522dd5b8e1fa0= e253f5de2f7a7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -365,7 +365,7 @@ cluster_sleep_1: cluster-sleep-1 { }; }; =20 - ete0 { + ete-0 { compatible =3D "arm,embedded-trace-extension"; =20 cpu =3D <&cpu0>; @@ -379,15 +379,174 @@ ete0_out_funnel_ete: endpoint { }; }; =20 + ete-1 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu1>; + + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete-2 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu2>; + + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete-3 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu3>; + + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete-4 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu4>; + + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete-5 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu5>; + + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete-6 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu6>; + + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete-7 { + compatible =3D "arm,embedded-trace-extension"; + + cpu =3D <&cpu7>; + + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint =3D <&funnel_ete_in_ete7>; + }; + }; + }; + }; + funnel-ete { compatible =3D "arm,coresight-static-funnel"; =20 in-ports { - port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + funnel_ete_in_ete0: endpoint { remote-endpoint =3D <&ete0_out_funnel_ete>; }; }; + + port@1 { + reg =3D <1>; + + funnel_ete_in_ete1: endpoint { + remote-endpoint =3D <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg =3D <2>; + + funnel_ete_in_ete2: endpoint { + remote-endpoint =3D <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg =3D <3>; + + funnel_ete_in_ete3: endpoint { + remote-endpoint =3D <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg =3D <4>; + + funnel_ete_in_ete4: endpoint { + remote-endpoint =3D <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg =3D <5>; + + funnel_ete_in_ete5: endpoint { + remote-endpoint =3D <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_ete_in_ete6: endpoint { + remote-endpoint =3D <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel_ete_in_ete7: endpoint { + remote-endpoint =3D <&ete7_out_funnel_ete>; + }; + }; }; =20 out-ports { --- base-commit: da7e6047a6264af16d2cb82bed9b6caa33eaf56a change-id: 20250129-topic-sm8650-upstream-add-all-coresight-cpus-a3418606b3= 54 Best regards, --=20 Neil Armstrong