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Tue, 28 Jan 2025 01:38:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IESpE/6TmYCtn7vt9b8+M+eOqAHMi7X4Aa/jIxEhceUkinauqe95Ek3jOdkLhDitwInRCGZ4g== X-Received: by 2002:a17:90b:270d:b0:2ee:863e:9ffc with SMTP id 98e67ed59e1d1-2f782ca5d86mr59282565a91.21.1738057084592; Tue, 28 Jan 2025 01:38:04 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa456absm9749501a91.2.2025.01.28.01.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 01:38:04 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 28 Jan 2025 15:07:41 +0530 Subject: [PATCH v5 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250128-preset_v2-v5-3-4d230d956f8c@oss.qualcomm.com> References: <20250128-preset_v2-v5-0-4d230d956f8c@oss.qualcomm.com> In-Reply-To: <20250128-preset_v2-v5-0-4d230d956f8c@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738057065; l=3427; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=aNUEDnnBXJmAjyo+Rv+xBzm6n/bBygSEIE3MuD7dTNE=; b=JcDyBKDyG0bP7cftM+W5ncKic8gdrE1Q9GqpbicZFepKvWWI1N1o99MUistpklv6aAFxq7qvQ zfrRJu4ShbwA9/G7L1H+z6Al+NvOzMVbk8ufaKbB7qgjF673jagnjCD X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: VZ4akHDWWC_kiyXUJW7pXtmeAYwbUP9b X-Proofpoint-ORIG-GUID: VZ4akHDWWC_kiyXUJW7pXtmeAYwbUP9b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_03,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501280074 Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 12 +++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pci->num_lanes < 1) + pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 6d6cbc8b5b2c..1007248d3525 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,14 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie = *pci) =20 } =20 +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1077,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes =3D dw_pcie_link_get_max_link_width(pci); u32 val; =20 dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1111,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |=3D PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); =20 - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + if (num_lanes !=3D pci->num_lanes) + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..500e793c9361 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -486,6 +486,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, s= ize_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, --=20 2.34.1