From nobody Fri Jan 31 00:18:17 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99FC31FC11B for ; Mon, 27 Jan 2025 03:27:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737948502; cv=none; b=r1rSjiucB/V0dMRHs3xpXtrCQFUW/EI4J4Uktclnvl64GKoLIQ2saJaxi8Kpn7ufC5HU5WIrZhI1cUkbTJbhKH9EJtdaFCZ052YK3KBI+TZGoZt4YTyBrQ4pNrkgLFBAFZjhsFwwHc/M6y1UYMFIZQHrDk2dFcBfvBNCkDwLNGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737948502; c=relaxed/simple; bh=BypsDgKIbNSD4JbmIdu5pCiNZbSbL6owtdy46pFhwE0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vFX3PWxqczL5h9PEEE6lHfGEYaZ24QTXYMPJ6FomMqW6wbmQuI44awWB2/AQJ0pVyimldrTZFX3LxwKKTSsPIa2GDkb+3Cv7c57X4f20l8eXJvCFdBtXamQX5Q5CQQM7ltSXU/PMlBZ/vLFjiZuwpVgVi/qMDLna+PgS/+Dc2bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4YhDJZ4h0fz11PHd; Mon, 27 Jan 2025 11:23:10 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id DE8A31402DA; Mon, 27 Jan 2025 11:27:16 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Mon, 27 Jan 2025 11:27:15 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v1 drm-dp 1/4] drm/hisilicon/hibmc: Add dp phy cfg to adjust serdes rate, voltage and pre-emphasis Date: Mon, 27 Jan 2025 11:20:21 +0800 Message-ID: <20250127032024.1542219-2-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250127032024.1542219-1-shiyongbang@huawei.com> References: <20250127032024.1542219-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li This phy is inited and configured for dp, and integrating them into dp init and dp link training process. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- drivers/gpu/drm/hisilicon/hibmc/Makefile | 2 +- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 1 + .../gpu/drm/hisilicon/hibmc/dp/dp_config.h | 1 + drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 9 ++- drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 33 +++++++-- drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.c | 72 +++++++++++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.h | 38 ++++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h | 1 + .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 8 +-- 9 files changed, 153 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.c create mode 100644 drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.h diff --git a/drivers/gpu/drm/hisilicon/hibmc/Makefile b/drivers/gpu/drm/his= ilicon/hibmc/Makefile index 95a4ed599d98..35a74cc10c80 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/Makefile +++ b/drivers/gpu/drm/hisilicon/hibmc/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only hibmc-drm-y :=3D hibmc_drm_drv.o hibmc_drm_de.o hibmc_drm_vdac.o hibmc_drm= _i2c.o \ - dp/dp_aux.o dp/dp_link.o dp/dp_hw.o hibmc_drm_dp.o + dp/dp_aux.o dp/dp_link.o dp/dp_hw.o dp/dp_phy.o hibmc_drm_dp.o =20 obj-$(CONFIG_DRM_HISI_HIBMC) +=3D hibmc-drm.o diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index 2c52a4476c4d..00b23301d26e 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -38,6 +38,7 @@ struct hibmc_dp_dev { struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field(= ) */ struct hibmc_dp_link link; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + void __iomem *phy_base; }; =20 #define dp_field_modify(reg_value, mask, val) \ diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h b/drivers/gpu/d= rm/hisilicon/hibmc/dp/dp_config.h index 74dd9956144e..c5feef8dc27d 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h @@ -15,5 +15,6 @@ #define HIBMC_DP_CLK_EN 0x7 #define HIBMC_DP_SYNC_EN_MASK 0x3 #define HIBMC_DP_LINK_RATE_CAL 27 +#define HIBMC_DP_SYNC_DELAY(lanes) ((lanes) =3D=3D 0x2 ? 86 : 46) =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index a8d543881c09..0dac4cfdde7c 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -7,6 +7,7 @@ #include "dp_comm.h" #include "dp_reg.h" #include "dp_hw.h" +#include "dp_phy.h" =20 static void hibmc_dp_set_tu(struct hibmc_dp_dev *dp, struct drm_display_mo= de *mode) { @@ -72,6 +73,9 @@ static void hibmc_dp_set_sst(struct hibmc_dp_dev *dp, str= uct drm_display_mode *m HIBMC_DP_CFG_STREAM_HTOTAL_SIZE, htotal_size); hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_HORIZONTAL_SIZE, HIBMC_DP_CFG_STREAM_HBLANK_SIZE, hblank_size); + hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_PACKET, + HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION, + HIBMC_DP_SYNC_DELAY(dp->link.cap.lanes)); } =20 static void hibmc_dp_link_cfg(struct hibmc_dp_dev *dp, struct drm_display_= mode *mode) @@ -165,8 +169,11 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) =20 hibmc_dp_aux_init(dp_dev); =20 + if (hibmc_dp_phy_init(dp_dev)) + return -EAGAIN; + dp_dev->link.cap.lanes =3D 0x2; - dp_dev->link.cap.link_rate =3D DP_LINK_BW_2_7; + dp_dev->link.cap.link_rate =3D DP_LINK_BW_8_1; =20 /* hdcp data */ writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index f6355c16cc0a..1124cd70c320 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -6,6 +6,7 @@ #include #include "dp_comm.h" #include "dp_reg.h" +#include "dp_phy.h" =20 #define HIBMC_EQ_MAX_RETRY 5 =20 @@ -108,7 +109,11 @@ static int hibmc_dp_link_training_cr_pre(struct hibmc_= dp_dev *dp) return ret; =20 for (i =3D 0; i < dp->link.cap.lanes; i++) - train_set[i] =3D DP_TRAIN_VOLTAGE_SWING_LEVEL_2; + train_set[i] =3D DP_TRAIN_VOLTAGE_SWING_LEVEL_0; + + ret =3D hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); + if (ret) + return ret; =20 ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp-= >link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { @@ -137,21 +142,28 @@ static bool hibmc_dp_link_get_adjust_train(struct hib= mc_dp_dev *dp, return false; } =20 -static inline int hibmc_dp_link_reduce_rate(struct hibmc_dp_dev *dp) +static int hibmc_dp_link_reduce_rate(struct hibmc_dp_dev *dp) { + u8 rate =3D 0; + switch (dp->link.cap.link_rate) { case DP_LINK_BW_2_7: dp->link.cap.link_rate =3D DP_LINK_BW_1_62; - return 0; + rate =3D DP_PHY_BW_1_62; + break; case DP_LINK_BW_5_4: dp->link.cap.link_rate =3D DP_LINK_BW_2_7; - return 0; + rate =3D DP_PHY_BW_2_7; + break; case DP_LINK_BW_8_1: dp->link.cap.link_rate =3D DP_LINK_BW_5_4; - return 0; + rate =3D DP_PHY_BW_5_4; + break; default: return -EINVAL; } + + return hibmc_dp_serdes_rate_switch(rate, dp); } =20 static inline int hibmc_dp_link_reduce_lane(struct hibmc_dp_dev *dp) @@ -159,6 +171,7 @@ static inline int hibmc_dp_link_reduce_lane(struct hibm= c_dp_dev *dp) switch (dp->link.cap.lanes) { case 0x2: dp->link.cap.lanes--; + drm_warn(dp->dev, "dp link training reduce to 1 lane\n"); break; case 0x1: drm_err(dp->dev, "dp link training reduce lane failed, already reach min= imum\n"); @@ -206,6 +219,11 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_d= ev *dp) } =20 level_changed =3D hibmc_dp_link_get_adjust_train(dp, lane_status); + + ret =3D hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); + if (ret) + return ret; + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.trai= n_set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { @@ -255,6 +273,11 @@ static int hibmc_dp_link_training_channel_eq(struct hi= bmc_dp_dev *dp) } =20 hibmc_dp_link_get_adjust_train(dp, lane_status); + + ret =3D hibmc_dp_serdes_set_tx_cfg(dp, dp->link.train_set); + if (ret) + return ret; + ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.c b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_phy.c new file mode 100644 index 000000000000..07940b5baf29 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2024 Hisilicon Limited. +#include +#include +#include +#include "dp_comm.h" +#include "dp_config.h" +#include "dp_reg.h" +#include "dp_phy.h" + +int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC= _DP_LANE_NUM_MAX]) +{ + u32 serdes_tx_cfg[4][4] =3D { {DP_PHY_VOL0_PRE0, DP_PHY_VOL0_PRE1, + DP_PHY_VOL0_PRE2, DP_PHY_VOL0_PRE3}, + {DP_PHY_VOL1_PRE0, DP_PHY_VOL1_PRE1, DP_PHY_VOL1_PRE2}, + {DP_PHY_VOL2_PRE0, DP_PHY_VOL2_PRE1}, {DP_PHY_VOL3_PRE0}}; + int cfg[2]; + int i; + + for (i =3D 0; i < HIBMC_DP_LANE_NUM_MAX; i++) { + cfg[i] =3D serdes_tx_cfg[(train_set[i] & 0x3)] + [(train_set[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT & 0x3)]; + if (!cfg[i]) { + cfg[i] =3D DP_PHY_VOL3_PRE0; + drm_warn(dp->dev, "dp serdes cfg beyonds the allowable range\n"); + } + + /* lane1 offset is 4 */ + writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, cfg[i]), + dp->phy_base + HIBMC_DP_PMA_LANE0_OFFSET + i * 4); + } + + usleep_range(300, 500); + + if (readl(dp->phy_base + HIBMC_DP_LANE_STATUS_OFFSET) !=3D DP_PHY_DONE) { + drm_err(dp->dev, "dp serdes cfg failed\n"); + return -EAGAIN; + } + + return 0; +} + +int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp) +{ + writel(rate, dp->phy_base + HIBMC_DP_LANE0_RATE_OFFSET); + writel(rate, dp->phy_base + HIBMC_DP_LANE1_RATE_OFFSET); + + usleep_range(300, 500); + + if (readl(dp->phy_base + HIBMC_DP_LANE_STATUS_OFFSET) !=3D DP_PHY_DONE) { + drm_err(dp->dev, "dp serdes rate switching failed\n"); + return -EAGAIN; + } + + if (rate < DP_PHY_BW_8_1) + drm_warn(dp->dev, "reducing serdes rate to :%d\n", + rate ? rate * HIBMC_DP_LINK_RATE_CAL * 10 : 162); + + return 0; +} + +int hibmc_dp_phy_init(struct hibmc_dp_dev *dp) +{ + dp->phy_base =3D dp->base + HIBMC_DP_HOST_OFFSET; + + writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_PHY_VOL0_PRE0), + dp->phy_base + HIBMC_DP_PMA_LANE0_OFFSET); + writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_PHY_VOL0_PRE0), + dp->phy_base + HIBMC_DP_PMA_LANE1_OFFSET); + + return hibmc_dp_serdes_rate_switch(DP_PHY_BW_8_1, dp); +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.h b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_phy.h new file mode 100644 index 000000000000..db9fddd24d0e --- /dev/null +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_phy.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) 2025 Hisilicon Limited. */ + +#ifndef DP_PHY_H +#define DP_PHY_H + +/* dp phy reg */ +#define HIBMC_DP_HOST_OFFSET 0x10000 +#define HIBMC_DP_LANE0_RATE_OFFSET 0x4 +#define HIBMC_DP_LANE1_RATE_OFFSET 0xc +#define HIBMC_DP_LANE_STATUS_OFFSET 0x10 +#define HIBMC_DP_PMA_LANE0_OFFSET 0x18 +#define HIBMC_DP_PMA_LANE1_OFFSET 0x1c +#define HIBMC_DP_PMA_TXDEEMPH GENMASK(18, 1) + +/* dp phy cfg parameter */ +#define DP_PHY_VOL0_PRE0 0x280 +#define DP_PHY_VOL0_PRE1 0x2300 +#define DP_PHY_VOL0_PRE2 0x53c0 +#define DP_PHY_VOL0_PRE3 0x8400 +#define DP_PHY_VOL1_PRE0 0x380 +#define DP_PHY_VOL1_PRE1 0x3440 +#define DP_PHY_VOL1_PRE2 0x6480 +#define DP_PHY_VOL2_PRE0 0x500 +#define DP_PHY_VOL2_PRE1 0x4500 +#define DP_PHY_VOL3_PRE0 0x600 +#define DP_PHY_BW_8_1 0x3 +#define DP_PHY_BW_5_4 0x2 +#define DP_PHY_BW_2_7 0x1 +#define DP_PHY_BW_1_62 0x0 + +#define DP_PHY_DONE 0x3 + +int hibmc_dp_phy_init(struct hibmc_dp_dev *dp); +int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp); +int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC= _DP_LANE_NUM_MAX]); + +#endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_reg.h index 4a515c726d52..99ba9c951c41 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h @@ -72,5 +72,6 @@ #define HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE GENMASK(9, 6) #define HIBMC_DP_CFG_STREAM_HTOTAL_SIZE GENMASK(31, 16) #define HIBMC_DP_CFG_STREAM_HBLANK_SIZE GENMASK(15, 0) +#define HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION GENMASK(31, 20) =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index e6de6d5edf6b..bade693d9730 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -28,9 +28,7 @@ #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" =20 -#define HIBMC_DP_HOST_SERDES_CTRL 0x1f001c -#define HIBMC_DP_HOST_SERDES_CTRL_VAL 0x8a00 -#define HIBMC_DP_HOST_SERDES_CTRL_MASK 0x7ffff +#define HIBMC_DP_HOST_SERDES_CTRL 0x1f001c =20 DEFINE_DRM_GEM_FOPS(hibmc_fops); =20 @@ -122,8 +120,8 @@ static int hibmc_kms_init(struct hibmc_drm_private *pri= v) } =20 /* if DP existed, init DP */ - if ((readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL) & - HIBMC_DP_HOST_SERDES_CTRL_MASK) =3D=3D HIBMC_DP_HOST_SERDES_CTRL_VAL= ) { + ret =3D readl(priv->mmio + HIBMC_DP_HOST_SERDES_CTRL); + if (ret) { ret =3D hibmc_dp_init(priv); if (ret) drm_err(dev, "failed to init dp: %d\n", ret); --=20 2.33.0