From nobody Thu Jan 30 19:16:18 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D35991FDE04; Mon, 27 Jan 2025 09:39:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737970752; cv=none; b=BQJZGJiveujchszUfzr6u9vXnbOsPUyg5IizJWUaUR/C0oy+P7kM+rSEmgKWnHztCTnDEJVP/GcaKR5l6zmbXr+whhJK5UGHphA87uuVtzXNDwEKmzYlR9TjtQXYFK0u9zlTmgcP1q9CEhmZmT9JX4/Cs+jsVt1cnEerE3c5iiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737970752; c=relaxed/simple; bh=KqZm4MD5/2nzq1lDTKuip2lJLdqrPklenXHEb7RV4Js=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mPuU9KplWPoijd0wN08KLxwHR+fr7FoiwsEWkTukSicd5CPuq0GdhLXYO/0RN5KaCKF8+98bz3XbfiHx8F/ZCffhGHQsYObrel76deruivWkueJ7/oetvk6jqTZCRC1w6JNWTd8o57/8M/sAFJM41QuVqrN5XKGYxpekGmd0u0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=MMF+0IDS; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="MMF+0IDS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1737970749; bh=KqZm4MD5/2nzq1lDTKuip2lJLdqrPklenXHEb7RV4Js=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MMF+0IDSCx+beoTBPt1K8NVwiN5AZBo1dyZIsCWAluY3yA6iRVDJIsAiW1UnQPMHE mLuUmpBqIQNMwStTHztGSoBGLh9bcyNtQtMS3j5YAzQHLW8KkFG5kcXD1v6pFTfi+w PMY01pTcwzloCQQsO74nScBBuSeJMXgghgZLGjeuUyCn9c9krOiUoWwksmAgBogG4I oMrUZTaHXdloMt15bcBl1cNfO4e4wESsu4kZbX2JTDtVK0SZUMCMHIAzfxT6DYrvqO J5WW5bmr6yq9xMJXwMFKpot7vdaNMKctR+/310T60bcp3NpCgypAWW8a+tWWigOHUH AhNnvRJ2u1Q9g== Received: from apertis-1.home (2a01cb088CcA73006086F5f072C6a07A.ipv6.abo.wanadoo.fr [IPv6:2a01:cb08:8cca:7300:6086:f5f0:72c6:a07a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: jmassot) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9557B17E0E8D; Mon, 27 Jan 2025 10:39:08 +0100 (CET) From: Julien Massot Date: Mon, 27 Jan 2025 10:38:46 +0100 Subject: [PATCH v2 1/2] dt-bindings: soc: renesas: Document MyIR Remi Pi board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-myir-remi-pi-v2-1-7bd3a1c62752@collabora.com> References: <20250127-myir-remi-pi-v2-0-7bd3a1c62752@collabora.com> In-Reply-To: <20250127-myir-remi-pi-v2-0-7bd3a1c62752@collabora.com> To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Massot , Krzysztof Kozlowski X-Mailer: b4 0.14.2 Document the MyIR Remi Pi" which is based on the Renesas RZ/G2L ("R9A07G044L2") SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Julien Massot Reviewed-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd2a3828f5757735eb473c39f27b57..3e02bc2e17483cf53679a130eaa= a5943d2f9a2a7 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -491,6 +491,13 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 =20 + - items: + - enum: + # MYIR Remi Pi SBC (MYB-YG2LX-REMI) + - myir,remi-pi + - const: renesas,r9a07g044l2 + - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) items: - enum: --=20 2.47.1 From nobody Thu Jan 30 19:16:18 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D4611FDA9E; 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Mon, 27 Jan 2025 10:39:09 +0100 (CET) From: Julien Massot Date: Mon, 27 Jan 2025 10:38:47 +0100 Subject: [PATCH v2 2/2] arm64: renesas: add initial support for MYIR Remi Pi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-myir-remi-pi-v2-2-7bd3a1c62752@collabora.com> References: <20250127-myir-remi-pi-v2-0-7bd3a1c62752@collabora.com> In-Reply-To: <20250127-myir-remi-pi-v2-0-7bd3a1c62752@collabora.com> To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Julien Massot X-Mailer: b4 0.14.2 Add basic support for the MyIR Remi Pi (based on r9a07g044l2): - UART - i2c - emmc - USB host - HDMI output - Ethernet Signed-off-by: Julien Massot --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts | 388 +++++++++++++++++= ++++ 2 files changed, 389 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 97228a3cb99c163d299b508ee7653aafea3d1a3a..6824c63a1b154acf13de7e3d44b= b10d5754738c4 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc-cru= -csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g044c2-smarc.dtb r9a07g044= c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044c2-smarc-cru-csi-ov5645.dtb =20 +dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-remi-pi.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) +=3D r9a07g044l2-smarc-cru-csi-ov5645.dtbo r9a07g044l2-smarc-cru-csi-ov5645-dtbs :=3D r9a07g044l2-smarc.dtb r9a07g044= l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts b/arch/arm= 64/boot/dts/renesas/r9a07g044l2-remi-pi.dts new file mode 100644 index 0000000000000000000000000000000000000000..57d318ded704a970c09fd8f7205= ccf7bc221e318 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the MYiR Remi Pi + * + * Copyright (C) 2022 MYiR Electronics Corp. + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include +#include + +#include "r9a07g044l2.dtsi" + +/ { + model =3D "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; + compatible =3D "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + aliases { + ethernet0 =3D ð0; + ethernet1 =3D ð1; + + serial0 =3D &scif0; + serial1 =3D &scif1; + serial2 =3D &scif2; + serial3 =3D &scif3; + + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + + mmc0 =3D &sdhi0; + mmc1 =3D &sdhi1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@48000000 { + device_type =3D "memory"; + /* first 128MB is reserved for secure area. */ + reg =3D <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_5p0v: regulator-5p0v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-5.0V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + vin-supply =3D <®_5p0v>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.8V"; + vin-supply =3D <®_3p3v>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + reg_1p1v: regulator-vdd-core { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-1.1V"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-always-on; + }; + + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "a"; + ddc-i2c-bus =3D <&i2c1>; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <<8912_out>; + }; + }; + }; +}; + +ð0 { + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + phy0: ethernet-phy@4 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + interrupts-extended =3D <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ð1 { + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + phy1: ethernet-phy@6 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <6>; + interrupts-extended =3D <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal_clk { + clock-frequency =3D <24000000>; +}; + +&gpu { + mali-supply =3D <®_1p1v>; +}; + +&ostm1 { + status =3D "okay"; +}; + +&ostm2 { + status =3D "okay"; +}; + +&pinctrl { + i2c0_pins: i2c0 { + pins =3D "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins =3D "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux =3D , /* SDA */ + ; /* SCL */ + }; + + i2c3_pins: i2c3 { + pinmux =3D , /* SDA */ + ; /* SCL */ + }; + + spi0_pins: spi0 { + pinmux =3D , /* CLK */ + , /* MOSI */ + , /* MISO */ + ; /* Chip Enable*/ + }; + + eth0_pins: eth0 { + pinmux =3D , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux =3D , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + + sdhi0_pins: sd0 { + sd0_data { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source =3D <1800>; + }; + + sd0_ctrl { + pins =3D "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sd0_rst { + pins =3D "SD0_RST#"; + power-source =3D <1800>; + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source =3D <1800>; + }; + + sd0_ctrl_uhs { + pins =3D "SD0_CLK", "SD0_CMD"; + power-source =3D <1800>; + }; + + sd0_rst_uhs { + pins =3D "SD0_RST#"; + power-source =3D <1800>; + }; + }; + + usb1_pins: usb1 { + pinmux =3D , /* VBUS */ + ; /* OVC */ + }; + + scif0_pins: scif0 { + pinmux =3D , /* TxD */ + ; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux =3D , /* TxD */ + ; /* RxD */ + }; + + scif2_pins: scif2 { + pinmux =3D , /* TxD */ + ; /* RxD */ + }; + + scif3_pins: scif3 { + pinmux =3D , /* TxD */ + ; /* RxD */ + }; +}; + +&sdhi0 { + pinctrl-0 =3D <&sdhi0_pins>; + pinctrl-1 =3D <&sdhi0_pins_uhs>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <®_1p8v>; + bus-width =3D <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type =3D <1>; + status =3D "okay"; +}; + +&usb2_phy1 { + pinctrl-0 =3D <&usb1_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&dsi { + status =3D "okay"; + ports { + port@1 { + dsi_out: endpoint { + remote-endpoint =3D <<8912_in>; + data-lanes =3D <1 2 3 4>; + }; + }; + }; +}; + +&du { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + + clock-frequency =3D <400000>; + status =3D "okay"; + + hdmi-bridge@48 { + compatible =3D "lontium,lt8912b"; + reg =3D <0x48> ; + reset-gpios =3D <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lt8912_in: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&dsi_out>; + }; + }; + + port@1 { + reg =3D <1>; + + lt8912_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&scif0 { + pinctrl-0 =3D <&scif0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&scif2 { + pinctrl-0 =3D <&scif2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&scif3 { + pinctrl-0 =3D <&scif3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&phyrst { + status =3D "okay"; +}; + +&mtu3 { + status =3D "okay"; +}; --=20 2.47.1