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Mon, 27 Jan 2025 05:48:32 -0800 (PST) From: Krzysztof Kozlowski Date: Mon, 27 Jan 2025 14:47:53 +0100 Subject: [PATCH 20/24] arm64: dts: qcom: sm8250: Use the header with DSI phy clock IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-dts-qcom-dsi-phy-clocks-v1-20-9d8ddbcb1c7f@linaro.org> References: <20250127-dts-qcom-dsi-phy-clocks-v1-0-9d8ddbcb1c7f@linaro.org> In-Reply-To: <20250127-dts-qcom-dsi-phy-clocks-v1-0-9d8ddbcb1c7f@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3495; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=eTiJpd0ZzHSjlbk+10lATAcIQTHEVoGhG40y5TkdTPk=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnl46Qx4Rsd/ipHmsAz0AEE93cfNo9wO5uLc9vO /rB0zuC7eaJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ5eOkAAKCRDBN2bmhouD 13TeD/45ytLjFUbH544Cx01YhXBr7uJYwYgHHmlUUD8xJiWVD8DLw53bTkJaP3nGKqHGjt5p7cP pZeNVClL8kwkjkvbmqPYLOL8xYCGxyo0lrknowQmX9Sj21OdQsnxkZmVNfKxVvYvvVa0zizSW3v 0HEy/9mDRyg1eady5GiMnKBX8RO8PoLHIQTRub0Z8JkAmjQJYnB4YDGPA4TIy6C192x5nPqXvgM 094PqZp/9dzpatUxi4Kn/gMVjqk6yHbpj/yQIocl1CQ90tDznSFU9IPr0JNyArviQduYeSmrFHX 2ID+q5LbAEfMbbhMMDn6CyAgGUTQGR+Dd4UxrvcWnO1UGy2VkyW1BBg+tOGiIgsXxu/Ye4q6mIx SaO4K8/Sr5iotaGv75orPPqVSIyDRBG9yq4TdNr7w6FRcOf/ha9QXoGadxu0BxHeSL8Q/Ym9Xnt GbftzuT44hg/sPhW9taZOIVRJvDQzAd8IYhOMlTd2kf/7b3XOWnGXr1CqUgLXlBWgknSVezMPSi W2LAUPU3FsLfT5HJ1hNQn7P7MbbdsOkou8FkDgUkdaLtaltjVU2ScTiD+7/ER8pgJihhIkL0Nlm hdEeY3OzQ1Rm2LTt4l1/PZJmoQoCZO3AYNbdK6ylods9npasgBmOi2gc1Sjs1zKJfHRGZL5yCDc xl9QBsRpRfKzGqg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Krzysztof Kozlowski --- Depends on: https://lore.kernel.org/all/20250127132105.107138-1-krzysztof.kozlowski@lin= aro.org/ --- .../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 21 +++++++++++++----= ---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arc= h/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 813b009b7bd6818b92b243f0982d2c7ef903d421..5723999db89afecb666db1e6c93= 7794455cf7342 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,7 +659,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; qcom,sync-dual-dsi; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index c2937b4d9f180296733b6d7a7a16a088f1f96b76..751294c5ee4385437364ffcedcf= d64248a42f6cf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -4861,8 +4862,10 @@ mdss_dsi0: dsi@ae94000 { "iface", "bus"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd RPMHPD_MMCX>; @@ -4953,8 +4956,10 @@ mdss_dsi1: dsi@ae96000 { "iface", "bus"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd RPMHPD_MMCX>; @@ -5011,10 +5016,10 @@ dispcc: clock-controller@af00000 { power-domains =3D <&rpmhpd RPMHPD_MMCX>; required-opps =3D <&rpmhpd_opp_low_svs>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names =3D "bi_tcxo", --=20 2.43.0