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Mon, 27 Jan 2025 20:59:50 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:42 -0800 Subject: [PATCH v3 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-1-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 From: Weilin Wang These functions are added to parse event counter restrictions and counter availability info from json files so that the metric grouping method could do grouping based on the counter restriction of events and the counters that are available on the system. Signed-off-by: Weilin Wang --- tools/perf/pmu-events/empty-pmu-events.c | 299 ++++++++++++++++++++-------= ---- tools/perf/pmu-events/jevents.py | 205 ++++++++++++++++++++- tools/perf/pmu-events/pmu-events.h | 32 +++- 3 files changed, 419 insertions(+), 117 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 1c7a2cfa321f..3a7ec31576f5 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -20,73 +20,73 @@ struct pmu_table_entry { =20 static const char *const big_c_string =3D /* offset=3D0 */ "tool\000" -/* offset=3D5 */ "duration_time\000tool\000Wall clock interval time in nan= oseconds\000config=3D1\000\00000\000\000" -/* offset=3D78 */ "user_time\000tool\000User (non-kernel) time in nanoseco= nds\000config=3D2\000\00000\000\000" -/* offset=3D145 */ "system_time\000tool\000System/kernel time in nanosecon= ds\000config=3D3\000\00000\000\000" -/* offset=3D210 */ "has_pmem\000tool\0001 if persistent memory installed o= therwise 0\000config=3D4\000\00000\000\000" -/* offset=3D283 */ "num_cores\000tool\000Number of cores. A core consists = of 1 or more thread, with each thread being associated with a logical Linux= CPU\000config=3D5\000\00000\000\000" -/* offset=3D425 */ "num_cpus\000tool\000Number of logical Linux CPUs. Ther= e may be multiple such CPUs on a core\000config=3D6\000\00000\000\000" -/* offset=3D525 */ "num_cpus_online\000tool\000Number of online logical Li= nux CPUs. There may be multiple such CPUs on a core\000config=3D7\000\00000= \000\000" -/* offset=3D639 */ "num_dies\000tool\000Number of dies. Each die has 1 or = more cores\000config=3D8\000\00000\000\000" -/* offset=3D712 */ "num_packages\000tool\000Number of packages. Each packa= ge has 1 or more die\000config=3D9\000\00000\000\000" -/* offset=3D795 */ "slots\000tool\000Number of functional units that in pa= rallel can execute parts of an instruction\000config=3D0xa\000\00000\000\00= 0" -/* offset=3D902 */ "smt_on\000tool\0001 if simultaneous multithreading (ak= a hyperthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000" -/* offset=3D1006 */ "system_tsc_freq\000tool\000The amount a Time Stamp Co= unter (TSC) increases per second\000config=3D0xc\000\00000\000\000" -/* offset=3D1102 */ "default_core\000" -/* offset=3D1115 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000e= vent=3D0x8a\000\00000\000\000" -/* offset=3D1174 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000e= vent=3D0x8b\000\00000\000\000" -/* offset=3D1233 */ "l3_cache_rd\000cache\000L3 cache access, read\000even= t=3D0x40\000\00000\000Attributable Level 3 cache access, read\000" -/* offset=3D1328 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000" -/* offset=3D1427 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20\000\00000\000\000" -/* offset=3D1557 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\0= 0000\000\000" -/* offset=3D1672 */ "hisi_sccl,ddrc\000" -/* offset=3D1687 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000" -/* offset=3D1773 */ "uncore_cbox\000" -/* offset=3D1785 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted fro= m L3 Eviction which misses in some processor core\000" -/* offset=3D2016 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000" -/* offset=3D2081 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000" -/* offset=3D2152 */ "hisi_sccl,l3c\000" -/* offset=3D2166 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000" -/* offset=3D2246 */ "uncore_imc_free_running\000" -/* offset=3D2270 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000" -/* offset=3D2365 */ "uncore_imc\000" -/* offset=3D2376 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000" -/* offset=3D2454 */ "uncore_sys_ddr_pmu\000" -/* offset=3D2473 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000" -/* offset=3D2546 */ "uncore_sys_ccn_pmu\000" -/* offset=3D2565 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000" -/* offset=3D2639 */ "uncore_sys_cmn_pmu\000" -/* offset=3D2658 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000" -/* offset=3D2798 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=3D2820 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" -/* offset=3D2883 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D3049 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3113 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3180 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D3251 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D3345 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" -/* offset=3D3479 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D3543 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3611 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3681 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3D3703 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3D3725 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D3745 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D5 */ "duration_time\000tool\000Wall clock interval time in nan= oseconds\000config=3D1\000\00000\000\000\000" +/* offset=3D79 */ "user_time\000tool\000User (non-kernel) time in nanoseco= nds\000config=3D2\000\00000\000\000\000" +/* offset=3D147 */ "system_time\000tool\000System/kernel time in nanosecon= ds\000config=3D3\000\00000\000\000\000" +/* offset=3D213 */ "has_pmem\000tool\0001 if persistent memory installed o= therwise 0\000config=3D4\000\00000\000\000\000" +/* offset=3D287 */ "num_cores\000tool\000Number of cores. A core consists = of 1 or more thread, with each thread being associated with a logical Linux= CPU\000config=3D5\000\00000\000\000\000" +/* offset=3D430 */ "num_cpus\000tool\000Number of logical Linux CPUs. Ther= e may be multiple such CPUs on a core\000config=3D6\000\00000\000\000\000" +/* offset=3D531 */ "num_cpus_online\000tool\000Number of online logical Li= nux CPUs. There may be multiple such CPUs on a core\000config=3D7\000\00000= \000\000\000" +/* offset=3D646 */ "num_dies\000tool\000Number of dies. Each die has 1 or = more cores\000config=3D8\000\00000\000\000\000" +/* offset=3D720 */ "num_packages\000tool\000Number of packages. Each packa= ge has 1 or more die\000config=3D9\000\00000\000\000\000" +/* offset=3D804 */ "slots\000tool\000Number of functional units that in pa= rallel can execute parts of an instruction\000config=3D0xa\000\00000\000\00= 0\000" +/* offset=3D912 */ "smt_on\000tool\0001 if simultaneous multithreading (ak= a hyperthreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\0= 00" +/* offset=3D1017 */ "system_tsc_freq\000tool\000The amount a Time Stamp Co= unter (TSC) increases per second\000config=3D0xc\000\00000\000\000\000" +/* offset=3D1114 */ "default_core\000" +/* offset=3D1127 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000e= vent=3D0x8a\000\00000\000\000\000" +/* offset=3D1187 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000e= vent=3D0x8b\000\00000\000\000\000" +/* offset=3D1247 */ "l3_cache_rd\000cache\000L3 cache access, read\000even= t=3D0x40\000\00000\000Attributable Level 3 cache access, read\000\000" +/* offset=3D1343 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,= 1\000" +/* offset=3D1446 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20\000\00000\000\0000,1\000" +/* offset=3D1580 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\0= 0000\000\0000,1\000" +/* offset=3D1699 */ "hisi_sccl,ddrc\000" +/* offset=3D1714 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000\000" +/* offset=3D1801 */ "uncore_cbox\000" +/* offset=3D1813 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted fro= m L3 Eviction which misses in some processor core\0000,1\000" +/* offset=3D2048 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000\000" +/* offset=3D2114 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" +/* offset=3D2186 */ "hisi_sccl,l3c\000" +/* offset=3D2200 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000\000" +/* offset=3D2281 */ "uncore_imc_free_running\000" +/* offset=3D2305 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000\000" +/* offset=3D2401 */ "uncore_imc\000" +/* offset=3D2412 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000\000" +/* offset=3D2491 */ "uncore_sys_ddr_pmu\000" +/* offset=3D2510 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000" +/* offset=3D2584 */ "uncore_sys_ccn_pmu\000" +/* offset=3D2603 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000" +/* offset=3D2678 */ "uncore_sys_cmn_pmu\000" +/* offset=3D2697 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000" +/* offset=3D2838 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" +/* offset=3D2860 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" +/* offset=3D2923 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3D3089 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3153 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3220 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3D3291 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3D3385 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" +/* offset=3D3519 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" +/* offset=3D3583 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3651 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3721 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" +/* offset=3D3743 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" +/* offset=3D3765 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3D3785 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" ; =20 static const struct compact_pmu_event pmu_events__common_tool[] =3D { -{ 5 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds= \000config=3D1\000\00000\000\000 */ -{ 210 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise= 0\000config=3D4\000\00000\000\000 */ -{ 283 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or = more thread, with each thread being associated with a logical Linux CPU\000= config=3D5\000\00000\000\000 */ -{ 425 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be= multiple such CPUs on a core\000config=3D6\000\00000\000\000 */ -{ 525 }, /* num_cpus_online\000tool\000Number of online logical Linux CPUs= . There may be multiple such CPUs on a core\000config=3D7\000\00000\000\000= */ -{ 639 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cor= es\000config=3D8\000\00000\000\000 */ -{ 712 }, /* num_packages\000tool\000Number of packages. Each package has 1= or more die\000config=3D9\000\00000\000\000 */ -{ 795 }, /* slots\000tool\000Number of functional units that in parallel c= an execute parts of an instruction\000config=3D0xa\000\00000\000\000 */ -{ 902 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hypert= hreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000 */ -{ 145 }, /* system_time\000tool\000System/kernel time in nanoseconds\000co= nfig=3D3\000\00000\000\000 */ -{ 1006 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (T= SC) increases per second\000config=3D0xc\000\00000\000\000 */ -{ 78 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000c= onfig=3D2\000\00000\000\000 */ +{ 5 }, /* duration_time\000tool\000Wall clock interval time in nanoseconds= \000config=3D1\000\00000\000\000\000 */ +{ 213 }, /* has_pmem\000tool\0001 if persistent memory installed otherwise= 0\000config=3D4\000\00000\000\000\000 */ +{ 287 }, /* num_cores\000tool\000Number of cores. A core consists of 1 or = more thread, with each thread being associated with a logical Linux CPU\000= config=3D5\000\00000\000\000\000 */ +{ 430 }, /* num_cpus\000tool\000Number of logical Linux CPUs. There may be= multiple such CPUs on a core\000config=3D6\000\00000\000\000\000 */ +{ 531 }, /* num_cpus_online\000tool\000Number of online logical Linux CPUs= . There may be multiple such CPUs on a core\000config=3D7\000\00000\000\000= \000 */ +{ 646 }, /* num_dies\000tool\000Number of dies. Each die has 1 or more cor= es\000config=3D8\000\00000\000\000\000 */ +{ 720 }, /* num_packages\000tool\000Number of packages. Each package has 1= or more die\000config=3D9\000\00000\000\000\000 */ +{ 804 }, /* slots\000tool\000Number of functional units that in parallel c= an execute parts of an instruction\000config=3D0xa\000\00000\000\000\000 */ +{ 912 }, /* smt_on\000tool\0001 if simultaneous multithreading (aka hypert= hreading) is enable otherwise 0\000config=3D0xb\000\00000\000\000\000 */ +{ 147 }, /* system_time\000tool\000System/kernel time in nanoseconds\000co= nfig=3D3\000\00000\000\000\000 */ +{ 1017 }, /* system_tsc_freq\000tool\000The amount a Time Stamp Counter (T= SC) increases per second\000config=3D0xc\000\00000\000\000\000 */ +{ 79 }, /* user_time\000tool\000User (non-kernel) time in nanoseconds\000c= onfig=3D2\000\00000\000\000\000 */ =20 }; =20 @@ -99,29 +99,29 @@ const struct pmu_table_entry pmu_events__common[] =3D { }; =20 static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { -{ 1115 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0= x8a\000\00000\000\000 */ -{ 1174 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0= x8b\000\00000\000\000 */ -{ 1427 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20\000\00000\000\000 */ -{ 1557 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000= \000 */ -{ 1233 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40= \000\00000\000Attributable Level 3 cache access, read\000 */ -{ 1328 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\000 */ +{ 1127 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0= x8a\000\00000\000\000\000 */ +{ 1187 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0= x8b\000\00000\000\000\000 */ +{ 1446 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20\000\00000\000\0000,1\000 */ +{ 1580 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000= \0000,1\000 */ +{ 1247 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40= \000\00000\000Attributable Level 3 cache access, read\000\000 */ +{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { -{ 1687 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000 */ +{ 1714 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { -{ 2166 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000 */ +{ 2200 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { -{ 2016 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000 */ -{ 2081 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000 */ -{ 1785 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted from L3 Evi= ction which misses in some processor core\000 */ +{ 2048 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000\000 */ +{ 2114 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000\000 */ +{ 1813 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted from L3 Evi= ction which misses in some processor core\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { -{ 2376 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000 */ +{ 2412 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { -{ 2270 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000 */ +{ 2305 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000\000 */ =20 }; =20 @@ -129,51 +129,51 @@ const struct pmu_table_entry pmu_events__test_soc_cpu= [] =3D { { .entries =3D pmu_events__test_soc_cpu_default_core, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_default_core), - .pmu_name =3D { 1102 /* default_core\000 */ }, + .pmu_name =3D { 1114 /* default_core\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 1672 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 1699 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 2152 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 2186 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 1773 /* uncore_cbox\000 */ }, + .pmu_name =3D { 1801 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 2365 /* uncore_imc\000 */ }, + .pmu_name =3D { 2401 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_= running), - .pmu_name =3D { 2246 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 2281 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 2798 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 3479 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ -{ 3251 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 3345 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ -{ 3543 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ -{ 3611 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 2883 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 2820 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ -{ 3745 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ -{ 3681 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 3703 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 3725 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 3180 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ -{ 3049 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ -{ 3113 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ +{ 2838 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 3519 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ +{ 3291 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 3385 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ +{ 3583 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ +{ 3651 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ +{ 2923 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 2860 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ +{ 3785 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ +{ 3721 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 3743 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 3765 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 3220 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ +{ 3089 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ +{ 3153 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ =20 }; =20 @@ -181,18 +181,18 @@ const struct pmu_table_entry pmu_metrics__test_soc_cp= u[] =3D { { .entries =3D pmu_metrics__test_soc_cpu_default_core, .num_entries =3D ARRAY_SIZE(pmu_metrics__test_soc_cpu_default_core), - .pmu_name =3D { 1102 /* default_core\000 */ }, + .pmu_name =3D { 1114 /* default_core\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { -{ 2565 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000 */ +{ 2603 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { -{ 2658 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000 */ +{ 2697 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { -{ 2473 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000 */ +{ 2510 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000 */ =20 }; =20 @@ -200,17 +200,17 @@ const struct pmu_table_entry pmu_events__test_soc_sys= [] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_p= mu), - .pmu_name =3D { 2546 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 2584 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_p= mu), - .pmu_name =3D { 2639 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 2678 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_p= mu), - .pmu_name =3D { 2454 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 2491 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 @@ -227,6 +227,12 @@ struct pmu_metrics_table { uint32_t num_pmus; }; =20 +/* Struct used to make the PMU counter layout table implementation opaque = to callers. */ +struct pmu_layouts_table { + const struct compact_pmu_event *entries; + size_t length; +}; + /* * Map a CPU to its table of PMU events. The CPU is identified by the * cpuid field, which is an arch-specific identifier for the CPU. @@ -240,6 +246,7 @@ struct pmu_events_map { const char *cpuid; struct pmu_events_table event_table; struct pmu_metrics_table metric_table; + struct pmu_layouts_table layout_table; }; =20 /* @@ -273,6 +280,7 @@ const struct pmu_events_map pmu_events_map[] =3D { .cpuid =3D 0, .event_table =3D { 0, 0 }, .metric_table =3D { 0, 0 }, + .layout_table =3D { 0, 0 }, } }; =20 @@ -317,6 +325,8 @@ static void decompress_event(int offset, struct pmu_eve= nt *pe) pe->unit =3D (*p =3D=3D '\0' ? NULL : p); while (*p++); pe->long_desc =3D (*p =3D=3D '\0' ? NULL : p); + while (*p++); + pe->counters_list =3D (*p =3D=3D '\0' ? NULL : p); } =20 static void decompress_metric(int offset, struct pmu_metric *pm) @@ -348,6 +358,19 @@ static void decompress_metric(int offset, struct pmu_m= etric *pm) pm->event_grouping =3D *p - '0'; } =20 +static void decompress_layout(int offset, struct pmu_layout *pm) +{ + const char *p =3D &big_c_string[offset]; + + pm->pmu =3D (*p =3D=3D '\0' ? NULL : p); + while (*p++); + pm->desc =3D (*p =3D=3D '\0' ? NULL : p); + p++; + pm->counters_num_gp =3D *p - '0'; + p++; + pm->counters_num_fixed =3D *p - '0'; +} + static int pmu_events_table__for_each_event_pmu(const struct pmu_events_ta= ble *table, const struct pmu_table_ent= ry *pmu, pmu_event_iter_fn fn, @@ -503,6 +526,21 @@ int pmu_metrics_table__for_each_metric(const struct pm= u_metrics_table *table, return 0; } =20 +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *tab= le, + pmu_layout_iter_fn fn, + void *data) { + for (size_t i =3D 0; i < table->length; i++) { + struct pmu_layout pm; + int ret; + + decompress_layout(table->entries[i].offset, &pm); + ret =3D fn(&pm, data); + if (ret) + return ret; + } + return 0; +} + static const struct pmu_events_map *map_for_cpu(struct perf_cpu cpu) { static struct { @@ -595,6 +633,34 @@ const struct pmu_metrics_table *pmu_metrics_table__fin= d(void) return map ? &map->metric_table : NULL; } =20 +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void) +{ + const struct pmu_layouts_table *table =3D NULL; + struct perf_cpu cpu =3D {-1}; + char *cpuid =3D get_cpuid_allow_env_override(cpu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i =3D 0; + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + if (!map->arch) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table =3D &map->layout_table; + break; + } + } + free(cpuid); + return table; +} + const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid) { for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; @@ -616,6 +682,16 @@ const struct pmu_metrics_table *find_core_metrics_tabl= e(const char *arch, const } return NULL; } +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, = const char *cpuid) +{ + for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; + tables->arch; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(table= s->cpuid, cpuid)) + return &tables->layout_table; + } + return NULL; +} =20 int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { @@ -644,6 +720,19 @@ int pmu_for_each_core_metric(pmu_metric_iter_fn fn, vo= id *data) return 0; } =20 +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; + tables->arch; + tables++) { + int ret =3D pmu_layouts_table__for_each_layout(&tables->la= yout_table, fn, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables =3D &pmu_sys_event_tables= [0]; diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index d781a377757a..5fd906ac6642 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -23,6 +23,8 @@ _metric_tables =3D [] _sys_metric_tables =3D [] # Mapping between sys event table names and sys metric table names. _sys_event_table_to_metric_table_mapping =3D {} +# List of regular PMU counter layout tables. +_pmu_layouts_tables =3D [] # Map from an event name to an architecture standard # JsonEvent. Architecture standard events are in json files in the top # f'{_args.starting_dir}/{_args.arch}' directory. @@ -31,6 +33,10 @@ _arch_std_events =3D {} _pending_events =3D [] # Name of events table to be written out _pending_events_tblname =3D None +# PMU counter layout to write out when the layout table is closed +_pending_pmu_counts =3D [] +# Name of PMU counter layout table to be written out +_pending_pmu_counts_tblname =3D None # Metrics to write out when the table is closed _pending_metrics =3D [] # Name of metrics table to be written out @@ -51,6 +57,11 @@ _json_event_attributes =3D [ 'long_desc' ] =20 +# Attributes that are in pmu_unit_layout. +_json_layout_attributes =3D [ + 'pmu', 'desc' +] + # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes =3D [ 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', @@ -265,7 +276,7 @@ class JsonEvent: =20 def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" - if not unit: + if not unit or unit =3D=3D "core": return 'default_core' # Comment brought over from jevents.c: # it's not realistic to keep adding these, we need something more sc= alable ... @@ -336,6 +347,19 @@ class JsonEvent: if 'Errata' in jd: extra_desc +=3D ' Spec update: ' + jd['Errata'] self.pmu =3D unit_to_pmu(jd.get('Unit')) + # The list of counter(s) the event could be collected with + class Counter: + gp =3D str() + fixed =3D str() + self.counters =3D {'list': str(), 'num': Counter()} + self.counters['list'] =3D jd.get('Counter') + # Number of generic counter + self.counters['num'].gp =3D jd.get('CountersNumGeneric') + # Number of fixed counter + self.counters['num'].fixed =3D jd.get('CountersNumFixed') + # If the event uses an MSR, other event uses the same MSR could not be + # schedule to collect at the same time. + self.msr =3D jd.get('MSRIndex') filter =3D jd.get('Filter') self.unit =3D jd.get('ScaleUnit') self.perpkg =3D jd.get('PerPkg') @@ -411,8 +435,20 @@ class JsonEvent: s +=3D f'\t{attr} =3D {value},\n' return s + '}' =20 - def build_c_string(self, metric: bool) -> str: + def build_c_string(self, metric: bool, layout: bool) -> str: s =3D '' + if layout: + for attr in _json_layout_attributes: + x =3D getattr(self, attr) + if attr in _json_enum_attributes: + s +=3D x if x else '0' + else: + s +=3D f'{x}\\000' if x else '\\000' + x =3D self.counters['num'].gp + s +=3D x if x else '0' + x =3D self.counters['num'].fixed + s +=3D x if x else '0' + return s for attr in _json_metric_attributes if metric else _json_event_attribu= tes: x =3D getattr(self, attr) if metric and x and attr =3D=3D 'metric_expr': @@ -425,12 +461,15 @@ class JsonEvent: s +=3D x if x else '0' else: s +=3D f'{x}\\000' if x else '\\000' + if not metric: + x =3D self.counters['list'] + s +=3D f'{x}\\000' if x else '\\000' return s =20 - def to_c_string(self, metric: bool) -> str: + def to_c_string(self, metric: bool, layout: bool) -> str: """Representation of the event as a C struct initializer.""" =20 - s =3D self.build_c_string(metric) + s =3D self.build_c_string(metric, layout) return f'{{ { _bcs.offsets[s] } }}, /* {s} */\n' =20 =20 @@ -467,6 +506,8 @@ def preprocess_arch_std_files(archpath: str) -> None: _arch_std_events[event.name.lower()] =3D event if event.metric_name: _arch_std_events[event.metric_name.lower()] =3D event + if event.counters['num'].gp: + _arch_std_events[event.pmu.lower()] =3D event =20 =20 def add_events_table_entries(item: os.DirEntry, topic: str) -> None: @@ -476,6 +517,8 @@ def add_events_table_entries(item: os.DirEntry, topic: = str) -> None: _pending_events.append(e) if e.metric_name: _pending_metrics.append(e) + if e.counters['num'].gp: + _pending_pmu_counts.append(e) =20 =20 def print_pending_events() -> None: @@ -519,8 +562,8 @@ def print_pending_events() -> None: last_pmu =3D event.pmu pmus.add((event.pmu, pmu_name)) =20 - _args.output_file.write(event.to_c_string(metric=3DFalse)) last_name =3D event.name + _args.output_file.write(event.to_c_string(metric=3DFalse, layout=3DFal= se)) _pending_events =3D [] =20 _args.output_file.write(f""" @@ -575,7 +618,7 @@ def print_pending_metrics() -> None: last_pmu =3D metric.pmu pmus.add((metric.pmu, pmu_name)) =20 - _args.output_file.write(metric.to_c_string(metric=3DTrue)) + _args.output_file.write(metric.to_c_string(metric=3DTrue, layout=3DFal= se)) _pending_metrics =3D [] =20 _args.output_file.write(f""" @@ -593,6 +636,35 @@ const struct pmu_table_entry {_pending_metrics_tblname= }[] =3D {{ """) _args.output_file.write('};\n\n') =20 +def print_pending_pmu_counter_layout_table() -> None: + '''Print counter layout data from counter.json file to counter layout ta= ble in + c-string''' + + def pmu_counts_cmp_key(j: JsonEvent) -> Tuple[bool, str, str]: + def fix_none(s: Optional[str]) -> str: + if s is None: + return '' + return s + + return (j.desc is not None, fix_none(j.pmu)) + + global _pending_pmu_counts + if not _pending_pmu_counts: + return + + global _pending_pmu_counts_tblname + global pmu_layouts_tables + _pmu_layouts_tables.append(_pending_pmu_counts_tblname) + + _args.output_file.write( + f'static const struct compact_pmu_event {_pending_pmu_counts_tblname= }[] =3D {{\n') + + for pmu_layout in sorted(_pending_pmu_counts, key=3Dpmu_counts_cmp_key): + _args.output_file.write(pmu_layout.to_c_string(metric=3DFalse, layout= =3DTrue)) + _pending_pmu_counts =3D [] + + _args.output_file.write('};\n\n') + def get_topic(topic: str) -> str: if topic.endswith('metrics.json'): return 'metrics' @@ -629,10 +701,12 @@ def preprocess_one_file(parents: Sequence[str], item:= os.DirEntry) -> None: pmu_name =3D f"{event.pmu}\\000" if event.name: _bcs.add(pmu_name, metric=3DFalse) - _bcs.add(event.build_c_string(metric=3DFalse), metric=3DFalse) + _bcs.add(event.build_c_string(metric=3DFalse, layout=3DFalse), metri= c=3DFalse) if event.metric_name: _bcs.add(pmu_name, metric=3DTrue) - _bcs.add(event.build_c_string(metric=3DTrue), metric=3DTrue) + _bcs.add(event.build_c_string(metric=3DTrue, layout=3DFalse), metric= =3DTrue) + if event.counters['num'].gp: + _bcs.add(event.build_c_string(metric=3DFalse, layout=3DTrue), metric= =3DFalse) =20 def process_one_file(parents: Sequence[str], item: os.DirEntry) -> None: """Process a JSON file during the main walk.""" @@ -649,11 +723,14 @@ def process_one_file(parents: Sequence[str], item: os= .DirEntry) -> None: if item.is_dir() and is_leaf_dir_ignoring_sys(item.path): print_pending_events() print_pending_metrics() + print_pending_pmu_counter_layout_table() =20 global _pending_events_tblname _pending_events_tblname =3D file_name_to_table_name('pmu_events_', par= ents, item.name) global _pending_metrics_tblname _pending_metrics_tblname =3D file_name_to_table_name('pmu_metrics_', p= arents, item.name) + global _pending_pmu_counts_tblname + _pending_pmu_counts_tblname =3D file_name_to_table_name('pmu_layouts_'= , parents, item.name) =20 if item.name =3D=3D 'sys': _sys_event_table_to_metric_table_mapping[_pending_events_tblname] = =3D _pending_metrics_tblname @@ -687,6 +764,12 @@ struct pmu_metrics_table { uint32_t num_pmus; }; =20 +/* Struct used to make the PMU counter layout table implementation opaque = to callers. */ +struct pmu_layouts_table { + const struct compact_pmu_event *entries; + size_t length; +}; + /* * Map a CPU to its table of PMU events. The CPU is identified by the * cpuid field, which is an arch-specific identifier for the CPU. @@ -700,6 +783,7 @@ struct pmu_events_map { const char *cpuid; struct pmu_events_table event_table; struct pmu_metrics_table metric_table; + struct pmu_layouts_table layout_table; }; =20 /* @@ -755,6 +839,12 @@ const struct pmu_events_map pmu_events_map[] =3D { metric_size =3D '0' if event_size =3D=3D '0' and metric_size =3D=3D '0': continue + layout_tblname =3D file_name_to_table_name('pmu_layouts_', [],= row[2].replace('/', '_')) + if layout_tblname in _pmu_layouts_tables: + layout_size =3D f'ARRAY_SIZE({layout_tblname})' + else: + layout_tblname =3D 'NULL' + layout_size =3D '0' cpuid =3D row[0].replace('\\', '\\\\') _args.output_file.write(f"""{{ \t.arch =3D "{arch}", @@ -766,6 +856,10 @@ const struct pmu_events_map pmu_events_map[] =3D { \t.metric_table =3D {{ \t\t.pmus =3D {metric_tblname}, \t\t.num_pmus =3D {metric_size} +\t}}, +\t.layout_table =3D {{ +\t\t.entries =3D {layout_tblname}, +\t\t.length =3D {layout_size} \t}} }}, """) @@ -776,6 +870,7 @@ const struct pmu_events_map pmu_events_map[] =3D { \t.cpuid =3D 0, \t.event_table =3D { 0, 0 }, \t.metric_table =3D { 0, 0 }, +\t.layout_table =3D { 0, 0 }, } }; """) @@ -844,6 +939,9 @@ static void decompress_event(int offset, struct pmu_eve= nt *pe) _args.output_file.write('\tp++;') else: _args.output_file.write('\twhile (*p++);') + _args.output_file.write('\twhile (*p++);') + _args.output_file.write(f'\n\tpe->counters_list =3D ') + _args.output_file.write("(*p =3D=3D '\\0' ? NULL : p);\n") _args.output_file.write("""} =20 static void decompress_metric(int offset, struct pmu_metric *pm) @@ -864,6 +962,30 @@ static void decompress_metric(int offset, struct pmu_m= etric *pm) _args.output_file.write('\twhile (*p++);') _args.output_file.write("""} =20 +static void decompress_layout(int offset, struct pmu_layout *pm) +{ +\tconst char *p =3D &big_c_string[offset]; +""") + for attr in _json_layout_attributes: + _args.output_file.write(f'\n\tpm->{attr} =3D ') + if attr in _json_enum_attributes: + _args.output_file.write("*p - '0';\n") + else: + _args.output_file.write("(*p =3D=3D '\\0' ? NULL : p);\n") + if attr =3D=3D _json_layout_attributes[-1]: + continue + if attr in _json_enum_attributes: + _args.output_file.write('\tp++;') + else: + _args.output_file.write('\twhile (*p++);') + _args.output_file.write('\tp++;') + _args.output_file.write(f'\n\tpm->counters_num_gp =3D ') + _args.output_file.write("*p - '0';\n") + _args.output_file.write('\tp++;') + _args.output_file.write(f'\n\tpm->counters_num_fixed =3D ') + _args.output_file.write("*p - '0';\n") + _args.output_file.write("""} + static int pmu_events_table__for_each_event_pmu(const struct pmu_events_ta= ble *table, const struct pmu_table_ent= ry *pmu, pmu_event_iter_fn fn, @@ -1019,6 +1141,21 @@ int pmu_metrics_table__for_each_metric(const struct = pmu_metrics_table *table, return 0; } =20 +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *tab= le, + pmu_layout_iter_fn fn, + void *data) { + for (size_t i =3D 0; i < table->length; i++) { + struct pmu_layout pm; + int ret; + + decompress_layout(table->entries[i].offset, &pm); + ret =3D fn(&pm, data); + if (ret) + return ret; + } + return 0; +} + static const struct pmu_events_map *map_for_cpu(struct perf_cpu cpu) { static struct { @@ -1111,6 +1248,34 @@ const struct pmu_metrics_table *pmu_metrics_table__f= ind(void) return map ? &map->metric_table : NULL; } =20 +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void) +{ + const struct pmu_layouts_table *table =3D NULL; + struct perf_cpu cpu =3D {-1}; + char *cpuid =3D get_cpuid_allow_env_override(cpu); + int i; + + /* on some platforms which uses cpus map, cpuid can be NULL for + * PMUs other than CORE PMUs. + */ + if (!cpuid) + return NULL; + + i =3D 0; + for (;;) { + const struct pmu_events_map *map =3D &pmu_events_map[i++]; + if (!map->arch) + break; + + if (!strcmp_cpuid_str(map->cpuid, cpuid)) { + table =3D &map->layout_table; + break; + } + } + free(cpuid); + return table; +} + const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid) { for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; @@ -1132,6 +1297,16 @@ const struct pmu_metrics_table *find_core_metrics_ta= ble(const char *arch, const } return NULL; } +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, = const char *cpuid) +{ + for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; + tables->arch; + tables++) { + if (!strcmp(tables->arch, arch) && !strcmp_cpuid_str(table= s->cpuid, cpuid)) + return &tables->layout_table; + } + return NULL; +} =20 int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data) { @@ -1160,6 +1335,19 @@ int pmu_for_each_core_metric(pmu_metric_iter_fn fn, = void *data) return 0; } =20 +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data) +{ + for (const struct pmu_events_map *tables =3D &pmu_events_map[0]; + tables->arch; + tables++) { + int ret =3D pmu_layouts_table__for_each_layout(&tables->la= yout_table, fn, data); + + if (ret) + return ret; + } + return 0; +} + const struct pmu_events_table *find_sys_events_table(const char *name) { for (const struct pmu_sys_events *tables =3D &pmu_sys_event_tables= [0]; @@ -1320,6 +1508,7 @@ struct pmu_table_entry { ftw(arch_path, [], process_one_file) print_pending_events() print_pending_metrics() + print_pending_pmu_counter_layout_table() =20 print_mapping_table(archs) print_system_mapping_table() diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index 675562e6f770..9a5cbec32513 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -45,6 +45,11 @@ struct pmu_event { const char *desc; const char *topic; const char *long_desc; + /** + * The list of counter(s) the event could be collected on. + * eg., "0,1,2,3,4,5,6,7". + */ + const char *counters_list; const char *pmu; const char *unit; bool perpkg; @@ -67,8 +72,18 @@ struct pmu_metric { enum metric_event_groups event_grouping; }; =20 +struct pmu_layout { + const char *pmu; + const char *desc; + /** Total number of generic counters*/ + int counters_num_gp; + /** Total number of fixed counters. Set to zero if no fixed counter on th= e unit.*/ + int counters_num_fixed; +}; + struct pmu_events_table; struct pmu_metrics_table; +struct pmu_layouts_table; =20 #define PMU_EVENTS__NOT_FOUND -1000 =20 @@ -80,6 +95,9 @@ typedef int (*pmu_metric_iter_fn)(const struct pmu_metric= *pm, const struct pmu_metrics_table *table, void *data); =20 +typedef int (*pmu_layout_iter_fn)(const struct pmu_layout *pm, + void *data); + int pmu_events_table__for_each_event(const struct pmu_events_table *table, struct perf_pmu *pmu, pmu_event_iter_fn fn, @@ -92,10 +110,13 @@ int pmu_events_table__for_each_event(const struct pmu_= events_table *table, * search of all tables. */ int pmu_events_table__find_event(const struct pmu_events_table *table, - struct perf_pmu *pmu, - const char *name, - pmu_event_iter_fn fn, - void *data); + struct perf_pmu *pmu, + const char *name, + pmu_event_iter_fn fn, + void *data); +int pmu_layouts_table__for_each_layout(const struct pmu_layouts_table *tab= le, + pmu_layout_iter_fn fn, + void *data); size_t pmu_events_table__num_events(const struct pmu_events_table *table, struct perf_pmu *pmu); =20 @@ -104,10 +125,13 @@ int pmu_metrics_table__for_each_metric(const struct p= mu_metrics_table *table, pm =20 const struct pmu_events_table *perf_pmu__find_events_table(struct perf_pmu= *pmu); const struct pmu_metrics_table *pmu_metrics_table__find(void); +const struct pmu_layouts_table *perf_pmu__find_layouts_table(void); const struct pmu_events_table *find_core_events_table(const char *arch, co= nst char *cpuid); const struct pmu_metrics_table *find_core_metrics_table(const char *arch, = const char *cpuid); +const struct pmu_layouts_table *find_core_layouts_table(const char *arch, = const char *cpuid); int pmu_for_each_core_event(pmu_event_iter_fn fn, void *data); int pmu_for_each_core_metric(pmu_metric_iter_fn fn, void *data); +int pmu_for_each_core_layout(pmu_layout_iter_fn fn, void *data); =20 const struct pmu_events_table *find_sys_events_table(const char *name); const struct pmu_metrics_table *find_sys_metrics_table(const char *name); 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Mon, 27 Jan 2025 20:59:52 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:43 -0800 Subject: [PATCH v3 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-2-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Kaiwen Xue X-Mailer: b4 0.15-dev-13183 From: Kaiwen Xue This adds definitions of new CSRs and bits defined in Sxcsrind ISA extension. These CSR enables indirect accesses mechanism to access any CSRs in M-, S-, and VS-mode. The range of the select values and ireg will be define by the ISA extension using Sxcsrind extension. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 37bdea65bbd8..2ad2d492e6b4 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -318,6 +318,12 @@ /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 =20 /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c @@ -365,6 +371,14 @@ /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)= */ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +/* + * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcs= rind) + */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VISREG6 0x257 =20 /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c @@ -407,6 +421,12 @@ /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +/* Machine-Level Window to Indrecitly Accessed Registers (Sxcsrind) */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 =20 /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c @@ -452,6 +472,11 @@ # define CSR_IEH CSR_MIEH # define CSR_ISELECT CSR_MISELECT # define CSR_IREG CSR_MIREG +# define CSR_IREG2 CSR_MIREG2 +# define CSR_IREG3 CSR_MIREG3 +# define CSR_IREG4 CSR_MIREG4 +# define CSR_IREG5 CSR_MIREG5 +# define CSR_IREG6 CSR_MIREG6 # define CSR_IPH CSR_MIPH # define CSR_TOPEI CSR_MTOPEI # define CSR_TOPI CSR_MTOPI @@ -477,6 +502,11 @@ # define CSR_IEH CSR_SIEH # define CSR_ISELECT CSR_SISELECT # define CSR_IREG CSR_SIREG +# define CSR_IREG2 CSR_SIREG2 +# define CSR_IREG3 CSR_SIREG3 +# define CSR_IREG4 CSR_SIREG4 +# define CSR_IREG5 CSR_SIREG5 +# define CSR_IREG6 CSR_SIREG6 # define CSR_IPH CSR_SIPH # define CSR_TOPEI CSR_STOPEI # define CSR_TOPI CSR_STOPI --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0FF81DD0C7 for ; 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This patch just enables the definition and parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 869da082252a..3d6e706fc5b2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -100,6 +100,8 @@ #define RISCV_ISA_EXT_ZICCRSE 91 #define RISCV_ISA_EXT_SVADE 92 #define RISCV_ISA_EXT_SVADU 93 +#define RISCV_ISA_EXT_SSCSRIND 94 +#define RISCV_ISA_EXT_SMCSRIND 95 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 @@ -109,9 +111,12 @@ #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..d3259b640115 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -393,7 +393,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), + __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8061DE8A2 for ; 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Signed-off-by: Atish Patra Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 16 +++++++++++++= +++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 9c7dd7e75e0c..f47d829545db 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -146,6 +146,22 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enab= le. =20 + - const: smcsrind + description: | + The standard Smcsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. = This + extension allows other ISA extension to use indirect CSR access + mechanism in M-mode as ratified in the 20240326 version of the + privileged ISA specification. + + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. = This + extension allows other ISA extension to use indirect CSR access + mechanism in S-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140791C5F3F for ; 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Mon, 27 Jan 2025 20:59:57 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.20.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 20:59:57 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:46 -0800 Subject: [PATCH v3 05/21] RISC-V: Define indirect CSR access helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-5-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The indriect CSR requires multiple instructions to read/write CSR. Add a few helper functions for ease of usage. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr_ind.h | 42 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_= ind.h new file mode 100644 index 000000000000..d36e1e06ed2b --- /dev/null +++ b/arch/riscv/include/asm/csr_ind.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef _ASM_RISCV_CSR_IND_H +#define _ASM_RISCV_CSR_IND_H + +#include + +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long value =3D 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + value =3D csr_read(iregcsr); \ + local_irq_restore(flags); \ + value; \ +}) + +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + csr_write(iregcsr, value); \ + local_irq_restore(flags); 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Mon, 27 Jan 2025 20:59:59 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.20.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 20:59:58 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:47 -0800 Subject: [PATCH v3 06/21] RISC-V: Add Sscfg extension CSR definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-6-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Kaiwen Xue X-Mailer: b4 0.15-dev-13183 From: Kaiwen Xue This adds the scountinhibit CSR definition and S-mode accessible hpmevent bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop counters directly from S-mode without invoking SBI calls to M-mode. It is also used to figure out the counters delegated to S-mode by the M-mode as well. Signed-off-by: Kaiwen Xue --- arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2ad2d492e6b4..42b7f4f7ec0f 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -224,6 +224,31 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */ +#ifdef CONFIG_64BIT +#define HPMEVENT_OF (_UL(1) << 63) +#define HPMEVENT_MINH (_UL(1) << 62) +#define HPMEVENT_SINH (_UL(1) << 61) +#define HPMEVENT_UINH (_UL(1) << 60) +#define HPMEVENT_VSINH (_UL(1) << 59) +#define HPMEVENT_VUINH (_UL(1) << 58) +#else +#define HPMEVENTH_OF (_ULL(1) << 31) +#define HPMEVENTH_MINH (_ULL(1) << 30) +#define HPMEVENTH_SINH (_ULL(1) << 29) +#define HPMEVENTH_UINH (_ULL(1) << 28) +#define HPMEVENTH_VSINH (_ULL(1) << 27) +#define HPMEVENTH_VUINH (_ULL(1) << 26) + +#define HPMEVENT_OF (HPMEVENTH_OF << 32) +#define HPMEVENT_MINH (HPMEVENTH_MINH << 32) +#define HPMEVENT_SINH (HPMEVENTH_SINH << 32) +#define HPMEVENT_UINH (HPMEVENTH_UINH << 32) +#define HPMEVENT_VSINH (HPMEVENTH_VSINH << 32) +#define HPMEVENT_VUINH (HPMEVENTH_VUINH << 32) +#endif + +#define SISELECT_SSCCFG_BASE 0x40 =20 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM @@ -305,6 +330,7 @@ #define CSR_SCOUNTEREN 0x106 #define CSR_SENVCFG 0x10a #define CSR_SSTATEEN0 0x10c +#define CSR_SCOUNTINHIBIT 0x120 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 505F21DFD9C for ; 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Mon, 27 Jan 2025 21:00:00 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.20.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:00 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:48 -0800 Subject: [PATCH v3 07/21] RISC-V: Add Ssccfg ISA extension definition and parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-7-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Ssccfg (=E2=80=98Ss=E2=80=99 for Privileged architecture and Supervisor-lev= el extension, =E2=80=98ccfg=E2=80=99 for Counter Configuration) provides acces= s to delegated counters and new supervisor-level state. This patch just enables the definitions and enable parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 3d6e706fc5b2..2f5ef1dee7ac 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -102,6 +102,8 @@ #define RISCV_ISA_EXT_SVADU 93 #define RISCV_ISA_EXT_SSCSRIND 94 #define RISCV_ISA_EXT_SMCSRIND 95 +#define RISCV_ISA_EXT_SSCCFG 96 +#define RISCV_ISA_EXT_SMCDELEG 97 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d3259b640115..b584aa2d5bc3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -390,12 +390,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), + __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6FF81581F1 for ; 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Mon, 27 Jan 2025 21:00:02 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:02 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:49 -0800 Subject: [PATCH v3 08/21] dt-bindings: riscv: add Counter delegation ISA extensions description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-8-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Add description for the Smcdeleg/Ssccfg extension. Signed-off-by: Atish Patra Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 16 +++++++++++++= +++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index f47d829545db..1706a77729db 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,14 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smcdeleg + description: | + The standard Smcdeleg supervisor-level extension for the machi= ne mode + to delegate the hpmcounters to supvervisor mode so that they a= re + directlyi accessible in the supervisor mode as ratified in the + 20240213 version of the privileged ISA specification. This ext= ension + depends on Sscsrind, Zihpm, Zicntr extensions. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -169,6 +177,14 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of risc= v-aia. =20 + - const: ssccfg + description: | + The standard Ssccfg supervisor-level extension for configuring + the delegated hpmcounters to be accessible directly in supervi= sor + mode as ratified in the 20240213 version of the privileged ISA + specification. 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Mon, 27 Jan 2025 21:00:03 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:03 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:50 -0800 Subject: [PATCH v3 09/21] RISC-V: Add Smcntrpmf extension parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-9-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Smcntrpmf extension allows M-mode to enable privilege mode filtering for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are only available only in Ssccfg only Smcntrpmf is present. That's why, kernel needs to detect presence of Smcntrpmf extension and enable privilege mode filtering for cycle/instret counters. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2f5ef1dee7ac..42b34e2f80e8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -104,6 +104,7 @@ #define RISCV_ISA_EXT_SMCSRIND 95 #define RISCV_ISA_EXT_SSCCFG 96 #define RISCV_ISA_EXT_SMCDELEG 97 +#define RISCV_ISA_EXT_SMCNTRPMF 98 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b584aa2d5bc3..ec068c9130e5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -394,6 +394,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27D811F55F3 for ; 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Mon, 27 Jan 2025 21:00:05 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:05 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:51 -0800 Subject: [PATCH v3 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-10-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Add the description for Smcntrpmf ISA extension Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/extensions.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 1706a77729db..0afe47259c55 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -136,6 +136,14 @@ properties: 20240213 version of the privileged ISA specification. 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Mon, 27 Jan 2025 21:00:07 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:06 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:52 -0800 Subject: [PATCH v3 11/21] RISC-V: perf: Restructure the SBI PMU code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-11-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 With Ssccfg/Smcdeleg, we no longer need SBI PMU extension to program/ access hpmcounter/events. However, we do need it for firmware counters. Rename the driver and its related code to represent generic name that will handle both sbi and ISA mechanism for hpmcounter related operations. Take this opportunity to update the Kconfig names to match the new driver name closely. No functional change intended. Signed-off-by: Atish Patra --- MAINTAINERS | 4 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 +- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- arch/riscv/kvm/Makefile | 4 +- arch/riscv/kvm/vcpu_sbi.c | 2 +- drivers/perf/Kconfig | 16 +- drivers/perf/Makefile | 4 +- drivers/perf/{riscv_pmu.c =3D> riscv_pmu_common.c} | 0 drivers/perf/{riscv_pmu_sbi.c =3D> riscv_pmu_dev.c} | 206 +++++++++++++---= ------ include/linux/perf/riscv_pmu.h | 8 +- 10 files changed, 147 insertions(+), 103 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 30cbc3d44cd5..2ef7ff933266 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20177,9 +20177,9 @@ M: Atish Patra R: Anup Patel L: linux-riscv@lists.infradead.org S: Supported -F: drivers/perf/riscv_pmu.c +F: drivers/perf/riscv_pmu_common.c +F: drivers/perf/riscv_pmu_dev.c F: drivers/perf/riscv_pmu_legacy.c -F: drivers/perf/riscv_pmu_sbi.c =20 RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 1d85b6617508..aa75f52e9092 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -13,7 +13,7 @@ #include #include =20 -#ifdef CONFIG_RISCV_PMU_SBI +#ifdef CONFIG_RISCV_PMU #define RISCV_KVM_MAX_FW_CTRS 32 #define RISCV_KVM_MAX_HW_CTRS 32 #define RISCV_KVM_MAX_COUNTERS (RISCV_KVM_MAX_HW_CTRS + RISCV_KVM_MAX_FW_C= TRS) @@ -128,5 +128,5 @@ static inline int kvm_riscv_vcpu_pmu_incr_fw(struct kvm= _vcpu *vcpu, unsigned lon =20 static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} -#endif /* CONFIG_RISCV_PMU_SBI */ +#endif /* CONFIG_RISCV_PMU */ #endif /* !__KVM_VCPU_RISCV_PMU_H */ diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index b96705258cf9..764bb158e760 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -89,7 +89,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_s= ta; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; =20 -#ifdef CONFIG_RISCV_PMU_SBI +#ifdef CONFIG_RISCV_PMU extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu; #endif #endif /* __RISCV_KVM_VCPU_SBI_H__ */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 0fb1840c3e0a..f4ad7af0bdab 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -23,11 +23,11 @@ kvm-y +=3D vcpu_exit.o kvm-y +=3D vcpu_fp.o kvm-y +=3D vcpu_insn.o kvm-y +=3D vcpu_onereg.o -kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o +kvm-$(CONFIG_RISCV_PMU) +=3D vcpu_pmu.o kvm-y +=3D vcpu_sbi.o kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_hsm.o -kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_sbi_pmu.o +kvm-$(CONFIG_RISCV_PMU) +=3D vcpu_sbi_pmu.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_sta.o kvm-$(CONFIG_RISCV_SBI_V01) +=3D vcpu_sbi_v01.o diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 6e704ed86a83..4eaf9b0f736b 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -20,7 +20,7 @@ static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v= 01 =3D { }; #endif =20 -#ifndef CONFIG_RISCV_PMU_SBI +#ifndef CONFIG_RISCV_PMU static const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_pmu =3D { .extid_start =3D -1UL, .extid_end =3D -1UL, diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 4e268de351c4..b3bdff2a99a4 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -75,7 +75,7 @@ config ARM_XSCALE_PMU depends on ARM_PMU && CPU_XSCALE def_bool y =20 -config RISCV_PMU +config RISCV_PMU_COMMON depends on RISCV bool "RISC-V PMU framework" default y @@ -86,7 +86,7 @@ config RISCV_PMU can reuse it. =20 config RISCV_PMU_LEGACY - depends on RISCV_PMU + depends on RISCV_PMU_COMMON bool "RISC-V legacy PMU implementation" default y help @@ -95,15 +95,15 @@ config RISCV_PMU_LEGACY of cycle/instruction counter and doesn't support counter overflow, or programmable counters. It will be removed in future. =20 -config RISCV_PMU_SBI - depends on RISCV_PMU && RISCV_SBI - bool "RISC-V PMU based on SBI PMU extension" +config RISCV_PMU + depends on RISCV_PMU_COMMON && RISCV_SBI + bool "RISC-V PMU based on SBI PMU extension and/or Counter delegation ext= ension" default y help Say y if you want to use the CPU performance monitor - using SBI PMU extension on RISC-V based systems. This option provides - full perf feature support i.e. counter overflow, privilege mode - filtering, counter configuration. + using SBI PMU extension or counter delegation ISA extension on RISC-V + based systems. This option provides full perf feature support i.e. + counter overflow, privilege mode filtering, counter configuration. =20 config STARFIVE_STARLINK_PMU depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index de71d2574857..0805d740c773 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -16,9 +16,9 @@ obj-$(CONFIG_FSL_IMX9_DDR_PMU) +=3D fsl_imx9_ddr_perf.o obj-$(CONFIG_HISI_PMU) +=3D hisilicon/ obj-$(CONFIG_QCOM_L2_PMU) +=3D qcom_l2_pmu.o obj-$(CONFIG_QCOM_L3_PMU) +=3D qcom_l3_pmu.o -obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu.o +obj-$(CONFIG_RISCV_PMU_COMMON) +=3D riscv_pmu_common.o obj-$(CONFIG_RISCV_PMU_LEGACY) +=3D riscv_pmu_legacy.o -obj-$(CONFIG_RISCV_PMU_SBI) +=3D riscv_pmu_sbi.o +obj-$(CONFIG_RISCV_PMU) +=3D riscv_pmu_dev.o obj-$(CONFIG_STARFIVE_STARLINK_PMU) +=3D starfive_starlink_pmu.o obj-$(CONFIG_THUNDERX2_PMU) +=3D thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) +=3D xgene_pmu.o diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu_common.c similarity index 100% rename from drivers/perf/riscv_pmu.c rename to drivers/perf/riscv_pmu_common.c diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_dev.c similarity index 88% rename from drivers/perf/riscv_pmu_sbi.c rename to drivers/perf/riscv_pmu_dev.c index 1aa303f76cc7..b69654554288 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -8,7 +8,7 @@ * sparc64 and x86 code. */ =20 -#define pr_fmt(fmt) "riscv-pmu-sbi: " fmt +#define pr_fmt(fmt) "riscv-pmu-dev: " fmt =20 #include #include @@ -87,6 +87,8 @@ static const struct attribute_group *riscv_pmu_attr_group= s[] =3D { static int sysctl_perf_user_access __read_mostly =3D SYSCTL_USER_ACCESS; =20 /* + * This structure is SBI specific but counter delegation also require coun= ter + * width, csr mapping. Reuse it for now. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -119,7 +121,7 @@ struct sbi_pmu_event_data { }; }; =20 -static struct sbi_pmu_event_data pmu_hw_event_map[] =3D { +static struct sbi_pmu_event_data pmu_hw_event_sbi_map[] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D {.hw_gen_event =3D { SBI_PMU_HW_CPU_CYCLES, SBI_PMU_EVENT_TYPE_HW, 0}}, @@ -153,7 +155,7 @@ static struct sbi_pmu_event_data pmu_hw_event_map[] =3D= { }; =20 #define C(x) PERF_COUNT_HW_CACHE_##x -static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_M= AX] +static struct sbi_pmu_event_data pmu_cache_event_sbi_map[PERF_COUNT_HW_CAC= HE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { [C(L1D)] =3D { @@ -298,7 +300,7 @@ static struct sbi_pmu_event_data pmu_cache_event_map[PE= RF_COUNT_HW_CACHE_MAX] }, }; =20 -static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) +static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; =20 @@ -313,25 +315,25 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_= data *edata) } } =20 -static void pmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_sbi_check_std_events(struct work_struct *work) { for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - pmu_sbi_check_event(&pmu_hw_event_map[i]); + rvpmu_sbi_check_event(&pmu_hw_event_map[i]); =20 for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) - pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); + rvpmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); } =20 -static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); =20 -static int pmu_sbi_ctr_get_width(int idx) +static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; } =20 -static bool pmu_sbi_ctr_is_fw(int cidx) +static bool rvpmu_ctr_is_fw(int cidx) { union sbi_pmu_ctr_info *info; =20 @@ -373,12 +375,12 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *nu= m_hw_ctr) } EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); =20 -static uint8_t pmu_sbi_csr_index(struct perf_event *event) +static uint8_t rvpmu_csr_index(struct perf_event *event) { return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } =20 -static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) +static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags =3D 0; bool guest_events =3D false; @@ -399,7 +401,7 @@ static unsigned long pmu_sbi_get_filter_flags(struct pe= rf_event *event) return cflags; } =20 -static int pmu_sbi_ctr_get_idx(struct perf_event *event) +static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); @@ -409,7 +411,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) uint64_t cbase =3D 0, cmask =3D rvpmu->cmask; unsigned long cflags =3D 0; =20 - cflags =3D pmu_sbi_get_filter_flags(event); + cflags =3D rvpmu_sbi_get_filter_flags(event); =20 /* * In legacy mode, we have to force the fixed counters for those events @@ -446,7 +448,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; =20 /* Additional sanity check for the counter id */ - if (pmu_sbi_ctr_is_fw(idx)) { + if (rvpmu_ctr_is_fw(idx)) { if (!test_and_set_bit(idx, cpuc->used_fw_ctrs)) return idx; } else { @@ -457,7 +459,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; } =20 -static void pmu_sbi_ctr_clear_idx(struct perf_event *event) +static void rvpmu_ctr_clear_idx(struct perf_event *event) { =20 struct hw_perf_event *hwc =3D &event->hw; @@ -465,13 +467,13 @@ static void pmu_sbi_ctr_clear_idx(struct perf_event *= event) struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); int idx =3D hwc->idx; =20 - if (pmu_sbi_ctr_is_fw(idx)) + if (rvpmu_ctr_is_fw(idx)) clear_bit(idx, cpuc->used_fw_ctrs); else clear_bit(idx, cpuc->used_hw_ctrs); } =20 -static int pmu_event_find_cache(u64 config) +static int sbi_pmu_event_find_cache(u64 config) { unsigned int cache_type, cache_op, cache_result, ret; =20 @@ -487,7 +489,7 @@ static int pmu_event_find_cache(u64 config) if (cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) return -EINVAL; =20 - ret =3D pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx; + ret =3D pmu_cache_event_sbi_map[cache_type][cache_op][cache_result].event= _idx; =20 return ret; } @@ -503,7 +505,7 @@ static bool pmu_sbi_is_fw_event(struct perf_event *even= t) return false; } =20 -static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) +static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; @@ -520,10 +522,10 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) case PERF_TYPE_HARDWARE: if (config >=3D PERF_COUNT_HW_MAX) return -EINVAL; - ret =3D pmu_hw_event_map[event->attr.config].event_idx; + ret =3D pmu_hw_event_sbi_map[event->attr.config].event_idx; break; case PERF_TYPE_HW_CACHE: - ret =3D pmu_event_find_cache(config); + ret =3D sbi_pmu_event_find_cache(config); break; case PERF_TYPE_RAW: /* @@ -646,7 +648,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu= , int cpu) return 0; } =20 -static u64 pmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; @@ -688,25 +690,25 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) return val; } =20 -static void pmu_sbi_set_scounteren(void *arg) +static void rvpmu_set_scounteren(void *arg) { struct perf_event *event =3D (struct perf_event *)arg; =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) | BIT(rvpmu_csr_index(event))); } =20 -static void pmu_sbi_reset_scounteren(void *arg) +static void rvpmu_reset_scounteren(void *arg) { struct perf_event *event =3D (struct perf_event *)arg; =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) & ~BIT(rvpmu_csr_index(event))); } =20 -static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) +static void rvpmu_sbi_ctr_start(struct perf_event *event, u64 ival) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; @@ -726,10 +728,10 @@ static void pmu_sbi_ctr_start(struct perf_event *even= t, u64 ival) =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_set_scounteren((void *)event); + rvpmu_set_scounteren((void *)event); } =20 -static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) +static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long fla= g) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; @@ -739,7 +741,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, = unsigned long flag) =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_reset_scounteren((void *)event); + rvpmu_reset_scounteren((void *)event); =20 if (sbi_pmu_snapshot_available()) flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; @@ -765,7 +767,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, = unsigned long flag) } } =20 -static int pmu_sbi_find_num_ctrs(void) +static int rvpmu_sbi_find_num_ctrs(void) { struct sbiret ret; =20 @@ -776,7 +778,7 @@ static int pmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) { struct sbiret ret; int i, num_hw_ctr =3D 0, num_fw_ctr =3D 0; @@ -807,7 +809,7 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long = *mask) return 0; } =20 -static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_all(struct riscv_pmu *pmu) { /* * No need to check the error because we are disabling all the counters @@ -817,7 +819,7 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *p= mu) 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); } =20 -static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; @@ -861,8 +863,8 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pm= u *pmu) * while the overflowed counters need to be started with updated initializ= ation * value. */ -static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw= _evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, + u64 ctr_ovf_mask) { int idx =3D 0, i; struct perf_event *event; @@ -900,8 +902,8 @@ static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cp= u_hw_events *cpu_hw_evt, } } =20 -static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *c= pu_hw_evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, + u64 ctr_ovf_mask) { int i, idx =3D 0; struct perf_event *event; @@ -935,18 +937,18 @@ static inline void pmu_sbi_start_ovf_ctrs_snapshot(st= ruct cpu_hw_events *cpu_hw_ } } =20 -static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + u64 ctr_ovf_mask) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); =20 if (sbi_pmu_snapshot_available()) - pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); else - pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); } =20 -static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) +static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) { struct perf_sample_data data; struct pt_regs *regs; @@ -978,7 +980,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *d= ev) } =20 pmu =3D to_riscv_pmu(event->pmu); - pmu_sbi_stop_hw_ctrs(pmu); + rvpmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ if (sbi_pmu_snapshot_available()) @@ -1047,13 +1049,55 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, voi= d *dev) hw_evt->state =3D 0; } =20 - pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); =20 return IRQ_HANDLED; } =20 -static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) +static void rvpmu_ctr_start(struct perf_event *event, u64 ival) +{ + rvpmu_sbi_ctr_start(event, ival); + /* TODO: Counter delegation implementation */ +} + +static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) +{ + rvpmu_sbi_ctr_stop(event, flag); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_find_num_ctrs(void) +{ + return rvpmu_sbi_find_num_ctrs(); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) +{ + return rvpmu_sbi_get_ctrinfo(nctr, mask); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_event_map(struct perf_event *event, u64 *econfig) +{ + return rvpmu_sbi_event_map(event, econfig); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_ctr_get_idx(struct perf_event *event) +{ + return rvpmu_sbi_ctr_get_idx(event); + /* TODO: Counter delegation implementation */ +} + +static u64 rvpmu_ctr_read(struct perf_event *event) +{ + return rvpmu_sbi_ctr_read(event); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); @@ -1068,7 +1112,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, str= uct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); =20 /* Stop all the counters so that they can be enabled from perf */ - pmu_sbi_stop_all(pmu); + rvpmu_sbi_stop_all(pmu); =20 if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; @@ -1082,7 +1126,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, str= uct hlist_node *node) return 0; } =20 -static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) +static int rvpmu_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); @@ -1097,7 +1141,7 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct= hlist_node *node) return 0; } =20 -static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_devic= e *pdev) +static int rvpmu_setup_irqs(struct riscv_pmu *pmu, struct platform_device = *pdev) { int ret; struct cpu_hw_events __percpu *hw_events =3D pmu->hw_events; @@ -1137,7 +1181,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, = struct platform_device *pde return -ENODEV; } =20 - ret =3D request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu= ", hw_events); + ret =3D request_percpu_irq(riscv_pmu_irq, rvpmu_ovf_handler, "riscv-pmu",= hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); return ret; @@ -1213,7 +1257,7 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } =20 -static void pmu_sbi_event_init(struct perf_event *event) +static void rvpmu_event_init(struct perf_event *event) { /* * The permissions are set at event_init so that we do not depend @@ -1227,7 +1271,7 @@ static void pmu_sbi_event_init(struct perf_event *eve= nt) event->hw.flags |=3D PERF_EVENT_FLAG_LEGACY; } =20 -static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struc= t *mm) +static void rvpmu_event_mapped(struct perf_event *event, struct mm_struct = *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1255,14 +1299,14 @@ static void pmu_sbi_event_mapped(struct perf_event = *event, struct mm_struct *mm) * that it is possible to do so to avoid any race. * And we must notify all cpus here because threads that currently run * on other cpus will try to directly access the counter too without - * calling pmu_sbi_ctr_start. + * calling rvpmu_sbi_ctr_start. */ if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_set_scounteren, (void *)event, 1); + rvpmu_set_scounteren, (void *)event, 1); } =20 -static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_str= uct *mm) +static void rvpmu_event_unmapped(struct perf_event *event, struct mm_struc= t *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1284,7 +1328,7 @@ static void pmu_sbi_event_unmapped(struct perf_event = *event, struct mm_struct *m =20 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_reset_scounteren, (void *)event, 1); + rvpmu_reset_scounteren, (void *)event, 1); } =20 static void riscv_pmu_update_counter_access(void *info) @@ -1327,7 +1371,7 @@ static struct ctl_table sbi_pmu_sysctl_table[] =3D { }, }; =20 -static int pmu_sbi_device_probe(struct platform_device *pdev) +static int rvpmu_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu =3D NULL; int ret =3D -ENODEV; @@ -1338,7 +1382,7 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) if (!pmu) return -ENOMEM; =20 - num_counters =3D pmu_sbi_find_num_ctrs(); + num_counters =3D rvpmu_find_num_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1351,10 +1395,10 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) } =20 /* cache all the information about counters now */ - if (pmu_sbi_get_ctrinfo(num_counters, &cmask)) + if (rvpmu_get_ctrinfo(num_counters, &cmask)) goto out_free; =20 - ret =3D pmu_sbi_setup_irqs(pmu, pdev); + ret =3D rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { pr_info("Perf sampling/filtering is not supported as sscof extension is = not available\n"); pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; @@ -1364,17 +1408,17 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; pmu->pmu.parent =3D &pdev->dev; pmu->cmask =3D cmask; - pmu->ctr_start =3D pmu_sbi_ctr_start; - pmu->ctr_stop =3D pmu_sbi_ctr_stop; - pmu->event_map =3D pmu_sbi_event_map; - pmu->ctr_get_idx =3D pmu_sbi_ctr_get_idx; - pmu->ctr_get_width =3D pmu_sbi_ctr_get_width; - pmu->ctr_clear_idx =3D pmu_sbi_ctr_clear_idx; - pmu->ctr_read =3D pmu_sbi_ctr_read; - pmu->event_init =3D pmu_sbi_event_init; - pmu->event_mapped =3D pmu_sbi_event_mapped; - pmu->event_unmapped =3D pmu_sbi_event_unmapped; - pmu->csr_index =3D pmu_sbi_csr_index; + pmu->ctr_start =3D rvpmu_ctr_start; + pmu->ctr_stop =3D rvpmu_ctr_stop; + pmu->event_map =3D rvpmu_event_map; + pmu->ctr_get_idx =3D rvpmu_ctr_get_idx; + pmu->ctr_get_width =3D rvpmu_ctr_get_width; + pmu->ctr_clear_idx =3D rvpmu_ctr_clear_idx; + pmu->ctr_read =3D rvpmu_ctr_read; + pmu->event_init =3D rvpmu_event_init; + pmu->event_mapped =3D rvpmu_event_mapped; + pmu->event_unmapped =3D rvpmu_event_unmapped; + pmu->csr_index =3D rvpmu_csr_index; =20 ret =3D riscv_pm_pmu_register(pmu); if (ret) @@ -1430,14 +1474,14 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) return ret; } =20 -static struct platform_driver pmu_sbi_driver =3D { - .probe =3D pmu_sbi_device_probe, +static struct platform_driver rvpmu_driver =3D { + .probe =3D rvpmu_device_probe, .driver =3D { - .name =3D RISCV_PMU_SBI_PDEV_NAME, + .name =3D RISCV_PMU_PDEV_NAME, }, }; =20 -static int __init pmu_sbi_devinit(void) +static int __init rvpmu_devinit(void) { int ret; struct platform_device *pdev; @@ -1452,20 +1496,20 @@ static int __init pmu_sbi_devinit(void) =20 ret =3D cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", - pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); + rvpmu_starting_cpu, rvpmu_dying_cpu); if (ret) { pr_err("CPU hotplug notifier could not be registered: %d\n", ret); return ret; } =20 - ret =3D platform_driver_register(&pmu_sbi_driver); + ret =3D platform_driver_register(&rvpmu_driver); if (ret) return ret; =20 - pdev =3D platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NUL= L, 0); + pdev =3D platform_device_register_simple(RISCV_PMU_PDEV_NAME, -1, NULL, 0= ); if (IS_ERR(pdev)) { - platform_driver_unregister(&pmu_sbi_driver); + platform_driver_unregister(&rvpmu_driver); return PTR_ERR(pdev); } =20 @@ -1474,4 +1518,4 @@ static int __init pmu_sbi_devinit(void) =20 return ret; } -device_initcall(pmu_sbi_devinit) +device_initcall(rvpmu_devinit) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 701974639ff2..525acd6d96d0 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -13,7 +13,7 @@ #include #include =20 -#ifdef CONFIG_RISCV_PMU +#ifdef CONFIG_RISCV_PMU_COMMON =20 /* * The RISCV_MAX_COUNTERS parameter should be specified. @@ -21,7 +21,7 @@ =20 #define RISCV_MAX_COUNTERS 64 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) -#define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" +#define RISCV_PMU_PDEV_NAME "riscv-pmu" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" =20 #define RISCV_PMU_STOP_FLAG_RESET 1 @@ -87,10 +87,10 @@ void riscv_pmu_legacy_skip_init(void); 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Mon, 27 Jan 2025 21:00:08 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:08 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:53 -0800 Subject: [PATCH v3 12/21] RISC-V: perf: Modify the counter discovery mechanism Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-12-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 If both counter delegation and SBI PMU is present, the counter delegation will be used for hardware pmu counters while the SBI PMU will be used for firmware counters. Thus, the driver has to probe the counters info via SBI PMU to distinguish the firmware counters. The hybrid scheme also requires improvements of the informational logging messages to indicate the user about underlying interface used for each use case. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 118 ++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 88 insertions(+), 30 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index b69654554288..c7adda948b5d 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -66,6 +66,10 @@ static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); +static bool cdeleg_available; +static bool sbi_available; =20 static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, @@ -88,7 +92,8 @@ static int sysctl_perf_user_access __read_mostly =3D SYSC= TL_USER_ACCESS; =20 /* * This structure is SBI specific but counter delegation also require coun= ter - * width, csr mapping. Reuse it for now. + * width, csr mapping. Reuse it for now we can have firmware counters for + * platfroms with counter delegation support. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -100,6 +105,8 @@ static unsigned int riscv_pmu_irq; =20 /* Cache the available counters in a bitmask */ static unsigned long cmask; +/* Cache the available firmware counters in another bitmask */ +static unsigned long firmware_cmask; =20 struct sbi_pmu_event_data { union { @@ -778,35 +785,49 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static int rvpmu_deleg_find_ctrs(void) +{ + /* TODO */ + return -1; +} + +static int rvpmu_sbi_get_ctrinfo(int nsbi_ctr, int ndeleg_ctr) { struct sbiret ret; - int i, num_hw_ctr =3D 0, num_fw_ctr =3D 0; + int i, num_hw_ctr =3D 0, num_fw_ctr =3D 0, num_ctr =3D 0; union sbi_pmu_ctr_info cinfo; =20 - pmu_ctr_list =3D kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL); - if (!pmu_ctr_list) - return -ENOMEM; - - for (i =3D 0; i < nctr; i++) { + for (i =3D 0; i < nsbi_ctr; i++) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0,= 0, 0); if (ret.error) /* The logical counter ids are not expected to be contiguous */ continue; =20 - *mask |=3D BIT(i); - cinfo.value =3D ret.value; if (cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) num_fw_ctr++; - else + + if (!cdeleg_available) { num_hw_ctr++; - pmu_ctr_list[i].value =3D cinfo.value; + cmask |=3D BIT(i); + pmu_ctr_list[i].value =3D cinfo.value; + } else if (cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + /* Track firmware counters in a different mask */ + firmware_cmask |=3D BIT(i); + pmu_ctr_list[i].value =3D cinfo.value; + } + } =20 - pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr); + if (cdeleg_available) { + pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, ndeleg_ctr= ); + num_ctr =3D num_fw_ctr + ndeleg_ctr; + } else { + pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr= ); + num_ctr =3D nsbi_ctr; + } =20 - return 0; + return num_ctr; } =20 static inline void rvpmu_sbi_stop_all(struct riscv_pmu *pmu) @@ -1067,16 +1088,33 @@ static void rvpmu_ctr_stop(struct perf_event *event= , unsigned long flag) /* TODO: Counter delegation implementation */ } =20 -static int rvpmu_find_num_ctrs(void) +static int rvpmu_find_ctrs(void) { - return rvpmu_sbi_find_num_ctrs(); - /* TODO: Counter delegation implementation */ -} + int num_sbi_counters =3D 0, num_deleg_counters =3D 0, num_counters =3D 0; =20 -static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) -{ - return rvpmu_sbi_get_ctrinfo(nctr, mask); - /* TODO: Counter delegation implementation */ + /* + * We don't know how many firmware counters available. Just allocate + * for maximum counters driver can support. The default is 64 anyways. + */ + pmu_ctr_list =3D kcalloc(RISCV_MAX_COUNTERS, sizeof(*pmu_ctr_list), + GFP_KERNEL); + if (!pmu_ctr_list) + return -ENOMEM; + + if (cdeleg_available) + num_deleg_counters =3D rvpmu_deleg_find_ctrs(); + + /* This is required for firmware counters even if the above is true */ + if (sbi_available) + num_sbi_counters =3D rvpmu_sbi_find_num_ctrs(); + + if (num_sbi_counters >=3D RISCV_MAX_COUNTERS || num_deleg_counters >=3D R= ISCV_MAX_COUNTERS) + return -ENOSPC; + + /* cache all the information about counters now */ + num_counters =3D rvpmu_sbi_get_ctrinfo(num_sbi_counters, num_deleg_counte= rs); + + return num_counters; } =20 static int rvpmu_event_map(struct perf_event *event, u64 *econfig) @@ -1377,12 +1415,21 @@ static int rvpmu_device_probe(struct platform_devic= e *pdev) int ret =3D -ENODEV; int num_counters; =20 - pr_info("SBI PMU extension is available\n"); + if (cdeleg_available) { + pr_info("hpmcounters will use the counter delegation ISA extension\n"); + if (sbi_available) + pr_info("Firmware counters will be use SBI PMU extension\n"); + else + pr_info("Firmware counters will be not available as SBI PMU extension i= s not present\n"); + } else if (sbi_available) { + pr_info("Both hpmcounters and firmware counters will use SBI PMU extensi= on\n"); + } + pmu =3D riscv_pmu_alloc(); if (!pmu) return -ENOMEM; =20 - num_counters =3D rvpmu_find_num_ctrs(); + num_counters =3D rvpmu_find_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1394,9 +1441,6 @@ static int rvpmu_device_probe(struct platform_device = *pdev) pr_info("SBI returned more than maximum number of counters. Limiting the= number of counters to %d\n", num_counters); } =20 - /* cache all the information about counters now */ - if (rvpmu_get_ctrinfo(num_counters, &cmask)) - goto out_free; =20 ret =3D rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { @@ -1486,13 +1530,27 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; =20 - if (sbi_spec_version < sbi_mk_version(0, 3) || - !sbi_probe_extension(SBI_EXT_PMU)) { - return 0; + if (sbi_spec_version >=3D sbi_mk_version(0, 3) && + sbi_probe_extension(SBI_EXT_PMU)) { + static_branch_enable(&riscv_pmu_sbi_available); + sbi_available =3D true; } =20 if (sbi_spec_version >=3D sbi_mk_version(2, 0)) sbi_v2_available =3D true; + /* + * We need all three extensions to be present to access the counters + * in S-mode via Supervisor Counter delegation. + */ + if (riscv_isa_extension_available(NULL, SSCCFG) && + riscv_isa_extension_available(NULL, SMCDELEG) && + riscv_isa_extension_available(NULL, SSCSRIND)) { + static_branch_enable(&riscv_pmu_cdeleg_available); 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Mon, 27 Jan 2025 21:00:10 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:10 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:54 -0800 Subject: [PATCH v3 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-13-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 51 ++++++++++++++++++++++++++++++++++++++= ++++ include/linux/perf/riscv_pmu.h | 13 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index c7adda948b5d..7742eb6d1ed2 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -307,6 +307,56 @@ static struct sbi_pmu_event_data pmu_cache_event_sbi_m= ap[PERF_COUNT_HW_CACHE_MAX }, }; =20 +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MA= X] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , _cache_event_map) \ + { .vendorid =3D _vendorid, .archid =3D _archid, .implid =3D _implid, \ + .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map = }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { +}; + +const struct riscv_pmu_event *current_pmu_hw_event_map; +const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_COUNT_HW_= CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void rvpmu_vendor_register_events(void) +{ + int cpu =3D raw_smp_processor_id(); + unsigned long vendor_id =3D riscv_cached_mvendorid(cpu); + unsigned long impl_id =3D riscv_cached_mimpid(cpu); + unsigned long arch_id =3D riscv_cached_marchid(cpu); + + for (int i =3D 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid =3D=3D vendor_id && + pmu_vendor_events_table[i].implid =3D=3D impl_id && + pmu_vendor_events_table[i].archid =3D=3D arch_id) { + current_pmu_hw_event_map =3D pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map =3D pmu_vendor_events_table[i].cache_event_= map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1547,6 +1597,7 @@ static int __init rvpmu_devinit(void) riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); cdeleg_available =3D true; + rvpmu_vendor_register_events(); } =20 if (!(sbi_available || cdeleg_available)) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 525acd6d96d0..a3e1fdd5084a 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -28,6 +28,19 @@ =20 #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 +#define HW_OP_UNSUPPORTED 0xFFFF +#define CACHE_OP_UNSUPPORTED 0xFFFF + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... 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Mon, 27 Jan 2025 21:00:11 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:11 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:55 -0800 Subject: [PATCH v3 14/21] RISC-V: perf: Implement supervisor counter delegation support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-14-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 There are few new RISC-V ISA exensions (ssccfg, sscsrind, smcntrpmf) which allows the hpmcounter/hpmevents to be programmed directly from S-mode. The implementation detects the ISA extension at runtime and uses them if available instead of SBI PMU extension. SBI PMU extension will still be used for firmware counters if the user requests it. The current linux driver relies on event encoding defined by SBI PMU specification for standard perf events. However, there are no standard event encoding available in the ISA. In the future, we may want to decouple the counter delegation and SBI PMU completely. In that case, counter delegation supported platforms must rely on the event encoding defined in the perf json file or in the pmu driver. For firmware events, it will continue to use the SBI PMU encoding as one can not support firmware event without SBI PMU. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 2 +- drivers/perf/riscv_pmu_dev.c | 568 +++++++++++++++++++++++++++++++++----= ---- include/linux/perf/riscv_pmu.h | 3 + 5 files changed, 472 insertions(+), 104 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 42b7f4f7ec0f..a06d5fec6e6d 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -249,6 +249,7 @@ #endif =20 #define SISELECT_SSCCFG_BASE 0x40 +#define HPMEVENT_MASK GENMASK_ULL(63, 56) =20 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6c82318065cf..1107795cc3cf 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -158,7 +158,7 @@ struct riscv_pmu_snapshot_data { u64 reserved[447]; }; =20 -#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) +#define RISCV_PMU_SBI_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 #define RISCV_PLAT_FW_EVENT 0xFFFF =20 diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2707a51b082c..0f4ecb6010d6 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -126,7 +126,7 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long = eidx, uint64_t evt_data) config =3D kvm_pmu_get_perf_event_cache_config(ecode); break; case SBI_PMU_EVENT_TYPE_RAW: - config =3D evt_data & RISCV_PMU_RAW_EVENT_MASK; + config =3D evt_data & RISCV_PMU_SBI_RAW_EVENT_MASK; break; case SBI_PMU_EVENT_TYPE_FW: if (ecode < SBI_PMU_FW_MAX) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 7742eb6d1ed2..e075d0d15221 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ @@ -59,31 +61,67 @@ asm volatile(ALTERNATIVE( \ #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) =20 -PMU_FORMAT_ATTR(event, "config:0-47"); +#define RVPMU_SBI_PMU_FORMAT_ATTR "config:0-47" +#define RVPMU_CDELEG_PMU_FORMAT_ATTR "config:0-55" + +static ssize_t __maybe_unused rvpmu_format_show(struct device *dev, struct= device_attribute *attr, + char *buf); + +#define RVPMU_ATTR_ENTRY(_name, _func, _config) ( \ + &((struct dev_ext_attribute[]) { \ + { __ATTR(_name, 0444, _func, NULL), (void *)_config } \ + })[0].attr.attr) + +#define RVPMU_FORMAT_ATTR_ENTRY(_name, _config) \ + RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) + PMU_FORMAT_ATTR(firmware, "config:62-63"); =20 static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +#define riscv_pmu_sbi_available() \ + static_branch_likely(&riscv_pmu_sbi_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); +#define riscv_pmu_cdeleg_available() \ + static_branch_unlikely(&riscv_pmu_cdeleg_available) + static bool cdeleg_available; static bool sbi_available; =20 -static struct attribute *riscv_arch_formats_attr[] =3D { - &format_attr_event.attr, +static struct attribute *riscv_sbi_pmu_formats_attr[] =3D { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_SBI_PMU_FORMAT_ATTR), + &format_attr_firmware.attr, + NULL, +}; + +static struct attribute_group riscv_sbi_pmu_format_group =3D { + .name =3D "format", + .attrs =3D riscv_sbi_pmu_formats_attr, +}; + +static const struct attribute_group *riscv_sbi_pmu_attr_groups[] =3D { + &riscv_sbi_pmu_format_group, + NULL, +}; + +static struct attribute *riscv_cdeleg_pmu_formats_attr[] =3D { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, NULL, }; =20 -static struct attribute_group riscv_pmu_format_group =3D { +static struct attribute_group riscv_cdeleg_pmu_format_group =3D { .name =3D "format", - .attrs =3D riscv_arch_formats_attr, + .attrs =3D riscv_cdeleg_pmu_formats_attr, }; =20 -static const struct attribute_group *riscv_pmu_attr_groups[] =3D { - &riscv_pmu_format_group, +static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] =3D { + &riscv_cdeleg_pmu_format_group, NULL, }; =20 @@ -385,6 +423,14 @@ static void rvpmu_sbi_check_std_events(struct work_str= uct *work) =20 static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); =20 +static ssize_t rvpmu_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr =3D container_of(attr, + struct dev_ext_attribute, attr); + return sysfs_emit(buf, "%s\n", (char *)eattr->var); +} + static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; @@ -437,6 +483,38 @@ static uint8_t rvpmu_csr_index(struct perf_event *even= t) return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } =20 +static uint64_t get_deleg_priv_filter_bits(struct perf_event *event) +{ + u64 priv_filter_bits =3D 0; + bool guest_events =3D false; + + if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS) + guest_events =3D true; + if (event->attr.exclude_kernel) + priv_filter_bits |=3D guest_events ? HPMEVENT_VSINH : HPMEVENT_SINH; + if (event->attr.exclude_user) + priv_filter_bits |=3D guest_events ? HPMEVENT_VUINH : HPMEVENT_UINH; + if (guest_events && event->attr.exclude_hv) + priv_filter_bits |=3D HPMEVENT_SINH; + if (event->attr.exclude_host) + priv_filter_bits |=3D HPMEVENT_UINH | HPMEVENT_SINH; + if (event->attr.exclude_guest) + priv_filter_bits |=3D HPMEVENT_VSINH | HPMEVENT_VUINH; + + return priv_filter_bits; +} + +static bool pmu_sbi_is_fw_event(struct perf_event *event) +{ + u32 type =3D event->attr.type; + u64 config =3D event->attr.config; + + if (type =3D=3D PERF_TYPE_RAW && ((config >> 63) =3D=3D 1)) + return true; + else + return false; +} + static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags =3D 0; @@ -465,7 +543,8 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); struct sbiret ret; int idx; - uint64_t cbase =3D 0, cmask =3D rvpmu->cmask; + u64 cbase =3D 0; + unsigned long ctr_mask =3D rvpmu->cmask; unsigned long cflags =3D 0; =20 cflags =3D rvpmu_sbi_get_filter_flags(event); @@ -478,21 +557,24 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *e= vent) if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type =3D=3D PER= F_TYPE_HARDWARE)) { if (event->attr.config =3D=3D PERF_COUNT_HW_CPU_CYCLES) { cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask =3D 1; + ctr_mask =3D 1; } else if (event->attr.config =3D=3D PERF_COUNT_HW_INSTRUCTIONS) { cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask =3D BIT(CSR_INSTRET - CSR_CYCLE); + ctr_mask =3D BIT(CSR_INSTRET - CSR_CYCLE); } } =20 + if (pmu_sbi_is_fw_event(event) && cdeleg_available) + ctr_mask =3D firmware_cmask; + /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, + ctr_mask, cflags, hwc->event_base, hwc->config, hwc->config >> 32); #else ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, 0); + ctr_mask, cflags, hwc->event_base, hwc->config, 0); #endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", @@ -501,7 +583,7 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) } =20 idx =3D ret.value; - if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value) + if (!test_bit(idx, &ctr_mask) || !pmu_ctr_list[idx].value) return -ENOENT; =20 /* Additional sanity check for the counter id */ @@ -551,17 +633,6 @@ static int sbi_pmu_event_find_cache(u64 config) return ret; } =20 -static bool pmu_sbi_is_fw_event(struct perf_event *event) -{ - u32 type =3D event->attr.type; - u64 config =3D event->attr.config; - - if ((type =3D=3D PERF_TYPE_RAW) && ((config >> 63) =3D=3D 1)) - return true; - else - return false; -} - static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type =3D event->attr.type; @@ -593,7 +664,7 @@ static int rvpmu_sbi_event_map(struct perf_event *event= , u64 *econfig) * 10 - SBI firmware events * 11 - Risc-V platform specific firmware event */ - raw_config_val =3D config & RISCV_PMU_RAW_EVENT_MASK; + raw_config_val =3D config & RISCV_PMU_SBI_RAW_EVENT_MASK; switch (config >> 62) { case 0: ret =3D RISCV_PMU_RAW_EVENT_IDX; @@ -622,6 +693,84 @@ static int rvpmu_sbi_event_map(struct perf_event *even= t, u64 *econfig) return ret; } =20 +static int cdeleg_pmu_event_find_cache(u64 config, u64 *eventid, uint32_t = *counter_mask) +{ + unsigned int cache_type, cache_op, cache_result; + + if (!current_pmu_cache_event_map) + return -ENOENT; + + cache_type =3D (config >> 0) & 0xff; + if (cache_type >=3D PERF_COUNT_HW_CACHE_MAX) + return -EINVAL; + + cache_op =3D (config >> 8) & 0xff; + if (cache_op >=3D PERF_COUNT_HW_CACHE_OP_MAX) + return -EINVAL; + + cache_result =3D (config >> 16) & 0xff; + if (cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) + return -EINVAL; + + if (eventid) + *eventid =3D current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].event_id; + if (counter_mask) + *counter_mask =3D current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].counter_mask; + + return 0; +} + +static int rvpmu_cdeleg_event_map(struct perf_event *event, u64 *econfig) +{ + u32 type =3D event->attr.type; + u64 config =3D event->attr.config; + int ret =3D 0; + + /* + * There are two ways standard perf events can be mapped to platform spec= ific + * encoding. + * 1. The vendor may specify the encodings in the driver. + * 2. The Perf tool for RISC-V may remap the standard perf event to platf= orm + * specific encoding. + * + * As RISC-V ISA doesn't define any standard event encoding. Thus, perf t= ool allows + * vendor to define it via json file. The encoding defined in the json wi= ll override + * the perf legacy encoding. However, some user may want to run performan= ce + * monitoring without perf tool as well. That's why, vendors may specify = the event + * encoding in the driver as well if they want to support that use case t= oo. + * If an encoding is defined in the json, it will be encoded as a raw eve= nt. + */ + + switch (type) { + case PERF_TYPE_HARDWARE: + if (config >=3D PERF_COUNT_HW_MAX) + return -EINVAL; + if (!current_pmu_hw_event_map) + return -ENOENT; + + *econfig =3D current_pmu_hw_event_map[config].event_id; + if (*econfig =3D=3D HW_OP_UNSUPPORTED) + ret =3D -ENOENT; + break; + case PERF_TYPE_HW_CACHE: + ret =3D cdeleg_pmu_event_find_cache(config, econfig, NULL); + if (*econfig =3D=3D HW_OP_UNSUPPORTED) + ret =3D -ENOENT; + break; + case PERF_TYPE_RAW: + *econfig =3D config & RISCV_PMU_DELEG_RAW_EVENT_MASK; + break; + default: + ret =3D -ENOENT; + break; + } + + /* event_base is not used for counter delegation */ + return ret; +} + static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) { int cpu; @@ -705,7 +854,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu= , int cpu) return 0; } =20 -static u64 rvpmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; @@ -782,10 +931,6 @@ static void rvpmu_sbi_ctr_start(struct perf_event *eve= nt, u64 ival) if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); - - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_set_scounteren((void *)event); } =20 static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long fla= g) @@ -796,10 +941,6 @@ static void rvpmu_sbi_ctr_stop(struct perf_event *even= t, unsigned long flag) struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_reset_scounteren((void *)event); - if (sbi_pmu_snapshot_available()) flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 @@ -835,12 +976,6 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static int rvpmu_deleg_find_ctrs(void) -{ - /* TODO */ - return -1; -} - static int rvpmu_sbi_get_ctrinfo(int nsbi_ctr, int ndeleg_ctr) { struct sbiret ret; @@ -928,53 +1063,75 @@ static inline void rvpmu_sbi_stop_hw_ctrs(struct ris= cv_pmu *pmu) } } =20 -/* - * This function starts all the used counters in two step approach. - * Any counter that did not overflow can be start in a single step - * while the overflowed counters need to be started with updated initializ= ation - * value. - */ -static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_deleg_ctr_start_mask(unsigned long mask) { - int idx =3D 0, i; - struct perf_event *event; - unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; - unsigned long ctr_start_mask =3D 0; - uint64_t max_period; - struct hw_perf_event *hwc; - u64 init_val =3D 0; + unsigned long scountinhibit_val =3D 0; =20 - for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { - ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; - /* Start all the counters that did not overflow in a single shot */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr= _start_mask, - 0, 0, 0, 0); - } + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &=3D ~mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_deleg_ctr_enable_irq(struct perf_event *event) +{ + unsigned long hpmevent_curr; + unsigned long of_mask; + struct hw_perf_event *hwc =3D &event->hw; + int counter_idx =3D hwc->idx; + unsigned long sip_val =3D csr_read(CSR_SIP); + + if (!is_sampling_event(event) || (sip_val & SIP_LCOFIP)) + return; =20 - /* Reinitialize and start all the counter that overflowed */ - while (ctr_ovf_mask) { - if (ctr_ovf_mask & 0x01) { - event =3D cpu_hw_evt->events[idx]; - hwc =3D &event->hw; - max_period =3D riscv_pmu_ctr_get_width_mask(event); - init_val =3D local64_read(&hwc->prev_count) & max_period; #if defined(CONFIG_32BIT) - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, init_val >> 32, 0); + hpmevent_curr =3D csr_ind_read(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_= idx); + of_mask =3D (u32)~HPMEVENTH_OF; #else - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, 0, 0); + hpmevent_curr =3D csr_ind_read(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_= idx); + of_mask =3D ~HPMEVENT_OF; #endif - perf_event_update_userpage(event); - } - ctr_ovf_mask =3D ctr_ovf_mask >> 1; - idx++; - } + + hpmevent_curr &=3D of_mask; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG4, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_cur= r); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_cur= r); +#endif +} + +static void rvpmu_deleg_ctr_start(struct perf_event *event, u64 ival) +{ + unsigned long scountinhibit_val =3D 0; + struct hw_perf_event *hwc =3D &event->hw; + +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival & 0xFFFFFFF= F); + csr_ind_write(CSR_SIREG4, SISELECT_SSCCFG_BASE, hwc->idx, ival >> BITS_PE= R_LONG); +#else + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival); +#endif + + rvpmu_deleg_ctr_enable_irq(event); + + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &=3D ~(1 << hwc->idx); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); } =20 -static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_deleg_ctr_stop_mask(unsigned long mask) +{ + unsigned long scountinhibit_val =3D 0; + + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val |=3D mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw= _evt, + u64 ctr_ovf_mask) { int i, idx =3D 0; struct perf_event *event; @@ -1008,15 +1165,53 @@ static inline void rvpmu_sbi_start_ovf_ctrs_snapsho= t(struct cpu_hw_events *cpu_h } } =20 -static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +/* + * This function starts all the used counters in two step approach. + * Any counter that did not overflow can be start in a single step + * while the overflowed counters need to be started with updated initializ= ation + * value. + */ +static void rvpmu_start_overflow_mask(struct riscv_pmu *pmu, u64 ctr_ovf_m= ask) { + int idx =3D 0, i; + struct perf_event *event; + unsigned long ctr_start_mask =3D 0; + u64 max_period, init_val =3D 0; + struct hw_perf_event *hwc; struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); =20 if (sbi_pmu_snapshot_available()) - rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); - else - rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + return rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + + /* Start all the counters that did not overflow */ + if (riscv_pmu_cdeleg_available()) { + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + rvpmu_deleg_ctr_start_mask(ctr_start_mask); + } else { + for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + /* Start all the counters that did not overflow in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, + ctr_start_mask, 0, 0, 0, 0); + } + } + + /* Reinitialize and start all the counter that overflowed */ + while (ctr_ovf_mask) { + if (ctr_ovf_mask & 0x01) { + event =3D cpu_hw_evt->events[idx]; + hwc =3D &event->hw; + max_period =3D riscv_pmu_ctr_get_width_mask(event); + init_val =3D local64_read(&hwc->prev_count) & max_period; + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_start(event, init_val); + else + rvpmu_sbi_ctr_start(event, init_val); + perf_event_update_userpage(event); + } + ctr_ovf_mask =3D ctr_ovf_mask >> 1; + idx++; + } } =20 static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) @@ -1051,7 +1246,10 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void *= dev) } =20 pmu =3D to_riscv_pmu(event->pmu); - rvpmu_sbi_stop_hw_ctrs(pmu); + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_stop_mask(cpu_hw_evt->used_hw_ctrs[0]); + else + rvpmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ if (sbi_pmu_snapshot_available()) @@ -1120,22 +1318,174 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void= *dev) hw_evt->state =3D 0; } =20 - rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); =20 return IRQ_HANDLED; } =20 +static int get_deleg_hw_ctr_width(int counter_offset) +{ + unsigned long hpm_warl; + int num_bits; + + if (counter_offset < 3 || counter_offset > 31) + return 0; + + hpm_warl =3D csr_ind_warl(CSR_SIREG, SISELECT_SSCCFG_BASE, counter_offset= , -1); + num_bits =3D __fls(hpm_warl); + +#if defined(CONFIG_32BIT) + hpm_warl =3D csr_ind_warl(CSR_SIREG4, SISELECT_SSCCFG_BASE, counter_offse= t, -1); + num_bits +=3D __fls(hpm_warl); +#endif + return num_bits; +} + +static int rvpmu_deleg_find_ctrs(void) +{ + int i, num_hw_ctr =3D 0; + union sbi_pmu_ctr_info cinfo; + unsigned long scountinhibit_old =3D 0; + + /* Do a WARL write/read to detect which hpmcounters have been delegated */ + scountinhibit_old =3D csr_read(CSR_SCOUNTINHIBIT); + csr_write(CSR_SCOUNTINHIBIT, -1); + cmask =3D csr_read(CSR_SCOUNTINHIBIT); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_old); + + for_each_set_bit(i, &cmask, RISCV_MAX_HW_COUNTERS) { + if (unlikely(i =3D=3D 1)) + continue; /* This should never happen as TM is read only */ + cinfo.value =3D 0; + cinfo.type =3D SBI_PMU_CTR_TYPE_HW; + /* + * If counter delegation is enabled, the csr stored to the cinfo will + * be a virtual counter that the delegation attempts to read. + */ + cinfo.csr =3D CSR_CYCLE + i; + if (i =3D=3D 0 || i =3D=3D 2) + cinfo.width =3D 63; + else + cinfo.width =3D get_deleg_hw_ctr_width(i); + + num_hw_ctr++; + pmu_ctr_list[i].value =3D cinfo.value; + } + + return num_hw_ctr; +} + +static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_= event *event) +{ + return -EINVAL; +} + +static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct pe= rf_event *event) +{ + unsigned long hw_ctr_mask =3D 0; + + /* + * TODO: Treat every hpmcounter can monitor every event for now. + * The event to counter mapping should come from the json file. + * The mapping should also tell if sampling is supported or not. + */ + + /* Select only hpmcounters */ + hw_ctr_mask =3D cmask & (~0x7); + hw_ctr_mask &=3D ~(cpuc->used_hw_ctrs[0]); + return __ffs(hw_ctr_mask); +} + +static void update_deleg_hpmevent(int counter_idx, uint64_t event_value, u= int64_t filter_bits) +{ + u64 hpmevent_value =3D 0; + + /* OF bit should be enable during the start if sampling is requested */ + hpmevent_value =3D (event_value & ~HPMEVENT_MASK) | filter_bits | HPMEVEN= T_OF; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_val= ue & 0xFFFFFFFF); + if (riscv_isa_extension_available(NULL, SSCOFPMF)) + csr_ind_write(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_idx, + hpmevent_value >> BITS_PER_LONG); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_val= ue); +#endif +} + +static int rvpmu_deleg_ctr_get_idx(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); + unsigned long hw_ctr_max_id; + u64 priv_filter; + int idx; + + /* + * TODO: We should not rely on SBI Perf encoding to check if the event + * is a fixed one or not. + */ + if (!is_sampling_event(event)) { + idx =3D get_deleg_fixed_hw_idx(cpuc, event); + if (idx =3D=3D 0 || idx =3D=3D 2) { + /* Priv mode filter bits are only available if smcntrpmf is present */ + if (riscv_isa_extension_available(NULL, SMCNTRPMF)) + goto found_idx; + else + goto skip_update; + } + } + + hw_ctr_max_id =3D __fls(cmask); + idx =3D get_deleg_next_hpm_hw_idx(cpuc, event); + if (idx < 3 || idx > hw_ctr_max_id) + goto out_err; +found_idx: + priv_filter =3D get_deleg_priv_filter_bits(event); + update_deleg_hpmevent(idx, hwc->config, priv_filter); +skip_update: + if (!test_and_set_bit(idx, cpuc->used_hw_ctrs)) + return idx; +out_err: + return -ENOENT; +} + static void rvpmu_ctr_start(struct perf_event *event, u64 ival) { - rvpmu_sbi_ctr_start(event, ival); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc =3D &event->hw; + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + rvpmu_deleg_ctr_start(event, ival); + else + rvpmu_sbi_ctr_start(event, ival); + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_set_scounteren((void *)event); } =20 static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) { - rvpmu_sbi_ctr_stop(event, flag); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc =3D &event->hw; + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_reset_scounteren((void *)event); + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) { + /* + * The counter is already stopped. No need to stop again. Counter + * mapping will be reset in clear_idx function. + */ + if (flag !=3D RISCV_PMU_STOP_FLAG_RESET) + rvpmu_deleg_ctr_stop_mask((1 << hwc->idx)); + else + update_deleg_hpmevent(hwc->idx, 0, 0); + } else { + rvpmu_sbi_ctr_stop(event, flag); + } } =20 static int rvpmu_find_ctrs(void) @@ -1169,20 +1519,22 @@ static int rvpmu_find_ctrs(void) =20 static int rvpmu_event_map(struct perf_event *event, u64 *econfig) { - return rvpmu_sbi_event_map(event, econfig); - /* TODO: Counter delegation implementation */ -} + u64 config1; =20 -static int rvpmu_ctr_get_idx(struct perf_event *event) -{ - return rvpmu_sbi_ctr_get_idx(event); - /* TODO: Counter delegation implementation */ + config1 =3D event->attr.config1; + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_cdeleg_event_map(event, econfig); + } else { + return rvpmu_sbi_event_map(event, econfig); + } } =20 -static u64 rvpmu_ctr_read(struct perf_event *event) +static int rvpmu_ctr_get_idx(struct perf_event *event) { - return rvpmu_sbi_ctr_read(event); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_deleg_ctr_get_idx(event); + else + return rvpmu_sbi_ctr_get_idx(event); } =20 static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) @@ -1200,7 +1552,16 @@ static int rvpmu_starting_cpu(unsigned int cpu, stru= ct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); =20 /* Stop all the counters so that they can be enabled from perf */ - rvpmu_sbi_stop_all(pmu); + if (riscv_pmu_cdeleg_available()) { + rvpmu_deleg_ctr_stop_mask(cmask); + if (riscv_pmu_sbi_available()) { + /* Stop the firmware counters as well */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, firmware_cmask, + 0, 0, 0, 0); + } + } else { + rvpmu_sbi_stop_all(pmu); + } =20 if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; @@ -1499,8 +1860,11 @@ static int rvpmu_device_probe(struct platform_device= *pdev) pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_EXCLUDE; } =20 - pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; pmu->pmu.parent =3D &pdev->dev; + if (cdeleg_available) + pmu->pmu.attr_groups =3D riscv_cdeleg_pmu_attr_groups; + else + pmu->pmu.attr_groups =3D riscv_sbi_pmu_attr_groups; pmu->cmask =3D cmask; pmu->ctr_start =3D rvpmu_ctr_start; pmu->ctr_stop =3D rvpmu_ctr_stop; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index a3e1fdd5084a..9e2758c32e8b 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -20,6 +20,7 @@ */ =20 #define RISCV_MAX_COUNTERS 64 +#define RISCV_MAX_HW_COUNTERS 32 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) #define RISCV_PMU_PDEV_NAME "riscv-pmu" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" @@ -28,6 +29,8 @@ =20 #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 +#define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) + #define HW_OP_UNSUPPORTED 0xFFFF #define CACHE_OP_UNSUPPORTED 0xFFFF =20 --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F9F1F78F3 for ; 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Mon, 27 Jan 2025 21:00:13 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:13 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:56 -0800 Subject: [PATCH v3 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-15-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra , Charlie Jenkins X-Mailer: b4 0.15-dev-13183 From: Charlie Jenkins When the PMU SBI extension is not implemented, sbi_v2_available should not be set to true. The SBI implementation for counter config matching and firmware counter read should also be skipped when the SBI extension is not implemented. Signed-off-by: Atish Patra Signed-off-by: Charlie Jenkins --- drivers/perf/riscv_pmu_dev.c | 49 +++++++++++++++++++++++++---------------= ---- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index e075d0d15221..52d927576c9b 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -410,18 +410,22 @@ static void rvpmu_sbi_check_event(struct sbi_pmu_even= t_data *edata) } } =20 -static void rvpmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_check_std_events(struct work_struct *work) { - for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - rvpmu_sbi_check_event(&pmu_hw_event_map[i]); - - for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) - for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) - for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) - rvpmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); + if (riscv_pmu_sbi_available()) { + for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); + + for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + } else { + DO_ONCE_LITE_IF(1, pr_err, "Boot time config matching not required for s= mcdeleg\n"); + } } =20 -static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_check_std_events); =20 static ssize_t rvpmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -549,6 +553,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) =20 cflags =3D rvpmu_sbi_get_filter_flags(event); =20 + if (!riscv_pmu_sbi_available()) + return -ENOENT; + /* * In legacy mode, we have to force the fixed counters for those events * but not in the user access mode as we want to use the other counters @@ -562,10 +569,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *ev= ent) cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; ctr_mask =3D BIT(CSR_INSTRET - CSR_CYCLE); } - } - - if (pmu_sbi_is_fw_event(event) && cdeleg_available) + } else if (pmu_sbi_is_fw_event(event) && cdeleg_available) { ctr_mask =3D firmware_cmask; + } =20 /* retrieve the available counter index */ #if defined(CONFIG_32BIT) @@ -871,7 +877,7 @@ static u64 rvpmu_ctr_read(struct perf_event *event) return val; } =20 - if (pmu_sbi_is_fw_event(event)) { + if (pmu_sbi_is_fw_event(event) && riscv_pmu_sbi_available()) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); if (ret.error) @@ -1524,9 +1530,8 @@ static int rvpmu_event_map(struct perf_event *event, = u64 *econfig) config1 =3D event->attr.config1; if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) return rvpmu_cdeleg_event_map(event, econfig); - } else { + else return rvpmu_sbi_event_map(event, econfig); - } } =20 static int rvpmu_ctr_get_idx(struct perf_event *event) @@ -1944,14 +1949,16 @@ static int __init rvpmu_devinit(void) int ret; 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Mon, 27 Jan 2025 21:00:15 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:15 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:57 -0800 Subject: [PATCH v3 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-16-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The counter restriction specified in the json file is passed to the drivers via config2 paarameter in perf attributes. This allows any platform vendor to define their custom mapping between event and hpmcounters without any rules defined in the ISA. For legacy events, the platform vendor may define the mapping in the driver in the vendor event table. The fixed cycle and instruction counters are fixed (0 and 2 respectively) by the ISA and maps to the legacy events. The platform vendor must specify this in the driver if intended to be used while profiling. Otherwise, they can just specify the alternate hpmcounters that may monitor and/or sample the cycle/instruction counts. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 78 ++++++++++++++++++++++++++++++++++----= ---- include/linux/perf/riscv_pmu.h | 2 ++ 2 files changed, 66 insertions(+), 14 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 52d927576c9b..ab84f83df5e1 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -76,6 +76,7 @@ static ssize_t __maybe_unused rvpmu_format_show(struct de= vice *dev, struct devic RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) =20 PMU_FORMAT_ATTR(firmware, "config:62-63"); +PMU_FORMAT_ATTR(counterid_mask, "config2:0-31"); =20 static bool sbi_v2_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); @@ -112,6 +113,7 @@ static const struct attribute_group *riscv_sbi_pmu_attr= _groups[] =3D { static struct attribute *riscv_cdeleg_pmu_formats_attr[] =3D { RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, + &format_attr_counterid_mask.attr, NULL, }; =20 @@ -1383,24 +1385,76 @@ static int rvpmu_deleg_find_ctrs(void) return num_hw_ctr; } =20 +/* The json file must correctly specify counter 0 or counter 2 is available + * in the counter lists for cycle/instret events. Otherwise, the drivers h= ave + * no way to figure out if a fixed counter must be used and pick a program= mable + * counter if available. + */ static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_= event *event) { - return -EINVAL; + struct hw_perf_event *hwc =3D &event->hw; + bool guest_events =3D event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENT= S; + + if (guest_events) { + if (hwc->event_base =3D=3D SBI_PMU_HW_CPU_CYCLES) + return 0; + if (hwc->event_base =3D=3D SBI_PMU_HW_INSTRUCTIONS) + return 2; + else + return -EINVAL; + } + + if (!event->attr.config2) + return -EINVAL; + + if (event->attr.config2 & RISCV_PMU_CYCLE_FIXED_CTR_MASK) + return 0; /* CY counter */ + else if (event->attr.config2 & RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK) + return 2; /* IR counter */ + else + return -EINVAL; } =20 static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct pe= rf_event *event) { - unsigned long hw_ctr_mask =3D 0; + u32 hw_ctr_mask =3D 0, temp_mask =3D 0; + u32 type =3D event->attr.type; + u64 config =3D event->attr.config; + int ret; =20 - /* - * TODO: Treat every hpmcounter can monitor every event for now. - * The event to counter mapping should come from the json file. - * The mapping should also tell if sampling is supported or not. - */ + /* Select only available hpmcounters */ + hw_ctr_mask =3D cmask & (~0x7) & ~(cpuc->used_hw_ctrs[0]); + + switch (type) { + case PERF_TYPE_HARDWARE: + temp_mask =3D current_pmu_hw_event_map[config].counter_mask; + break; + case PERF_TYPE_HW_CACHE: + ret =3D cdeleg_pmu_event_find_cache(config, NULL, &temp_mask); + if (ret) + return ret; + break; + case PERF_TYPE_RAW: + /* + * Mask off the counters that can't monitor this event (specified via js= on) + * The counter mask for this event is set in config2 via the property 'C= ounter' + * in the json file or manual configuration of config2. If the config2 i= s not set, + * it is assumed all the available hpmcounters can monitor this event. + * Note: This assumption may fail for virtualization use case where they= hypervisor + * (e.g. KVM) virtualizes the counter. Any event to counter mapping prov= ided by the + * guest is meaningless from a hypervisor perspective. Thus, the hypervi= sor doesn't + * set config2 when creating kernel counter and relies default host mapp= ing. + */ + if (event->attr.config2) + temp_mask =3D event->attr.config2; + break; + default: + break; + } + + if (temp_mask) + hw_ctr_mask &=3D temp_mask; =20 - /* Select only hpmcounters */ - hw_ctr_mask =3D cmask & (~0x7); - hw_ctr_mask &=3D ~(cpuc->used_hw_ctrs[0]); return __ffs(hw_ctr_mask); } =20 @@ -1429,10 +1483,6 @@ static int rvpmu_deleg_ctr_get_idx(struct perf_event= *event) u64 priv_filter; int idx; =20 - /* - * TODO: We should not rely on SBI Perf encoding to check if the event - * is a fixed one or not. - */ if (!is_sampling_event(event)) { idx =3D get_deleg_fixed_hw_idx(cpuc, event); if (idx =3D=3D 0 || idx =3D=3D 2) { diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 9e2758c32e8b..e58f83811988 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -30,6 +30,8 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 #define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_CYCLE_FIXED_CTR_MASK 0x01 +#define RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK 0x04 =20 #define HW_OP_UNSUPPORTED 0xFFFF #define CACHE_OP_UNSUPPORTED 0xFFFF --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95F561F8675 for ; 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Mon, 27 Jan 2025 21:00:16 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:16 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:58 -0800 Subject: [PATCH v3 17/21] RISC-V: perf: Add legacy event encodings via sysfs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-17-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_dev.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index ab84f83df5e1..055011f07759 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -122,7 +122,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_= group =3D { .attrs =3D riscv_cdeleg_pmu_formats_attr, }; =20 +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=3D" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=3D" RVPMU_EVENT_ATTR_RESOLVE(mask) "\n") + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init= =3D { + .name =3D "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] =3D { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -362,11 +375,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MA= X] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; =20 -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , \ + _cache_event_map, _attrs) \ { .vendorid =3D _vendorid, .archid =3D _archid, .implid =3D _implid, \ - .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map = }, + .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map,= \ + .attrs_events =3D _attrs }, =20 static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { }; @@ -388,6 +404,8 @@ static void rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid =3D=3D arch_id) { current_pmu_hw_event_map =3D pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map =3D pmu_vendor_events_table[i].cache_event_= map; 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Mon, 27 Jan 2025 21:00:18 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:18 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 20:59:59 -0800 Subject: [PATCH v3 18/21] RISC-V: perf: Add Qemu virt machine events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-18-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Signed-off-by: Atish Patra --- arch/riscv/include/asm/vendorid_list.h | 4 ++++ drivers/perf/riscv_pmu_dev.c | 36 ++++++++++++++++++++++++++++++= ++++ 2 files changed, 40 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index 2f2bb0c84f9a..ef22b03552bc 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,4 +9,8 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 +#define QEMU_VIRT_VENDOR_ID 0x000 +#define QEMU_VIRT_IMPL_ID 0x000 +#define QEMU_VIRT_ARCH_ID 0x000 + #endif diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 055011f07759..db4a61fac838 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -384,7 +385,42 @@ struct riscv_vendor_pmu_events { .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map,= \ .attrs_events =3D _attrs }, =20 +/* QEMU virt PMU events */ +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_M= AX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D {0x01, 0xFFFFFFF8}, + [PERF_COUNT_HW_INSTRUCTIONS] =3D {0x02, 0xFFFFFFF8} +}; + +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_H= W_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10019, 0xFFFFFFF8}, + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] =3D {0x1001B, 0xFFFFFFF8}, + + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10021, 0xFFFFFFF8}, +}; + +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFF= F8); +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFF= FFF8); +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFF= F8); + +static struct attribute *qemu_virt_event_group[] =3D { + RVPMU_EVENT_ATTR_PTR(cycles), + RVPMU_EVENT_ATTR_PTR(instructions), + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + NULL, +}; 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Mon, 27 Jan 2025 21:00:20 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:19 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 21:00:00 -0800 Subject: [PATCH v3 19/21] tools/perf: Support event code for arch standard events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-19-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 RISC-V relies on the event encoding from the json file. That includes arch standard events. If event code is present, event is already updated with correct encoding. No need to update it again which results in losing the event encoding. Signed-off-by: Atish Patra --- tools/perf/pmu-events/arch/riscv/arch-standard.json | 10 ++++++++++ tools/perf/pmu-events/jevents.py | 4 +++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/riscv/arch-standard.json b/tools/pe= rf/pmu-events/arch/riscv/arch-standard.json new file mode 100644 index 000000000000..96e21f088558 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/arch-standard.json @@ -0,0 +1,10 @@ +[ + { + "EventName": "cycles", + "BriefDescription": "cycle executed" + }, + { + "EventName": "instructions", + "BriefDescription": "instruction retired" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 5fd906ac6642..28acd598dd7c 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -417,7 +417,9 @@ class JsonEvent: self.long_desc +=3D extra_desc if arch_std: if arch_std.lower() in _arch_std_events: - event =3D _arch_std_events[arch_std.lower()].event + # No need to replace as evencode would have updated the event befo= re + if not eventcode: + event =3D _arch_std_events[arch_std.lower()].event # Copy from the architecture standard event to self for undefined = fields. for attr, value in _arch_std_events[arch_std.lower()].__dict__.ite= ms(): if hasattr(self, attr) and not getattr(self, attr): --=20 2.34.1 From nobody Sat May 9 07:19:09 2026 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9D561F91FF for ; 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Mon, 27 Jan 2025 21:00:22 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f7ffa5a7f7sm8212776a91.11.2025.01.27.21.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2025 21:00:21 -0800 (PST) From: Atish Patra Date: Mon, 27 Jan 2025 21:00:01 -0800 Subject: [PATCH v3 20/21] tools/perf: Pass the Counter constraint values in the pmu events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250127-counter_delegation-v3-20-64894d7e16d5@rivosinc.com> References: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 RISC-V doesn't have any standard event to counter mapping discovery mechanism in the ISA. The ISA defines 29 programmable counters and platforms can choose to implement any number of them and map any events to any counters. Thus, the perf tool need to inform the driver about the counter mapping of each events. The current perf infrastructure only parses the 'Counter' constraints in metrics. This patch extends that to pass in the pmu events so that any driver can retrieve those values via perf attributes if defined accordingly. Signed-off-by: Atish Patra --- tools/perf/pmu-events/jevents.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 28acd598dd7c..c21945238469 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -274,6 +274,11 @@ class JsonEvent: return fixed[name.lower()] return event =20 + def counter_list_to_bitmask(counterlist): + counter_ids =3D list(map(int, counterlist.split(','))) + bitmask =3D sum(1 << pos for pos in counter_ids) + return bitmask + def unit_to_pmu(unit: str) -> Optional[str]: """Convert a JSON Unit to Linux PMU name.""" if not unit or unit =3D=3D "core": @@ -427,6 +432,10 @@ class JsonEvent: else: raise argparse.ArgumentTypeError('Cannot find arch std event:', ar= ch_std) =20 + if self.counters['list']: + bitmask =3D counter_list_to_bitmask(self.counters['list']) + event +=3D f',counterid_mask=3D{bitmask:#x}' + self.event =3D real_event(self.name, event) =20 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<20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> In-Reply-To: <20250127-counter_delegation-v3-0-64894d7e16d5@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Signed-off-by: Atish Patra --- tools/perf/pmu-events/empty-pmu-events.c | 144 +++++++++++++++------------= ---- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 3a7ec31576f5..22f0463dc522 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -36,42 +36,42 @@ static const char *const big_c_string =3D /* offset=3D1127 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000e= vent=3D0x8a\000\00000\000\000\000" /* offset=3D1187 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000e= vent=3D0x8b\000\00000\000\000\000" /* offset=3D1247 */ "l3_cache_rd\000cache\000L3 cache access, read\000even= t=3D0x40\000\00000\000Attributable Level 3 cache access, read\000\000" -/* offset=3D1343 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,= 1\000" -/* offset=3D1446 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20\000\00000\000\0000,1\000" -/* offset=3D1580 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\0= 0000\000\0000,1\000" -/* offset=3D1699 */ "hisi_sccl,ddrc\000" -/* offset=3D1714 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000\000" -/* offset=3D1801 */ "uncore_cbox\000" -/* offset=3D1813 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted fro= m L3 Eviction which misses in some processor core\0000,1\000" -/* offset=3D2048 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000\000" -/* offset=3D2114 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" -/* offset=3D2186 */ "hisi_sccl,l3c\000" -/* offset=3D2200 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000\000" -/* offset=3D2281 */ "uncore_imc_free_running\000" -/* offset=3D2305 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000\000" -/* offset=3D2401 */ "uncore_imc\000" -/* offset=3D2412 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000\000" -/* offset=3D2491 */ "uncore_sys_ddr_pmu\000" -/* offset=3D2510 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000" -/* offset=3D2584 */ "uncore_sys_ccn_pmu\000" -/* offset=3D2603 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000" -/* offset=3D2678 */ "uncore_sys_cmn_pmu\000" -/* offset=3D2697 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000" -/* offset=3D2838 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=3D2860 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" -/* offset=3D2923 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D3089 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3153 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3220 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D3291 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D3385 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" -/* offset=3D3519 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D3583 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3651 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3721 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3D3743 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3D3765 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D3785 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D1343 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80,counterid_mask=3D0x= 3\000\00000\000\0000,1\000" +/* offset=3D1465 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20,counterid_mask=3D0x3\000\00000\000\0000,1\000" +/* offset=3D1618 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000,count= erid_mask=3D0x3\000\00000\000\0000,1\000" +/* offset=3D1756 */ "hisi_sccl,ddrc\000" +/* offset=3D1771 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000\000" +/* offset=3D1858 */ "uncore_cbox\000" +/* offset=3D1870 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81,counterid_mask=3D0x3\000\00000\000A cross-co= re snoop resulted from L3 Eviction which misses in some processor core\0000= ,1\000" +/* offset=3D2124 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000\000" +/* offset=3D2190 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" +/* offset=3D2262 */ "hisi_sccl,l3c\000" +/* offset=3D2276 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000\000" +/* offset=3D2357 */ "uncore_imc_free_running\000" +/* offset=3D2381 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000\000" +/* offset=3D2477 */ "uncore_imc\000" +/* offset=3D2488 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000\000" +/* offset=3D2567 */ "uncore_sys_ddr_pmu\000" +/* offset=3D2586 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000" +/* offset=3D2660 */ "uncore_sys_ccn_pmu\000" +/* offset=3D2679 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000" +/* offset=3D2754 */ "uncore_sys_cmn_pmu\000" +/* offset=3D2773 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000" +/* offset=3D2914 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" +/* offset=3D2936 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" +/* offset=3D2999 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3D3165 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3229 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3296 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3D3367 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3D3461 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" +/* offset=3D3595 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" +/* offset=3D3659 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3727 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3797 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" +/* offset=3D3819 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" +/* offset=3D3841 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3D3861 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" ; =20 static const struct compact_pmu_event pmu_events__common_tool[] =3D { @@ -101,27 +101,27 @@ const struct pmu_table_entry pmu_events__common[] =3D= { static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { { 1127 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0= x8a\000\00000\000\000\000 */ { 1187 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0= x8b\000\00000\000\000\000 */ -{ 1446 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20\000\00000\000\0000,1\000 */ -{ 1580 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000= \0000,1\000 */ +{ 1465 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20,counterid_mask=3D0x3\000\00000\000\0000,1\000 */ +{ 1618 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000,counterid_mas= k=3D0x3\000\00000\000\0000,1\000 */ { 1247 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40= \000\00000\000Attributable Level 3 cache access, read\000\000 */ -{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,1\000 */ +{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80,counterid_mask=3D0x3\000\00= 000\000\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { -{ 1714 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000\000 */ +{ 1771 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { -{ 2200 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000\000 */ +{ 2276 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { -{ 2048 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000\000 */ -{ 2114 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000\000 */ -{ 1813 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted from L3 Evi= ction which misses in some processor core\0000,1\000 */ +{ 2124 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000\000 */ +{ 2190 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000\000 */ +{ 1870 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81,counterid_mask=3D0x3\000\00000\000A cross-core snoop= resulted from L3 Eviction which misses in some processor core\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { -{ 2412 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000\000 */ +{ 2488 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { -{ 2305 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000\000 */ +{ 2381 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000\000 */ =20 }; =20 @@ -134,46 +134,46 @@ const struct pmu_table_entry pmu_events__test_soc_cpu= [] =3D { { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 1699 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 1756 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 2186 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 2262 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 1801 /* uncore_cbox\000 */ }, + .pmu_name =3D { 1858 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 2401 /* uncore_imc\000 */ }, + .pmu_name =3D { 2477 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_= running), - .pmu_name =3D { 2281 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 2357 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 2838 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 3519 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ -{ 3291 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 3385 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ -{ 3583 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ -{ 3651 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 2923 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 2860 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ -{ 3785 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ -{ 3721 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 3743 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 3765 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 3220 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ -{ 3089 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ -{ 3153 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ +{ 2914 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 3595 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ +{ 3367 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 3461 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ +{ 3659 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ +{ 3727 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ +{ 2999 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 2936 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ +{ 3861 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ +{ 3797 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 3819 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 3841 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 3296 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ +{ 3165 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ +{ 3229 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ =20 }; =20 @@ -186,13 +186,13 @@ const struct pmu_table_entry pmu_metrics__test_soc_cp= u[] =3D { }; =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { -{ 2603 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000 */ +{ 2679 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { -{ 2697 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000 */ +{ 2773 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { -{ 2510 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000 */ +{ 2586 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000 */ =20 }; =20 @@ -200,17 +200,17 @@ const struct pmu_table_entry pmu_events__test_soc_sys= [] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_p= mu), - .pmu_name =3D { 2584 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 2660 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_p= mu), - .pmu_name =3D { 2678 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 2754 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_p= mu), - .pmu_name =3D { 2491 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 2567 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 --=20 2.34.1