From nobody Thu Jan 30 17:29:24 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A9571E495; Fri, 24 Jan 2025 06:09:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737698994; cv=none; b=Nrc7d2eMKg6CxrDQMxI0qfk8kxJVUcSYSf8YzxmJQSfEuLdk3aeEcxiyQ1PmWdwqy/62hhxmIxdIIR22Pc16C1MVLjCZmyzvS3CcTN4UJFC9SRavuLj/wy8X2ik4yB2Lvh3FincznuL6A+Kbl0Mfpn+eM4hKxXyOLKG4PcTOXRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737698994; c=relaxed/simple; bh=HB5ZnS4q+1lNjRNFRKOBEryWyeX+Hii0iaTR+Pz3n5g=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=s58kKcBFc6ORhbQxDwftSMNa7OTJWGjncgVak/blruVaGxt3bhAw6ArnInsL21ojZyN6EfAvr7DVU6Oi53xo1GFYyU5zMQATx2LneuGV4il/QWnDk24OzV/8kALxRpdT7UhhSTeNOmEEghJyua0hMTR1vXLOqUYl4/TmsOVyn0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=JXK84GrT; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="JXK84GrT" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50NK2Mqs026145; Fri, 24 Jan 2025 06:09:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=4/HEvOW1RLDEzWT1JFcEf3 SsQ9lKIFOIxW0RaecRrXY=; b=JXK84GrT4owp9Ki8p8xh/t0InoufP512dJ0jN/ vNyLzK8IpVLmVwhZ95crZMy3Y+mpyKTi0h1V/hMdlZ3UmqeIDDXN0T2Vu1NMHhle LKEJPCvyHQCIU74AkZainmVO8NddU4D4CQQ5zU986CaHkQKwUBC9LQklTnfNwQ+f snexEZjVxTneeoatlf6uAdVgjps/M5FqPxqVBI5cwcWGdoFqfbdUo6XoV7FYIlw6 buL5m8s0QRZonDCEDLpykpXJyhreBbqcaS4DeZ2U7xOMjmtMJHdKEBErZQVBcQBC Uwadqtk0VnvEjjtbbii/qVK4xV9r4Sap/2/XivbTWz+xuFYQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44bvenh19a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Jan 2025 06:09:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50O69mY4023687 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 Jan 2025 06:09:48 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 23 Jan 2025 22:09:44 -0800 From: Manikanta Mylavarapu To: , , , , , , , , Subject: [PATCH v2] clk: qcom: ipq5424: fix software and hardware flow control error of UART Date: Fri, 24 Jan 2025 11:39:14 +0530 Message-ID: <20250124060914.1564681-1-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oQV7EXfUrJ5q7eWm6KeMwV-IdUs4yeFX X-Proofpoint-ORIG-GUID: oQV7EXfUrJ5q7eWm6KeMwV-IdUs4yeFX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-24_02,2025-01-23_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 adultscore=0 spamscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501240042 The UART=E2=80=99s software and hardware flow control are currently not functioning correctly. For software flow control, the following error is encountered: qcom_geni_serial 1a80000.serial: Couldn't find suitable clock rate for 56000000, 3500000, 2500000, 1152000, 921600, 19200 During hardware flow control testing, a =E2=80=9CRetry 0: Got ZCAN error=E2= =80=9D is observed. To address these issues, update the UART frequency table to include all supported frequencies according to the frequency plan. Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver f= or IPQ5424 SoC") Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Add Fixes tag. drivers/clk/qcom/gcc-ipq5424.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index d5b218b76e29..37b1a3ff8f4e 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -592,13 +592,19 @@ static struct clk_rcg2 gcc_qupv3_spi1_clk_src =3D { }; =20 static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] =3D { - F(960000, P_XO, 10, 2, 5), - F(4800000, P_XO, 5, 0, 0), - F(9600000, P_XO, 2, 4, 5), - F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5), + F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625), + F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625), + F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625), F(24000000, P_XO, 1, 0, 0), F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25), + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20), + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500), + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50), + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625), + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), { } }; base-commit: 853d1f41ba73e78d22e7075d9a95670aab187eba --=20 2.34.1