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[2a02:8428:e55b:1101:1e41:304e:170b:482f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf3278f06sm16418985f8f.70.2025.01.22.05.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jan 2025 05:59:17 -0800 (PST) From: Julien Stephan Date: Wed, 22 Jan 2025 14:59:14 +0100 Subject: [PATCH v8 5/5] arm64: dts: mediatek: mt8365: Add support for camera Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250122-add-mtk-isp-3-0-support-v8-5-a3d3731eef45@baylibre.com> References: <20250122-add-mtk-isp-3-0-support-v8-0-a3d3731eef45@baylibre.com> In-Reply-To: <20250122-add-mtk-isp-3-0-support-v8-0-a3d3731eef45@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan X-Mailer: b4 0.14.2 Add base support for cameras for mt8365 platforms. This requires nodes for the sensor interface, camsv, and CSI receivers. Reviewed-by: Laurent Pinchart Signed-off-by: Julien Stephan --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 125 +++++++++++++++++++++++++++= ++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 9c91fe8ea0f969770a611f90b593683f93ff3e22..f3aae8d76cbece5779fe0b23139= d594c0ea52579 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8365"; @@ -704,6 +705,23 @@ ethernet: ethernet@112a0000 { status =3D "disabled"; }; =20 + mipi_csi0: mipi-csi0@11c10000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c10000 0 0x2000>; + status =3D "disabled"; + num-lanes =3D <4>; + #phy-cells =3D <1>; + }; + + mipi_csi1: mipi-csi1@11c12000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c12000 0 0x2000>; + phy-type =3D ; + status =3D "disabled"; + num-lanes =3D <4>; + #phy-cells =3D <0>; + }; + u3phy: t-phy@11cc0000 { compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells =3D <1>; @@ -774,6 +792,113 @@ larb2: larb@15001000 { mediatek,larb-id =3D <2>; }; =20 + seninf: seninf@15040000 { + compatible =3D "mediatek,mt8365-seninf"; + reg =3D <0 0x15040000 0 0x6000>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names =3D "camsys", "top_mux"; + + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + + phys =3D <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names =3D "csi0", "csi1"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + + port@4 { + reg =3D <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint =3D + <&camsv1_endpoint>; + }; + }; + + port@5 { + reg =3D <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint =3D + <&camsv2_endpoint>; + }; + }; + }; + }; + + camsv1: camsv@15050000 { + compatible =3D "mediatek,mt8365-camsv"; + reg =3D <0 0x15050000 0 0x0040>, + <0 0x15050208 0 0x0020>, + <0 0x15050400 0 0x0100>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV0>; + clock-names =3D "cam", "camtg", "camsv"; + iommus =3D <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb =3D <&larb2>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + camsv1_endpoint: endpoint { + remote-endpoint =3D <&seninf_camsv1_endpoint>; + }; + }; + }; + }; + + camsv2: camsv@15050800 { + compatible =3D "mediatek,mt8365-camsv"; + reg =3D <0 0x15050800 0 0x0040>, + <0 0x15050228 0 0x0020>, + <0 0x15050c00 0 0x0100>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV1>; + clock-names =3D "cam", "camtg", "camsv"; + iommus =3D <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb =3D <&larb2>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + camsv2_endpoint: endpoint { + remote-endpoint =3D <&seninf_camsv2_endpoint>; + }; + }; + }; + }; + vdecsys: syscon@16000000 { compatible =3D "mediatek,mt8365-vdecsys", "syscon"; reg =3D <0 0x16000000 0 0x1000>; --=20 2.47.1