From nobody Fri Dec 19 21:54:47 2025 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 484221F37A6 for ; Tue, 21 Jan 2025 13:48:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737467315; cv=none; b=T1t63DxkiKoka8h4a1hSRVLSWTckPQrGOA0uR4armTj6redTC3ea+1oalkuIEg3x+MkkrL7Tcbf6J1+OjGKwCcWqQZICnLzGxP6M0/m1bRD48nS4la4TbbcWMj8y4MoqtekglxCwgI3QCMfpbKXqULJzbZ+EOPYJfnVYysT3TGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737467315; c=relaxed/simple; bh=nLd6SBx8bYo+CaXVGjzyPZEBGv6kFvBc6zDO6shy8yw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=m0tW5uY/4kKIIZbSdT0rbbFsYvqw6w8jCG/gv2vAbgAVHeU03vGaCqaCJVqh+cd8Z1swbX4g2GitHq/ZyswOy6fc8AKliFeSaYnOQe4a/tFrtG9Pqcztvk0+D6iQmiFMOxKkOPPzopujrO0eG6wfSW4sW5AEhVU40KSE0w1zYdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VpGlern/; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VpGlern/" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-21644aca3a0so125187805ad.3 for ; Tue, 21 Jan 2025 05:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1737467312; x=1738072112; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=KHhrcwSV5gVycE0fiHKV7RdTl3Q9CP6hDVIbPOyumYU=; b=VpGlern/vMlvmMHrszutlRd1245DefPs1hgJ96rsTJXSjkBl5o80WEqN0W0O90B7hs w5aD4Ty4LBKC0ZIX1Gcuh0dNqg/mvfGy6nM0fHLToeh5eeb6koD15opTKxXHPnFMb955 y2LjXvFTEjZQ+iwv2tNOJC+bu/jVc7fiDQZMa2F2nP+U4+IKH3iKwAO3CZl+YNq8NiSs XKP2apKRCh1sm4ovamNOzIYuh83J6YJ7ENqmyZCYwW/6+WNvlBrDcIZyzRnx4FmgJEKA iTS1gkCZRIor+u+K47+hKcceqCGByAmcdAQsztcToZJQEnT6rcRSINB4i/60HzTUEd9E s1zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737467312; x=1738072112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KHhrcwSV5gVycE0fiHKV7RdTl3Q9CP6hDVIbPOyumYU=; b=dSuTvsgHbbETbfwH3CJoBFH7ncN8cWpQfkgHMgv+vSmh4/ApfDG4rXZRPHsyspXMDY Umr/Qvutqy/qfpJRC4aZCYkJKNHPXY2Z6TL+BkhpaQIiqOemvJKoEthmtePZMPPOPv/Q AzzDbITOwYef+ds2Cx+0o8d2AtQSjODCwhQ/j73smjKQompWpRurjBAmYY0AezPSCsBC wK4mq00VesPy+qf/b7vO+aVhSiN/dxgtDTqbVgCO96Sft7sm2mb5bEhNdRSAP738U3eY lJardEfa2j8u+R+Z6d0yruLvg/eCYufNpubi7PB8d5cbViIy9md+jEct9ZbESIKX4ILj leHg== X-Forwarded-Encrypted: i=1; AJvYcCWIUFRYePv2Y8ghnWMnAfRi2lF96h7bLAYtOiQohtKQ1qBgQLZd2Y7BSpBPPI/JCKLdFxh/C2qAY9oi8jM=@vger.kernel.org X-Gm-Message-State: AOJu0YzWFnF6O8v2mhNBxZaUK4Or06iUVnxoJbEQQViVFcZjCXzv2kBb usT54ClL0Bent1QtHYy5MTTbmilVSz/A+0fGpLL39J8bR/LIbPVi X-Gm-Gg: ASbGncuTQ3aMyCOrpo8aSGnctRygEYjAyDwnhycpK33eJA46FoBnDF6GRVJ7ktcKz3I Q6c6b1Whpy28Lb+5PLNBcuSiwYl8zNBWG9OPbvrfY3vIdLE3Waer1G9ZeqiZ2EflZcpq892wzcI 6X8VXnF/Qmb7tUcVekbNIO7bPGshtjAtQ0UTWz+/TORnRsobEIV/GjOsqRVCk6AypRSygUFZTAe JWCBCMXSJ1Ns2qW3pom9FeZHGHM6XzKqj2IZT2wNCh56HWQLc0Hra5Z3wRj47fQJ940zrIZMHFX qXFTQTW+ZrzGMQ== X-Google-Smtp-Source: AGHT+IHm5MzzsASxMbvgFHxZ+JP4w7CgMK4Xn//ZyrTxkv9Iyn+vWv+tr7VrWbz1DqG9EtF+rt1Z3g== X-Received: by 2002:a05:6a20:d49a:b0:1e1:adcd:eae5 with SMTP id adf61e73a8af0-1eb2160ff91mr21719711637.42.1737467311797; Tue, 21 Jan 2025 05:48:31 -0800 (PST) Received: from distilledx.SRMIST.EDU.IN ([103.4.222.252]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-a9bdf0b513asm7408655a12.71.2025.01.21.05.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 05:48:31 -0800 (PST) From: Tejas Vipin To: neil.armstrong@linaro.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch Cc: quic_jesszhan@quicinc.com, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tejas Vipin Subject: [PATCH] drm/panel: samsung-s6e88a0-ams452ef01: transition to mipi_dsi wrapped functions Date: Tue, 21 Jan 2025 19:18:19 +0530 Message-ID: <20250121134819.251718-1-tejasvipin76@gmail.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Changes the samsung-s6e88a0-ams452ef01 panel to use multi style functions for improved error handling. Signed-off-by: Tejas Vipin Reviewed-by: Douglas Anderson --- .../panel/panel-samsung-s6e88a0-ams452ef01.c | 89 +++++++------------ 1 file changed, 31 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c b/dri= vers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c index d2df227abbea..c80775b0aad3 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c @@ -39,91 +39,68 @@ static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams= 452ef01 *ctx) static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx) { struct mipi_dsi_device *dsi =3D ctx->dsi; - struct device *dev =3D &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D dsi }; =20 dsi->mode_flags |=3D MIPI_DSI_MODE_LPM; =20 - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands - mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polar= ity + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // enable LEVEL= 2 commands + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcc, 0x4c); // set Pixel Clock Di= vider polarity =20 - ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); =20 // set default brightness/gama - mipi_dsi_dcs_write_seq(dsi, 0xca, - 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB - 0x80, 0x80, 0x80, // V203 R,G,B - 0x80, 0x80, 0x80, // V151 R,G,B - 0x80, 0x80, 0x80, // V87 R,G,B - 0x80, 0x80, 0x80, // V51 R,G,B - 0x80, 0x80, 0x80, // V35 R,G,B - 0x80, 0x80, 0x80, // V23 R,G,B - 0x80, 0x80, 0x80, // V11 R,G,B - 0x6b, 0x68, 0x71, // V3 R,G,B - 0x00, 0x00, 0x00); // V1 R,G,B + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, + 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,// V255 RR,GG,BB + 0x80, 0x80, 0x80, // V203 R,G,B + 0x80, 0x80, 0x80, // V151 R,G,B + 0x80, 0x80, 0x80, // V87 R,G,B + 0x80, 0x80, 0x80, // V51 R,G,B + 0x80, 0x80, 0x80, // V35 R,G,B + 0x80, 0x80, 0x80, // V23 R,G,B + 0x80, 0x80, 0x80, // V11 R,G,B + 0x6b, 0x68, 0x71, // V3 R,G,B + 0x00, 0x00, 0x00); // V1 R,G,B // set default Amoled Off Ratio - mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); - mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss volta= ge - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0x2c, 0x0b); // set default = elvss voltage + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma/aor update + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5); // disable LEVE= L2 commands =20 - ret =3D mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); =20 - return 0; + return dsi_ctx.accum_err; } =20 static int s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx) { struct mipi_dsi_device *dsi =3D ctx->dsi; - struct device *dev =3D &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D dsi}; =20 dsi->mode_flags &=3D ~MIPI_DSI_MODE_LPM; =20 - ret =3D mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(35); - - ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 35); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); =20 - return 0; + return dsi_ctx.accum_err; } =20 static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel) { struct s6e88a0_ams452ef01 *ctx =3D to_s6e88a0_ams452ef01(panel); - struct device *dev =3D &ctx->dsi->dev; int ret; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); - if (ret < 0) { - dev_err(dev, "Failed to enable regulators: %d\n", ret); + if (ret < 0) return ret; - } =20 s6e88a0_ams452ef01_reset(ctx); =20 ret =3D s6e88a0_ams452ef01_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); @@ -136,12 +113,8 @@ static int s6e88a0_ams452ef01_prepare(struct drm_panel= *panel) static int s6e88a0_ams452ef01_unprepare(struct drm_panel *panel) { struct s6e88a0_ams452ef01 *ctx =3D to_s6e88a0_ams452ef01(panel); - struct device *dev =3D &ctx->dsi->dev; - int ret; =20 - ret =3D s6e88a0_ams452ef01_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + s6e88a0_ams452ef01_off(ctx); =20 gpiod_set_value_cansleep(ctx->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); --=20 2.48.1