From nobody Tue Feb 10 01:17:56 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2BFD1F2375 for ; Tue, 21 Jan 2025 12:56:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737464182; cv=none; b=KSClvorkMNZoXldFvWCJvzYqX+zRpLLCs5lvS9BOYf9OHa6LlwJSzx1+QhTzY5PzI9McE1ZNXQuKLmMUAEiZEjmh7Lhg0G2/wRz8hw5u0HqXO+GmsckerQdxxv1eIJzLoES6zpCaRZEprIJ3r3pDc+LU89JItUOAho3nvKq2l2c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737464182; c=relaxed/simple; bh=zkCwi5FnK5wPCkeA+FruP2G2sZBycMp67B53czYr/6Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pRPvgCYHXgFWsUxgJMn3ZoTPXv7SeHw1+8M5rcAD3UEg6mE27avZ4TmYMII+weXyMurDk/ie+q69WyWRvu6Sja4ck+GR8PRFvkwLo+GuvA3eYUKh80tYuiXl0q0zvTgLQao6AjBlXrMVHCad2OJonJB/Kj455+o1mXObzCyHUgo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thaumatec.com; spf=pass smtp.mailfrom=thaumatec.com; dkim=pass (2048-bit key) header.d=thaumatec-com.20230601.gappssmtp.com header.i=@thaumatec-com.20230601.gappssmtp.com header.b=XpLvY1dk; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thaumatec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thaumatec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=thaumatec-com.20230601.gappssmtp.com header.i=@thaumatec-com.20230601.gappssmtp.com header.b="XpLvY1dk" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5d3d479b1e6so8310555a12.2 for ; Tue, 21 Jan 2025 04:56:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thaumatec-com.20230601.gappssmtp.com; s=20230601; t=1737464178; x=1738068978; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RiSS1nYpUCNiSeYMCfYpcAR25/sptrb9q7TkmxVtubc=; b=XpLvY1dk2L5JB0bcHjksR5QgHP1TWAL0Rpg1CZsLqGmpoK1nNbDrgOwPyuqSShn8MO GPhHAExIYl9VYszhRja4X0PXJLXaN+kWJByCxiYbJhZDJvKmsaQ2z1Vh+cL1x5v/+Xrk 9ei5ZaTRZOa72EYGzx+c4Q1h8xwbbN/Wpu5pQJAnDNM2kPVd9Y5fAl4uLIUlncPgq8+W Wl8lzBnn72LCtFkw8MdVXGSILgayIFC/XfyaDtw/7+8EwNPAtwkjlHTfP+ydHzMAIfz8 s5DHGsK2yI1Zmtkt0ho6P7ViRvmwazjJwehimtRINSe0JiLozsiWdZ5xW0MwyD2zQWXO 4Fug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737464178; x=1738068978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RiSS1nYpUCNiSeYMCfYpcAR25/sptrb9q7TkmxVtubc=; b=IvaUP8BFPZh4Zq97Zn2bD7c+/tQb8+IznlGDd420K+oIoLyng9lbxCBtGTYx85qipT UlTudSSHUzMY+2XyGSuWtGkXoxKqyny/AJ1bMhSdKF9P+daCBGhFTN2RBLarPID727UH 3OwMXhNLu6zoV/G5MDOR/LN4xtZTo3DIQuqvbc7OReHjO/QIM1WJhgAFgQo7u9w0dsVD P/Y4DGZSSvSs/XjkWSV4Lr0fBm7D0yL8Y9MDF8+2b1Ikh+7SvGhivfP8BLevxH09XSzX +98cFwkIgT92lc1TKTGOmBOeEqG0AN2bpuNK6yUjVJTjuzkG5IPdn4ZFRPLwRtQQe/Nz 3jrQ== X-Forwarded-Encrypted: i=1; AJvYcCWPnS1S+Ymlt6WA3Heg+iYsW+Nf6cSq92N2YvNACyIjJPLJaGfQTDpxSBB697X0ro/xusTcmzc7qSaJ0ME=@vger.kernel.org X-Gm-Message-State: AOJu0Yx1WoCRjchV4UpUFj0NSorhi0cg8fJzvzr/z4F+wo+obWgNfso9 iCm3cSP2Ff3I2Plf95TGAh7mXZcScsBE6OF5j7HsJeYd24yOjzcRblBxdlzTRc4= X-Gm-Gg: ASbGncuBWt7ZrkAwtDMMtWENWUfzlPbfiwFwO8lgRenvuOCuhxGoDQPD1KxJzUCxTna a9dbQznEH0ETmKI653FEtUlqLODgI8Hk2MON8pI5qER5HAs2LXg0fTUnNwAZqpHHe2QMcrU9V/D BaUXSndsIAL7Q1gVMB67V4TuKUmk/dEhQ2afrKjSvmUfnF2J/kXrXaW3xSNADDdM7bijEqCuOtt pZ78H+cQoY2/8QAxFIbNzcKplAIUCcHC/IKtlOC+ylhI5iBV13EuVq9MaN2+0S8L4v1LFkL3sw5 UdoEmjn4S0RQHOem8SNYnEt/dw== X-Google-Smtp-Source: AGHT+IGNUrQ1owGiuycreL+ecfL6xNDC4NN9qxkE8FnFn4B+VO++Fb989ERQC0artIbK2G1crar2zw== X-Received: by 2002:a50:9357:0:b0:5db:e91a:6baf with SMTP id 4fb4d7f45d1cf-5dbe91a6ce3mr1051424a12.14.1737464178063; Tue, 21 Jan 2025 04:56:18 -0800 (PST) Received: from lczechowski-Latitude-5440.. ([78.9.4.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384ce0529sm740943866b.43.2025.01.21.04.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 04:56:17 -0800 (PST) From: Lukasz Czechowski To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quentin.schulz@cherry.de, Lukasz Czechowski , stable@vger.kernel.org Subject: [PATCH v2 1/2] arm64: dts: rockchip: Move uart5 pin configuration to SoM dtsi Date: Tue, 21 Jan 2025 13:56:03 +0100 Message-ID: <20250121125604.3115235-2-lukasz.czechowski@thaumatec.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250121125604.3115235-1-lukasz.czechowski@thaumatec.com> References: <20250121125604.3115235-1-lukasz.czechowski@thaumatec.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for uart5 cannot be used for the UART CTS/RTS, because they are already allocated for different purposes. CTS pin is routed to SUS_S3# signal, while RTS pin is used internally and is not available on Q7 connector. Move definition of the pinctrl-0 property from px30-ringneck-haikou.dts to px30-ringneck.dtsi. This commit is a dependency to next commit in the patch series, that disables DMA for uart5. Cc: stable@vger.kernel.org Reviewed-by: Quentin Schulz Signed-off-by: Lukasz Czechowski --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 - arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index e4517f47d519c..eb9470a00e549 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -226,7 +226,6 @@ &uart0 { }; =20 &uart5 { - pinctrl-0 =3D <&uart5_xfer>; rts-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index ae050cc6cd050..2c87005c89bd3 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -396,6 +396,10 @@ &u2phy_host { status =3D "okay"; }; =20 +&uart5 { + pinctrl-0 =3D <&uart5_xfer>; +}; + /* Mule UCAN */ &usb_host0_ehci { status =3D "okay"; --=20 2.43.0