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Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 6d6cbc8b5b2c..3588197ba2d7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -277,6 +277,25 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_= pcie *pci, u16 start, return 0; } =20 +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 v= sec_cap) +{ + u16 vsec =3D 0; + u32 header; + + if (vendor_id !=3D dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) + return 0; + + while ((vsec =3D dw_pcie_find_next_ext_capability(pci, vsec, + PCI_EXT_CAP_ID_VNDR))) { + header =3D dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_ID(header) =3D=3D vsec_cap) + return vsec; + } + + return 0; +} +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability); + u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { return dw_pcie_find_next_ext_capability(pci, 0, cap); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..02e94bd9b042 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -476,6 +476,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); =20 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 v= sec_cap); =20 int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); --=20 2.17.1 From nobody Thu Dec 18 00:12:23 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9FBB1F2367 for ; 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Tue, 21 Jan 2025 20:52:06 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.109.115.6]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250121115203epsmtip1c91f42914922686799b4797c5330bb73~csvWC2urJ1602616026epsmtip1_; Tue, 21 Jan 2025 11:52:03 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, quic_nitegupt@quicinc.com, quic_krichai@quicinc.com, gost.dev@samsung.com, Shradha Todi Subject: [PATCH v5 2/4] Add debugfs based silicon debug support in DWC Date: Tue, 21 Jan 2025 16:44:19 +0530 Message-Id: <20250121111421.35437-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250121111421.35437-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNJsWRmVeSWpSXmKPExsWy7bCmpu7m/v50g3vXWC2mH1a0WNKUYdG0 +i6rxc0DO5ksVnyZyW6xauE1NouGnt+sFpd3zWGzODvvOJtFy58WFou7LZ2sFou2fmG3ePCg 0qJzzhFmi/97drBb9B6udRDw2DnrLrvHgk2lHi1H3rJ6bFrVyeZx59oeNo8nV6YzeUzcU+fR t2UVo8fnTXIBnFHZNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+ AbpumTlAHygplCXmlAKFAhKLi5X07WyK8ktLUhUy8otLbJVSC1JyCkwK9IoTc4tL89L18lJL rAwNDIxMgQoTsjMmbZvFXrAzrGJn/2fmBsZ+zy5GTg4JAROJxZ0/WbsYuTiEBHYzShxueMwC 4XxilDjwrhHK+cYo8WTzE1aYloNPZzOC2EICexklpu9VhyhqZpLo+fmJGSTBJqAl0fi1C8wW EbCWONy+hQ2kiFngKZNE6/GfQA4Hh7CAm8TZVcIgNSwCqhJLD2wEW8ArYCVx8vt7Fohl8hKr NxwAm8MJNOfNkTtgt0oIzOWQ6DyzhgmiyEViwxUYW1ji1fEt7BC2lMTnd3vZIOx0iZWbZzBD 2DkS3zYvgaq3lzhwZQ4LyD3MApoS63fpQ4RlJaaeWgdWwizAJ9H7+wlUOa/EjnkwtrLEl797 oO6UlJh37DI0gDwkDk+czggJlD5GiZOzj7BPYJSbhbBiASPjKkbJ1ILi3PTUZNMCw7zUcnis JefnbmIEp1Itlx2MN+b/0zvEyMTBeIhRgoNZSYRX9ENPuhBvSmJlVWpRfnxRaU5q8SFGU2AA TmSWEk3OBybzvJJ4QxNLAxMzMzMTS2MzQyVx3uadLelCAumJJanZqakFqUUwfUwcnFINTJuD ZYuMz2SkqjuluD2QunFKL7bYyZgtsu39o22CDI8usX6NYcq6dJdt9u4ZXdmvJY9XXmG8uavq 0j6/lQJKOyazfy2zf3MwcZ12bdRUxXNdrJX36q+K3cwSW9bnKnxQquL41b/JX/ZvdDpUcOqV 6+z0NWdF1T8kT0kqfh+wMiHJ4/yFvleOrG4fj65PCn/fl7pPgUM9v+D5Cj7WxSt2vWcwUWeT 0LC5r6m5o3mr20HHUg9HnxKPq0rJC6y6T6i2VK0Vl5FaX/nwS2tQyuYmScED32RMmqNl7X5s ODqn0vST1WvO4x8Lr9cpdn44/ea+3tyXMQtq9/TIWiu9rUqdcf1XlLsvO7f4eo+He4RnKLEU ZyQaajEXFScCALP1L4guBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsWy7bCSnG5aV3+6wdIzTBbTDytaLGnKsGha fZfV4uaBnUwWK77MZLdYtfAam0VDz29Wi8u75rBZnJ13nM2i5U8Li8Xdlk5Wi0Vbv7BbPHhQ adE55wizxf89O9gteg/XOgh47Jx1l91jwaZSj5Yjb1k9Nq3qZPO4c20Pm8eTK9OZPCbuqfPo 27KK0ePzJrkAzigum5TUnMyy1CJ9uwSujEnbZrEX7Ayr2Nn/mbmBsd+zi5GTQ0LAROLg09mM XYxcHEICuxklGv7uZINISEp8vriOCcIWllj57zk7RFEjk8SBrotgCTYBLYnGr13MILaIgK3E /UeTWUGKmAW+Mkl8/HQDKMHBISzgJnF2lTBIDYuAqsTSAxtZQWxeASuJk9/fs0AskJdYveEA 2BxOAWuJN0fugNUIAdXM3n6KdQIj3wJGhlWMkqkFxbnpucWGBUZ5qeV6xYm5xaV56XrJ+bmb GMHBrqW1g3HPqg96hxiZOBgPMUpwMCuJ8Ip+6EkX4k1JrKxKLcqPLyrNSS0+xCjNwaIkzvvt dW+KkEB6YklqdmpqQWoRTJaJg1Oqgant2UXWRZqHj3E1XBbw8vivmJGrMdGLi/9hobyvxuEr F055WtRkhfbZGTQsDf9d9PJPVBS3ac+xU/nXNWeWzzm/qM9RP71OMfkBa1T54cpShqemHUG/ 90vEyEj/0MmdLTXtWKCESc9V7RlpuV/9Plet+fYrMqJT+NH2rR8vWbu1OxxeN7HxKEN1rrrY ywNH5eOfX8s966y9xuOgg3u76/daacNsJ76d/V/t5mzQ1xeb+tNH5fadjwfyMh/+qMuazqm8 ctvE4ozU1PfHH2469Gz2H0m1BrMKQf/Jb+bfOHs7TTS6aq107h2m+99efAkwk/ka4Zb65KiQ c3PqrOksR/54OnhkLf70WlYsb8IdOyWW4oxEQy3mouJEAOofCo7lAgAA X-CMS-MailID: 20250121115206epcas5p42ce605e6c8500fd2cdfea83a82b101a5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250121115206epcas5p42ce605e6c8500fd2cdfea83a82b101a5 References: <20250121111421.35437-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Add support to provide silicon debug interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 13 ++ drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + .../controller/dwc/pcie-designware-debugfs.c | 173 ++++++++++++++++++ .../pci/controller/dwc/pcie-designware-ep.c | 5 + .../pci/controller/dwc/pcie-designware-host.c | 6 + drivers/pci/controller/dwc/pcie-designware.h | 15 ++ 7 files changed, 223 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-dwc-pcie create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI= /testing/debugfs-dwc-pcie new file mode 100644 index 000000000000..e7920ac82e38 --- /dev/null +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -0,0 +1,13 @@ +What: /sys/kernel/debug/dwc_pcie_/rasdes_debug/lane_detect +Date: January 2025 +Contact: Shradha Todi +Description: (RW) Write the lane number to be checked for detection. Read + will return whether PHY indicates receiver detection on the + selected lane. The default selected lane is Lane0. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_debug/rx_valid +Date: January 2025 +Contact: Shradha Todi +Description: (RW) Write the lane number to be checked as valid or invalid.= Read + will return the status of PIPE RXVALID signal of the selected lane. + The default selected lane is Lane0. diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index b6d6778b0698..99ddc1e18f72 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -6,6 +6,16 @@ menu "DesignWare-based PCIe controllers" config PCIE_DW bool =20 +config PCIE_DW_DEBUGFS + default y + depends on DEBUG_FS + depends on PCIE_DW_HOST || PCIE_DW_EP + bool "DWC PCIe debugfs entries" + help + Enables debugfs entries for the DW PCIe Controller. These entries + make use of the RAS features in the DW controller to help in debug, + error injection and statistical counters. + config PCIE_DW_HOST bool select PCIE_DW diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index a8308d9ea986..54565eedc52c 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_DW) +=3D pcie-designware.o +obj-$(CONFIG_PCIE_DW_DEBUGFS) +=3D pcie-designware-debugfs.o obj-$(CONFIG_PCIE_DW_HOST) +=3D pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c new file mode 100644 index 000000000000..907864c35ef3 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe controller debugfs driver + * + * Copyright (C) 2025 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Shradha Todi + */ + +#include + +#include "pcie-designware.h" + +#define SD_STATUS_L1LANE_REG 0xb0 +#define PIPE_RXVALID BIT(18) +#define PIPE_DETECT_LANE BIT(17) +#define LANE_SELECT GENMASK(3, 0) + +#define DWC_DEBUGFS_BUF_MAX 128 + +struct dwc_pcie_vendor_id { + u16 vendor_id; + u16 vsec_rasdes_cap_id; +}; + +static const struct dwc_pcie_vendor_id dwc_pcie_vendor_ids[] =3D { + {PCI_VENDOR_ID_SAMSUNG, 0x2}, + {} /* terminator */ +}; + +/** + * struct dwc_pcie_rasdes_info - Stores controller common information + * @ras_cap_offset: RAS DES vendor specific extended capability offset + * @reg_lock: Mutex used for RASDES shadow event registers + * @rasdes_dir: Top level debugfs directory entry + * + * Any parameter constant to all files of the debugfs hierarchy for a sing= le controller + * will be stored in this struct. It is allocated and assigned to controll= er specific + * struct dw_pcie during initialization. + */ +struct dwc_pcie_rasdes_info { + u32 ras_cap_offset; + struct mutex reg_lock; + struct dentry *rasdes_dir; +}; + +static ssize_t lane_detect_read(struct file *file, char __user *buf, size_= t count, loff_t *ppos) +{ + struct dw_pcie *pci =3D file->private_data; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t off =3D 0; + u32 val; + + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); + val =3D FIELD_GET(PIPE_DETECT_LANE, val); + if (val) + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Lane Detecte= d\n"); + else + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Lane Undetec= ted\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t lane_detect_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_pcie *pci =3D file->private_data; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + u32 lane, val; + + val =3D kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); + val &=3D ~(LANE_SELECT); + val |=3D FIELD_PREP(LANE_SELECT, lane); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val= ); + + return count; +} + +static ssize_t rx_valid_read(struct file *file, char __user *buf, size_t c= ount, loff_t *ppos) +{ + struct dw_pcie *pci =3D file->private_data; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t off =3D 0; + u32 val; + + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_R= EG); + val =3D FIELD_GET(PIPE_RXVALID, val); + if (val) + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "RX Valid\n"); + else + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "RX Invalid\n= "); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t rx_valid_write(struct file *file, const char __user *buf, s= ize_t count, loff_t *ppos) +{ + return lane_detect_write(file, buf, count, ppos); +} + +#define dwc_debugfs_create(name) \ +debugfs_create_file(#name, 0644, rasdes_debug, pci, \ + &dbg_ ## name ## _fops) + +#define DWC_DEBUGFS_FOPS(name) \ +static const struct file_operations dbg_ ## name ## _fops =3D { \ + .open =3D simple_open, \ + .read =3D name ## _read, \ + .write =3D name ## _write \ +} + +DWC_DEBUGFS_FOPS(lane_detect); +DWC_DEBUGFS_FOPS(rx_valid); + +void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) +{ + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + + debugfs_remove_recursive(rinfo->rasdes_dir); + mutex_destroy(&rinfo->reg_lock); +} + +int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) +{ + struct dentry *dir, *rasdes_debug; + struct dwc_pcie_rasdes_info *rasdes_info; + const struct dwc_pcie_vendor_id *vid; + char dirname[DWC_DEBUGFS_BUF_MAX]; + struct device *dev =3D pci->dev; + int ras_cap; + + for (vid =3D dwc_pcie_vendor_ids; vid->vendor_id; vid++) { + ras_cap =3D dw_pcie_find_vsec_capability(pci, vid->vendor_id, + vid->vsec_rasdes_cap_id); + if (ras_cap) + break; + } + if (!ras_cap) { + dev_dbg(dev, "No RASDES capability available\n"); + return -ENODEV; + } + + rasdes_info =3D devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL); + if (!rasdes_info) + return -ENOMEM; + + /* Create main directory for each platform driver */ + snprintf(dirname, DWC_DEBUGFS_BUF_MAX, "dwc_pcie_%s", dev_name(dev)); + dir =3D debugfs_create_dir(dirname, NULL); + if (IS_ERR(dir)) + return PTR_ERR(dir); + + /* Create subdirectories for Debug, Error injection, Statistics */ + rasdes_debug =3D debugfs_create_dir("rasdes_debug", dir); + + mutex_init(&rasdes_info->reg_lock); + rasdes_info->ras_cap_offset =3D ras_cap; + rasdes_info->rasdes_dir =3D dir; + pci->rasdes_info =3D rasdes_info; + + /* Create debugfs files for Debug subdirectory */ + dwc_debugfs_create(lane_detect); + dwc_debugfs_create(rx_valid); + + return 0; +} diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index f3ac7d46a855..84b5f27a2c69 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -642,6 +642,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); =20 + dwc_pcie_rasdes_debugfs_deinit(pci); dw_pcie_edma_remove(pci); } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); @@ -813,6 +814,10 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) =20 dw_pcie_ep_init_non_sticky_registers(pci); =20 + ret =3D dwc_pcie_rasdes_debugfs_init(pci); + if (ret) + goto err_remove_edma; + return 0; =20 err_remove_edma: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index d2291c3ceb8b..1cd282f70830 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -524,6 +524,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_remove_edma; =20 + ret =3D dwc_pcie_rasdes_debugfs_init(pci); + if (ret) + goto err_remove_edma; + if (!dw_pcie_link_up(pci)) { ret =3D dw_pcie_start_link(pci); if (ret) @@ -571,6 +575,8 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) =20 dw_pcie_stop_link(pci); =20 + dwc_pcie_rasdes_debugfs_deinit(pci); + dw_pcie_edma_remove(pci); =20 if (pp->has_msi_ctrl) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 02e94bd9b042..8d5dc22f06f7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -463,6 +463,7 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + void *rasdes_info; }; =20 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -796,4 +797,18 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 = func_no) return NULL; } #endif + +#ifdef CONFIG_PCIE_DW_DEBUGFS +int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci); 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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250121115209epcas5p3c5974d568705bc669645c72026dcba22 References: <20250121111421.35437-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Add support to provide error injection interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 70 ++++++++ .../controller/dwc/pcie-designware-debugfs.c | 165 +++++++++++++++++- 2 files changed, 233 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI= /testing/debugfs-dwc-pcie index e7920ac82e38..cff205ab2678 100644 --- a/Documentation/ABI/testing/debugfs-dwc-pcie +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -11,3 +11,73 @@ Contact: Shradha Todi Description: (RW) Write the lane number to be checked as valid or invalid.= Read will return the status of PIPE RXVALID signal of the selected lane. The default selected lane is Lane0. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ +Date: January 2025 +Contact: Shradha Todi +Description: rasdes_err_inj is the directory which can be used to inject e= rrors in the + system. The possible errors that can be injected are: + + 1) TLP LCRC error injection TX Path - tx_lcrc + 2) 16b CRC error injection of ACK/NAK DLLP - b16_crc_dllp + 3) 16b CRC error injection of Update-FC DLLP - b16_crc_upd_fc + 4) TLP ECRC error injection TX Path - tx_ecrc + 5) TLP's FCRC error injection TX Path - fcrc_tlp + 6) Parity error of TSOS - parity_tsos + 7) Parity error on SKPOS - parity_skpos + 8) LCRC error injection RX Path - rx_lcrc + 9) ECRC error injection RX Path - rx_ecrc + 10) TLPs SEQ# error - tlp_err_seq + 11) DLLPS ACK/NAK SEQ# error - ack_nak_dllp_seq + 12) ACK/NAK DLLPs transmission block - ack_nak_dllp + 13) UpdateFC DLLPs transmission block - upd_fc_dllp + 14) Always transmission for NAK DLLP - nak_dllp + 15) Invert SYNC header - inv_sync_hdr_sym + 16) COM/PAD TS1 order set - com_pad_ts1 + 17) COM/PAD TS2 order set - com_pad_ts2 + 18) COM/FTS FTS order set - com_fts + 19) COM/IDL E-idle order set - com_idl + 20) END/EDB symbol - end_edb + 21) STP/SDP symbol - stp_sdp + 22) COM/SKP SKP order set - com_skp + 23) Posted TLP Header credit value control - posted_tlp_hdr + 24) Non-Posted TLP Header credit value control - non_post_tlp_hdr + 25) Completion TLP Header credit value control - cmpl_tlp_hdr + 26) Posted TLP Data credit value control - posted_tlp_data + 27) Non-Posted TLP Data credit value control - non_post_tlp_data + 28) Completion TLP Data credit value control - cmpl_tlp_data + 29) Generates duplicate TLPs - duplicate_dllp + 30) Generates Nullified TLPs - nullified_tlp + + Each of the possible errors are WO attributes. Write to the attribute wi= ll + prepare controller to inject the respective error in the next transmissi= on + of data. Parameter required to write will change in the following ways: + + i) Errors 9) - 10) are sequence errors. The write command for these will= be + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/<= error> + + + Number of errors to be injected + + The difference to add or subtract from natural sequence number to + generate sequence error. Range (-4095 : 4095) + + ii) Errors 23) - 28) are credit value error insertions. Write command: + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_= inj/ + + + Number of errors to be injected + + The difference to add or subtract from UpdateFC credit value. + Range (-4095 : 4095) + + Target VC number + + iii) All other errors. Write command: + + echo > /sys/kernel/debug/dwc_pcie_/rasdes_err_inj/ + + + Number of errors to be injected diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index 907864c35ef3..801d51d8786f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -17,6 +17,20 @@ #define PIPE_DETECT_LANE BIT(17) #define LANE_SELECT GENMASK(3, 0) =20 +#define ERR_INJ0_OFF 0x34 +#define EINJ_VAL_DIFF GENMASK(28, 16) +#define EINJ_VC_NUM GENMASK(14, 12) +#define EINJ_TYPE_SHIFT 8 +#define EINJ0_TYPE GENMASK(11, 8) +#define EINJ1_TYPE BIT(8) +#define EINJ2_TYPE GENMASK(9, 8) +#define EINJ3_TYPE GENMASK(10, 8) +#define EINJ4_TYPE GENMASK(10, 8) +#define EINJ5_TYPE BIT(8) +#define EINJ_COUNT GENMASK(7, 0) + +#define ERR_INJ_ENABLE_REG 0x30 + #define DWC_DEBUGFS_BUF_MAX 128 =20 struct dwc_pcie_vendor_id { @@ -45,6 +59,72 @@ struct dwc_pcie_rasdes_info { struct dentry *rasdes_dir; }; =20 +/** + * struct dwc_pcie_rasdes_priv - Stores file specific private data informa= tion + * @pci: Reference to the dw_pcie structure + * @idx: Index to point to specific file related information in array of s= tructs + * + * All debugfs files will have this struct as its private data. + */ +struct dwc_pcie_rasdes_priv { + struct dw_pcie *pci; + int idx; +}; + +/** + * struct dwc_pcie_err_inj - Store details about each error injection supp= orted by DWC RASDES + * @name: Name of the error that can be injected + * @err_inj_group: Group number to which the error belongs to. Value can r= ange from 0 - 5 + * @err_inj_type: Each group can have multiple types of error + */ +struct dwc_pcie_err_inj { + const char *name; + u32 err_inj_group; + u32 err_inj_type; +}; + +static const struct dwc_pcie_err_inj err_inj_list[] =3D { + {"tx_lcrc", 0x0, 0x0}, + {"b16_crc_dllp", 0x0, 0x1}, + {"b16_crc_upd_fc", 0x0, 0x2}, + {"tx_ecrc", 0x0, 0x3}, + {"fcrc_tlp", 0x0, 0x4}, + {"parity_tsos", 0x0, 0x5}, + {"parity_skpos", 0x0, 0x6}, + {"rx_lcrc", 0x0, 0x8}, + {"rx_ecrc", 0x0, 0xb}, + {"tlp_err_seq", 0x1, 0x0}, + {"ack_nak_dllp_seq", 0x1, 0x1}, + {"ack_nak_dllp", 0x2, 0x0}, + {"upd_fc_dllp", 0x2, 0x1}, + {"nak_dllp", 0x2, 0x2}, + {"inv_sync_hdr_sym", 0x3, 0x0}, + {"com_pad_ts1", 0x3, 0x1}, + {"com_pad_ts2", 0x3, 0x2}, + {"com_fts", 0x3, 0x3}, + {"com_idl", 0x3, 0x4}, + {"end_edb", 0x3, 0x5}, + {"stp_sdp", 0x3, 0x6}, + {"com_skp", 0x3, 0x7}, + {"posted_tlp_hdr", 0x4, 0x0}, + {"non_post_tlp_hdr", 0x4, 0x1}, + {"cmpl_tlp_hdr", 0x4, 0x2}, + {"posted_tlp_data", 0x4, 0x4}, + {"non_post_tlp_data", 0x4, 0x5}, + {"cmpl_tlp_data", 0x4, 0x6}, + {"duplicate_dllp", 0x5, 0x0}, + {"nullified_tlp", 0x5, 0x1}, +}; + +static const u32 err_inj_type_mask[] =3D { + EINJ0_TYPE, + EINJ1_TYPE, + EINJ2_TYPE, + EINJ3_TYPE, + EINJ4_TYPE, + EINJ5_TYPE, +}; + static ssize_t lane_detect_read(struct file *file, char __user *buf, size_= t count, loff_t *ppos) { struct dw_pcie *pci =3D file->private_data; @@ -105,6 +185,63 @@ static ssize_t rx_valid_write(struct file *file, const= char __user *buf, size_t return lane_detect_write(file, buf, count, ppos); } =20 +static ssize_t err_inj_write(struct file *file, const char __user *buf, si= ze_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + u32 val, counter, vc_num, err_group, type_mask; + int val_diff =3D 0; + char *kern_buf; + + err_group =3D err_inj_list[pdata->idx].err_inj_group; + type_mask =3D err_inj_type_mask[err_group]; + + kern_buf =3D memdup_user_nul(buf, count); + if (IS_ERR(kern_buf)) + return PTR_ERR(kern_buf); + + if (err_group =3D=3D 4) { + val =3D sscanf(kern_buf, "%u %d %u", &counter, &val_diff, &vc_num); + if ((val !=3D 3) || (val_diff < -4095 || val_diff > 4095)) { + kfree(kern_buf); + return -EINVAL; + } + } else if (err_group =3D=3D 1) { + val =3D sscanf(kern_buf, "%u %d", &counter, &val_diff); + if ((val !=3D 2) || (val_diff < -4095 || val_diff > 4095)) { + kfree(kern_buf); + return -EINVAL; + } + } else { + val =3D kstrtou32(kern_buf, 0, &counter); + if (val) { + kfree(kern_buf); + return val; + } + } + + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x= 4 * err_group)); + val &=3D ~(type_mask | EINJ_COUNT); + val |=3D ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & ty= pe_mask); + val |=3D FIELD_PREP(EINJ_COUNT, counter); + + if (err_group =3D=3D 1 || err_group =3D=3D 4) { + val &=3D ~(EINJ_VAL_DIFF); + val |=3D FIELD_PREP(EINJ_VAL_DIFF, val_diff); + } + if (err_group =3D=3D 4) { + val &=3D ~(EINJ_VC_NUM); + val |=3D FIELD_PREP(EINJ_VC_NUM, vc_num); + } + + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err= _group), val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 = << err_group)); + + kfree(kern_buf); + return count; +} + #define dwc_debugfs_create(name) \ debugfs_create_file(#name, 0644, rasdes_debug, pci, \ &dbg_ ## name ## _fops) @@ -119,6 +256,11 @@ static const struct file_operations dbg_ ## name ## _f= ops =3D { \ DWC_DEBUGFS_FOPS(lane_detect); DWC_DEBUGFS_FOPS(rx_valid); =20 +static const struct file_operations dwc_pcie_err_inj_ops =3D { + .open =3D simple_open, + .write =3D err_inj_write, +}; + void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) { struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; @@ -129,12 +271,13 @@ void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *p= ci) =20 int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) { - struct dentry *dir, *rasdes_debug; + struct dentry *dir, *rasdes_debug, *rasdes_err_inj; struct dwc_pcie_rasdes_info *rasdes_info; + struct dwc_pcie_rasdes_priv *priv_tmp; const struct dwc_pcie_vendor_id *vid; char dirname[DWC_DEBUGFS_BUF_MAX]; struct device *dev =3D pci->dev; - int ras_cap; + int ras_cap, i, ret; =20 for (vid =3D dwc_pcie_vendor_ids; vid->vendor_id; vid++) { ras_cap =3D dw_pcie_find_vsec_capability(pci, vid->vendor_id, @@ -159,6 +302,7 @@ int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) =20 /* Create subdirectories for Debug, Error injection, Statistics */ rasdes_debug =3D debugfs_create_dir("rasdes_debug", dir); + rasdes_err_inj =3D debugfs_create_dir("rasdes_err_inj", dir); =20 mutex_init(&rasdes_info->reg_lock); rasdes_info->ras_cap_offset =3D ras_cap; @@ -169,5 +313,22 @@ int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) dwc_debugfs_create(lane_detect); dwc_debugfs_create(rx_valid); =20 + /* Create debugfs files for Error injection subdirectory */ + for (i =3D 0; i < ARRAY_SIZE(err_inj_list); i++) { + priv_tmp =3D devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) { + ret =3D -ENOMEM; + goto err_deinit; + } + + priv_tmp->idx =3D i; + priv_tmp->pci =3D pci; + debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp, + &dwc_pcie_err_inj_ops); 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Tue, 21 Jan 2025 11:52:13 +0000 (GMT) Received: from epsmgms1p2new.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250121115213epsmtrp1b14c75c5157af5c74474e89896e13da6~csvfXasw_0976909769epsmtrp1j; Tue, 21 Jan 2025 11:52:13 +0000 (GMT) X-AuditID: b6c32a49-3d20270000004e54-57-678f8f9c64a4 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 8B.BB.18949.D6A8F876; Tue, 21 Jan 2025 20:52:13 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.109.115.6]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250121115211epsmtip19f988ed6d8c1f80c8391dba98cdd45a1~csvdIKuRU1750517505epsmtip1D; Tue, 21 Jan 2025 11:52:11 +0000 (GMT) From: Shradha Todi To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, Jonathan.Cameron@Huawei.com, fan.ni@samsung.com, a.manzanares@samsung.com, pankaj.dubey@samsung.com, quic_nitegupt@quicinc.com, quic_krichai@quicinc.com, gost.dev@samsung.com, Shradha Todi Subject: [PATCH v5 4/4] Add debugfs based statistical counter support in DWC Date: Tue, 21 Jan 2025 16:44:21 +0530 Message-Id: <20250121111421.35437-5-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250121111421.35437-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFJsWRmVeSWpSXmKPExsWy7bCmhu6c/v50g8VfeS2mH1a0WNKUYdG0 +i6rxc0DO5ksVnyZyW6xauE1NouGnt+sFpd3zWGzODvvOJtFy58WFou7LZ2sFou2fmG3ePCg 0qJzzhFmi/97drBb9B6udRDw2DnrLrvHgk2lHi1H3rJ6bFrVyeZx59oeNo8nV6YzeUzcU+fR t2UVo8fnTXIBnFHZNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+ AbpumTlAHygplCXmlAKFAhKLi5X07WyK8ktLUhUy8otLbJVSC1JyCkwK9IoTc4tL89L18lJL rAwNDIxMgQoTsjPerpvGXjAvvWLvGb0Gxj1hXYycHBICJhL/1u1h7WLk4hAS2M0o0dh8HMr5 xCjx9e8UdgjnG6PE0dsdQA4HWMurJUkQ8b2MEhOmHIYqamaSaD73jhVkLpuAlkTj1y5mEFtE wFricPsWNpAiZoGnTBKtx3+ygSSEBXwk1k/dxQ5iswioSqxvOwjWzCtgJXG59zELxIHyEqs3 HAAbxAk06M2RO2D3SQgs5JB4duEQM8RJLhI7z8dD1AtLvDq+hR3ClpJ42d8GZadLrNw8gxnC zpH4tnkJE4RtL3HgyhwWkDHMApoS63fpQ4RlJaaeWgdWwizAJ9H7+wlUOa/EjnkwtrLEl797 oM6UlJh37DIrhO0h8ff5J2ZIoPQxSmy68pRxAqPcLIQVCxgZVzFKphYU56anFpsWGOallsMj LTk/dxMjOJFqee5gvPvgg94hRiYOxkOMEhzMSiK8oh960oV4UxIrq1KL8uOLSnNSiw8xmgLD byKzlGhyPjCV55XEG5pYGpiYmZmZWBqbGSqJ8zbvbEkXEkhPLEnNTk0tSC2C6WPi4JRqYEr+ X2XbtOXSfffZc7aqyfrIx52ofTNl9coJe4SeXQ2Icv0zVc6ffc7Xid7CHcsCbZ98z3R4p/t7 8fK4o/s0ziYI3UtZsUTXo+OXxuZ1JVIxmc/+ML4rcVGPeF6z10LeLFc+IHipvLmP6/m9yyqE nt0tjfwzocddtuLWc4vLBo1J+o8rvuTWfD32LGTV/N2XjTTqWieLcc8+PcmssV/q7o8g1sDw 3zv2O70sTFNNPfS7puLxZ+bfpfeE2Fa9bm78IPxR+8/zhybxQkvFN/A0+Fcb8d38uf3NTp0/ fopVu2yavhz92f/kcsuUuH/HdTgVZonkrF7fELuJ7QmPj4fi9E1P+f4/9mAS3THt8YI/dbZK LMUZiYZazEXFiQCdZwjULQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsWy7bCSnG5uV3+6wYKLqhbTDytaLGnKsGha fZfV4uaBnUwWK77MZLdYtfAam0VDz29Wi8u75rBZnJ13nM2i5U8Li8Xdlk5Wi0Vbv7BbPHhQ adE55wizxf89O9gteg/XOgh47Jx1l91jwaZSj5Yjb1k9Nq3qZPO4c20Pm8eTK9OZPCbuqfPo 27KK0ePzJrkAzigum5TUnMyy1CJ9uwSujLfrprEXzEuv2HtGr4FxT1gXIweHhICJxKslSV2M XBxCArsZJRa8fMPaxcgJFJeU+HxxHROELSyx8t9zdoiiRiaJjatusYEk2AS0JBq/djGD2CIC thL3H01mBSliFvjKJPHx0w2whLCAj8T6qbvYQWwWAVWJ9W0HwTbwClhJXO59zAKxQV5i9YYD YPWcAtYSb47cAasRAqqZvf0U6wRGvgWMDKsYJVMLinPTc4sNC4zyUsv1ihNzi0vz0vWS83M3 MYJDXUtrB+OeVR/0DjEycTAeYpTgYFYS4RX90JMuxJuSWFmVWpQfX1Sak1p8iFGag0VJnPfb 694UIYH0xJLU7NTUgtQimCwTB6dUAxOffPeT58/Vvt8sLtogq5PH+0VoRWzw748P7Rs+NH0W WhBTulXPYN2qW9ILPn6UNDSNvvku4KDby4CFvLlWNjcMFjys2PLhy+Q93x/PmDVPY8WS55oL GfNvx0WeeLzMcJ7RlCDHuhtTwz/NCaoLKV0d6bY9Y9K1LUyiD+7WLPlap3GY+Zq86uvSYM1H n74GOknOXFV1To6hReHPtcR88/RnJ1TEVzXVRohOmCMtrjPT7dH8m/rJsxpTl0ot4NZSnbp0 b8Xa1eHyZ82dH526qb1mr4evcPrnWu+N0S8FpP9IrZa2d5n6d6LkrAcfjuoGKWxdGPvzWEzK 6oRFualGKUzsEzlKFnAUhi76dUomrfaBEktxRqKhFnNRcSIANbBp9eQCAAA= X-CMS-MailID: 20250121115213epcas5p14d712e58b5bf6505b0bd729fb33b25b8 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250121115213epcas5p14d712e58b5bf6505b0bd729fb33b25b8 References: <20250121111421.35437-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Add support to provide statistical counter interface to userspace. This set of debug registers are part of the RASDES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi --- Documentation/ABI/testing/debugfs-dwc-pcie | 61 +++++ .../controller/dwc/pcie-designware-debugfs.c | 229 +++++++++++++++++- 2 files changed, 289 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/debugfs-dwc-pcie b/Documentation/ABI= /testing/debugfs-dwc-pcie index cff205ab2678..d3f84f46b400 100644 --- a/Documentation/ABI/testing/debugfs-dwc-pcie +++ b/Documentation/ABI/testing/debugfs-dwc-pcie @@ -81,3 +81,64 @@ Description: rasdes_err_inj is the directory which can b= e used to inject errors =20 Number of errors to be injected + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//coun= ter_enable +Date: January 2025 +Contact: Shradha Todi +Description: rasdes_event_counters is the directory which can be used to c= ollect + statistical data about the number of times a certain event has occurred + in the controller. The list of possible events are: + + 1) EBUF Overflow + 2) EBUF Underrun + 3) Decode Error + 4) Running Disparity Error + 5) SKP OS Parity Error + 6) SYNC Header Error + 7) Rx Valid De-assertion + 8) CTL SKP OS Parity Error + 9) 1st Retimer Parity Error + 10) 2nd Retimer Parity Error + 11) Margin CRC and Parity Error + 12) Detect EI Infer + 13) Receiver Error + 14) RX Recovery Req + 15) N_FTS Timeout + 16) Framing Error + 17) Deskew Error + 18) Framing Error In L0 + 19) Deskew Uncompleted Error + 20) Bad TLP + 21) LCRC Error + 22) Bad DLLP + 23) Replay Number Rollover + 24) Replay Timeout + 25) Rx Nak DLLP + 26) Tx Nak DLLP + 27) Retry TLP + 28) FC Timeout + 29) Poisoned TLP + 30) ECRC Error + 31) Unsupported Request + 32) Completer Abort + 33) Completion Timeout + 34) EBUF SKP Add + 35) EBUF SKP Del + + counter_enable is RW. Write 1 to enable the event counter and write 0 to + disable the event counter. Read will return whether the counter is curre= ntly + enabled or disabled. Counter is disabled by default. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//coun= ter_value +Date: January 2025 +Contact: Shradha Todi +Description: (RO) Read will return the current value of the event counter.= To reset the counter, + counter should be disabled and enabled back using the 'counter_enable' a= ttribute. + +What: /sys/kernel/debug/dwc_pcie_/rasdes_event_counters//lane= _select +Date: January 2025 +Contact: Shradha Todi +Description: (RW) Some lanes in the event list are lane specific events. T= hese include + events 1) - 11) and 34) - 35). + Write lane number for which counter needs to be enabled/disabled/dumped. + Read will return the current selected lane number. Lane0 is selected by = default. diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers= /pci/controller/dwc/pcie-designware-debugfs.c index 801d51d8786f..5d883b13be84 100644 --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -31,6 +31,17 @@ =20 #define ERR_INJ_ENABLE_REG 0x30 =20 +#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc + +#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 +#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24) +#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16) +#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8) +#define EVENT_COUNTER_STATUS BIT(7) +#define EVENT_COUNTER_ENABLE GENMASK(4, 2) +#define PER_EVENT_ON 0x3 +#define PER_EVENT_OFF 0x1 + #define DWC_DEBUGFS_BUF_MAX 128 =20 struct dwc_pcie_vendor_id { @@ -125,6 +136,61 @@ static const u32 err_inj_type_mask[] =3D { EINJ5_TYPE, }; =20 +/** + * struct dwc_pcie_event_counter - Store details about each event counter = supported in DWC RASDES + * @name: Name of the error counter + * @group_no: Group number that the event belongs to. Value ranges from 0 = - 4 + * @event_no: Event number of the particular event. Value ranges from - + * Group 0: 0 - 10 + * Group 1: 5 - 13 + * Group 2: 0 - 7 + * Group 3: 0 - 5 + * Group 4: 0 - 1 + */ +struct dwc_pcie_event_counter { + const char *name; + u32 group_no; + u32 event_no; +}; + +static const struct dwc_pcie_event_counter event_list[] =3D { + {"ebuf_overflow", 0x0, 0x0}, + {"ebuf_underrun", 0x0, 0x1}, + {"decode_err", 0x0, 0x2}, + {"running_disparity_err", 0x0, 0x3}, + {"skp_os_parity_err", 0x0, 0x4}, + {"sync_header_err", 0x0, 0x5}, + {"rx_valid_deassertion", 0x0, 0x6}, + {"ctl_skp_os_parity_err", 0x0, 0x7}, + {"retimer_parity_err_1st", 0x0, 0x8}, + {"retimer_parity_err_2nd", 0x0, 0x9}, + {"margin_crc_parity_err", 0x0, 0xA}, + {"detect_ei_infer", 0x1, 0x5}, + {"receiver_err", 0x1, 0x6}, + {"rx_recovery_req", 0x1, 0x7}, + {"n_fts_timeout", 0x1, 0x8}, + {"framing_err", 0x1, 0x9}, + {"deskew_err", 0x1, 0xa}, + {"framing_err_in_l0", 0x1, 0xc}, + {"deskew_uncompleted_err", 0x1, 0xd}, + {"bad_tlp", 0x2, 0x0}, + {"lcrc_err", 0x2, 0x1}, + {"bad_dllp", 0x2, 0x2}, + {"replay_num_rollover", 0x2, 0x3}, + {"replay_timeout", 0x2, 0x4}, + {"rx_nak_dllp", 0x2, 0x5}, + {"tx_nak_dllp", 0x2, 0x6}, + {"retry_tlp", 0x2, 0x7}, + {"fc_timeout", 0x3, 0x0}, + {"poisoned_tlp", 0x3, 0x1}, + {"ecrc_error", 0x3, 0x2}, + {"unsupported_request", 0x3, 0x3}, + {"completer_abort", 0x3, 0x4}, + {"completion_timeout", 0x3, 0x5}, + {"ebuf_skp_add", 0x4, 0x0}, + {"ebuf_skp_del", 0x4, 0x1}, +}; + static ssize_t lane_detect_read(struct file *file, char __user *buf, size_= t count, loff_t *ppos) { struct dw_pcie *pci =3D file->private_data; @@ -242,6 +308,127 @@ static ssize_t err_inj_write(struct file *file, const= char __user *buf, size_t c return count; } =20 +static void set_event_number(struct dwc_pcie_rasdes_priv *pdata, struct dw= _pcie *pci, + struct dwc_pcie_rasdes_info *rinfo) +{ + u32 val; + + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val &=3D ~EVENT_COUNTER_ENABLE; + val &=3D ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT); + val |=3D FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].gr= oup_no); + val |=3D FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].ev= ent_no); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); +} + +static ssize_t counter_enable_read(struct file *file, char __user *buf, si= ze_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t off =3D 0; + u32 val; + + mutex_lock(&rinfo->reg_lock); + set_event_number(pdata, pci, rinfo); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + mutex_unlock(&rinfo->reg_lock); + val =3D FIELD_GET(EVENT_COUNTER_STATUS, val); + if (val) + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Counter Enab= led\n"); + else + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Counter Disa= bled\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t counter_enable_write(struct file *file, const char __user *= buf, + size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + u32 val, enable; + + val =3D kstrtou32_from_user(buf, count, 0, &enable); + if (val) + return val; + + mutex_lock(&rinfo->reg_lock); + set_event_number(pdata, pci, rinfo); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + if (enable) + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON); + else + val |=3D FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF); + + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + mutex_unlock(&rinfo->reg_lock); + + return count; +} + +static ssize_t counter_lane_read(struct file *file, char __user *buf, size= _t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t off =3D 0; + u32 val; + + mutex_lock(&rinfo->reg_lock); + set_event_number(pdata, pci, rinfo); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + mutex_unlock(&rinfo->reg_lock); + val =3D FIELD_GET(EVENT_COUNTER_LANE_SELECT, val); + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Lane: %d\n", = val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t counter_lane_write(struct file *file, const char __user *bu= f, + size_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + u32 val, lane; + + val =3D kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + mutex_lock(&rinfo->reg_lock); + set_event_number(pdata, pci, rinfo); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_CTRL_REG); + val &=3D ~(EVENT_COUNTER_LANE_SELECT); + val |=3D FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane); + dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTR= L_REG, val); + mutex_unlock(&rinfo->reg_lock); + + return count; +} + +static ssize_t counter_value_read(struct file *file, char __user *buf, siz= e_t count, loff_t *ppos) +{ + struct dwc_pcie_rasdes_priv *pdata =3D file->private_data; + struct dw_pcie *pci =3D pdata->pci; + struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; + char debugfs_buf[DWC_DEBUGFS_BUF_MAX]; + ssize_t off =3D 0; + u32 val; + + mutex_lock(&rinfo->reg_lock); + set_event_number(pdata, pci, rinfo); + val =3D dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUN= TER_DATA_REG); + mutex_unlock(&rinfo->reg_lock); + off +=3D scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX - off, "Counter value= : %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + #define dwc_debugfs_create(name) \ debugfs_create_file(#name, 0644, rasdes_debug, pci, \ &dbg_ ## name ## _fops) @@ -261,6 +448,23 @@ static const struct file_operations dwc_pcie_err_inj_o= ps =3D { .write =3D err_inj_write, }; =20 +static const struct file_operations dwc_pcie_counter_enable_ops =3D { + .open =3D simple_open, + .read =3D counter_enable_read, + .write =3D counter_enable_write, +}; + +static const struct file_operations dwc_pcie_counter_lane_ops =3D { + .open =3D simple_open, + .read =3D counter_lane_read, + .write =3D counter_lane_write, +}; + +static const struct file_operations dwc_pcie_counter_value_ops =3D { + .open =3D simple_open, + .read =3D counter_value_read, +}; + void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) { struct dwc_pcie_rasdes_info *rinfo =3D pci->rasdes_info; @@ -271,7 +475,7 @@ void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) =20 int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) { - struct dentry *dir, *rasdes_debug, *rasdes_err_inj; + struct dentry *dir, *rasdes_debug, *rasdes_err_inj, *rasdes_event_counter= , *rasdes_events; struct dwc_pcie_rasdes_info *rasdes_info; struct dwc_pcie_rasdes_priv *priv_tmp; const struct dwc_pcie_vendor_id *vid; @@ -303,6 +507,7 @@ int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) /* Create subdirectories for Debug, Error injection, Statistics */ rasdes_debug =3D debugfs_create_dir("rasdes_debug", dir); rasdes_err_inj =3D debugfs_create_dir("rasdes_err_inj", dir); + rasdes_event_counter =3D debugfs_create_dir("rasdes_event_counter", dir); =20 mutex_init(&rasdes_info->reg_lock); rasdes_info->ras_cap_offset =3D ras_cap; @@ -326,6 +531,28 @@ int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp, &dwc_pcie_err_inj_ops); } + + /* Create debugfs files for Statistical counter subdirectory */ + for (i =3D 0; i < ARRAY_SIZE(event_list); i++) { + priv_tmp =3D devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) { + ret =3D -ENOMEM; + goto err_deinit; + } + + priv_tmp->idx =3D i; + priv_tmp->pci =3D pci; + rasdes_events =3D debugfs_create_dir(event_list[i].name, rasdes_event_co= unter); + if (event_list[i].group_no =3D=3D 0 || event_list[i].group_no =3D=3D 4) { + debugfs_create_file("lane_select", 0644, rasdes_events, + priv_tmp, &dwc_pcie_counter_lane_ops); + } + debugfs_create_file("counter_value", 0444, rasdes_events, priv_tmp, + &dwc_pcie_counter_value_ops); + debugfs_create_file("counter_enable", 0644, rasdes_events, priv_tmp, + &dwc_pcie_counter_enable_ops); + } + return 0; =20 err_deinit: --=20 2.17.1