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([78.9.4.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db8942cad4sm5681726a12.60.2025.01.21.01.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 01:23:14 -0800 (PST) From: Lukasz Czechowski To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quentin.schulz@cherry.de, Lukasz Czechowski Subject: [PATCH 1/2] arm64: dts: rockchip: Move uart5 pin configuration to SoM dtsi Date: Tue, 21 Jan 2025 10:22:54 +0100 Message-ID: <20250121092255.3108495-2-lukasz.czechowski@thaumatec.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250121092255.3108495-1-lukasz.czechowski@thaumatec.com> References: <20250121092255.3108495-1-lukasz.czechowski@thaumatec.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for uart5 cannot be used for the UART CTS/RTS, because they are already allocated for different purposes. CTS pin is routed to SUS_S3# signal, while RTS pin is used internally and is not available on Q7 connector. Move definition of the pinctrl-0 property from px30-ringneck-haikou.dts to px30-ringneck.dtsi. Signed-off-by: Lukasz Czechowski Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 - arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/a= rm64/boot/dts/rockchip/px30-ringneck-haikou.dts index e4517f47d519c..eb9470a00e549 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -226,7 +226,6 @@ &uart0 { }; =20 &uart5 { - pinctrl-0 =3D <&uart5_xfer>; rts-gpios =3D <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index ae050cc6cd050..2c87005c89bd3 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -396,6 +396,10 @@ &u2phy_host { status =3D "okay"; }; =20 +&uart5 { + pinctrl-0 =3D <&uart5_xfer>; +}; + /* Mule UCAN */ &usb_host0_ehci { status =3D "okay"; --=20 2.43.0 From nobody Mon Feb 9 07:45:33 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 310E41BD519 for ; Tue, 21 Jan 2025 09:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737451402; cv=none; b=r9jAXpOvas4dxcomCQKDSlJ05jrd6nCAbt74FL8/drYRWLXjgub/QrVZnMzLYPntfzCGvlfWAnDgptG+ikBhJu6mtDqAHVZLOGz4jvJaKPYleW7MEU3Mo6w6OmiDktbxIiKUJT8AZBy0bxwuosziHyanuiyiOI5t3fEQP3YNKQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737451402; c=relaxed/simple; bh=GMSiog3xbKrlA5a5KWFlrnu5Cgk8TZeql687hUdoP6w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X1Xm1NVXr6maVB+p4NapSTx1Rmff2B+dA8N+MdPIJ+/+URsVYpgCdHy9gh3uJOZdymCbxAc3ZdCy1xdKqQp/xv9z569v21wGrqa+pj++dzLNeaoiCovc6tKeJA/5GR/TiC7/VgH0dFaldNhU3OLBhLR5nPGfsdMxUN7mDMeQK0c= ARC-Authentication-Results: i=1; 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([78.9.4.190]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db8942cad4sm5681726a12.60.2025.01.21.01.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jan 2025 01:23:18 -0800 (PST) From: Lukasz Czechowski To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quentin.schulz@cherry.de, Lukasz Czechowski Subject: [PATCH 2/2] arm64: dts: rockchip: Disable DMA for uart5 on px30-ringneck Date: Tue, 21 Jan 2025 10:22:55 +0100 Message-ID: <20250121092255.3108495-3-lukasz.czechowski@thaumatec.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250121092255.3108495-1-lukasz.czechowski@thaumatec.com> References: <20250121092255.3108495-1-lukasz.czechowski@thaumatec.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" UART controllers without flow control seem to behave unstable in case DMA is enabled. The issues were indicated in the message: https://lore.kernel.org/linux-arm-kernel/CAMdYzYpXtMocCtCpZLU_xuWmOp2Ja_v0A= j0e6YFNRA-yV7u14g@mail.gmail.com/ In case of PX30-uQ7 Ringneck SoM, it was noticed that after couple of hours of UART communication, the CPU stall was occurring, leading to the system becoming unresponsive. After disabling the DMA, extensive UART communication tests for up to two weeks were performed, and no issues were further observed. The flow control pins for uart5 are not available on PX30-uQ7 Ringneck, as configured by pinctrl-0, so the DMA nodes were removed on SoM dtsi. Signed-off-by: Lukasz Czechowski Reviewed-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index 2c87005c89bd3..e80412abec081 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -397,6 +397,8 @@ &u2phy_host { }; =20 &uart5 { + /delete-property/ dmas; + /delete-property/ dma-names; pinctrl-0 =3D <&uart5_xfer>; }; =20 --=20 2.43.0