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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:40:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Date: Sat, 18 Jan 2025 13:39:44 +0100 Message-ID: <20250118124044.157308-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MM_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mm-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 1f768b2eeb1a..102d8a6cdb55 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -16,7 +16,8 @@ #define IMX8MM_CLK_EXT4 7 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 -#define IMX8MM_VIDEO_PLL1_REF_SEL 10 +#define IMX8MM_VIDEO_PLL_REF_SEL 10 +#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL #define IMX8MM_DRAM_PLL_REF_SEL 11 #define IMX8MM_GPU_PLL_REF_SEL 12 #define IMX8MM_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MM_SYS_PLL3_REF_SEL 17 #define IMX8MM_AUDIO_PLL1 18 #define IMX8MM_AUDIO_PLL2 19 -#define IMX8MM_VIDEO_PLL1 20 +#define IMX8MM_VIDEO_PLL 20 +#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL #define IMX8MM_DRAM_PLL 21 #define IMX8MM_GPU_PLL 22 #define IMX8MM_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MM_SYS_PLL3 27 #define IMX8MM_AUDIO_PLL1_BYPASS 28 #define IMX8MM_AUDIO_PLL2_BYPASS 29 -#define IMX8MM_VIDEO_PLL1_BYPASS 30 +#define IMX8MM_VIDEO_PLL_BYPASS 30 +#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS #define IMX8MM_DRAM_PLL_BYPASS 31 #define IMX8MM_GPU_PLL_BYPASS 32 #define IMX8MM_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MM_SYS_PLL3_BYPASS 37 #define IMX8MM_AUDIO_PLL1_OUT 38 #define IMX8MM_AUDIO_PLL2_OUT 39 -#define IMX8MM_VIDEO_PLL1_OUT 40 +#define IMX8MM_VIDEO_PLL_OUT 40 +#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT #define IMX8MM_DRAM_PLL_OUT 41 #define IMX8MM_GPU_PLL_OUT 42 #define IMX8MM_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B29E188580 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:40:56 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 02/23] clk: imx8mm: rename video_pll1 to video_pll Date: Sat, 18 Jan 2025 13:39:45 +0100 Message-ID: <20250118124044.157308-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. (no changes since v7) Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++++++++------------------ 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..8a1fc7e17ba2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -28,7 +28,7 @@ static u32 share_count_nand; static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "dumm= y", }; static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pll1= _ref_sel", }; static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pll2= _ref_sel", }; -static const char *video_pll1_bypass_sels[] =3D {"video_pll1", "video_pll1= _ref_sel", }; +static const char *video_pll_bypass_sels[] =3D {"video_pll", "video_pll_re= f_sel", }; static const char *dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pll_ref_s= el", }; static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; @@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] =3D {"osc_24m", "a= rm_pll_out", "sys_pll2_500m static const char * const imx8mm_a53_core_sels[] =3D {"arm_a53_div", "arm_= pll_out", }; =20 static const char *imx8mm_m4_sels[] =3D {"osc_24m", "sys_pll2_200m", "sys_= pll2_250m", "sys_pll1_266m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_= out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_o= ut", }; =20 static const char *imx8mm_vpu_sels[] =3D {"osc_24m", "arm_pll_out", "sys_p= ll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", }; =20 static const char *imx8mm_gpu3d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out", "sys= _pll1_800m", "sys_pll3_out", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_o= ut", }; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_ou= t", }; =20 static const char *imx8mm_main_axi_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_= 100m",}; + "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_1= 00m",}; =20 static const char *imx8mm_enet_axi_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll1_800m", "sys_pll2_250m", - "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_o= ut", }; + "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_ou= t", }; =20 static const char *imx8mm_nand_usdhc_sels[] =3D {"osc_24m", "sys_pll1_266m= ", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_= out", }; @@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] =3D {"osc_24m= ", "sys_pll2_125m", "sys_pl "sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; =20 static const char *imx8mm_disp_rtrm_sels[] =3D {"osc_24m", "sys_pll1_800m"= , "sys_pll2_200m", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", }; + "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", }; =20 static const char *imx8mm_usb_bus_sels[] =3D {"osc_24m", "sys_pll2_500m", = "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_800m", = "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_sels[] =3D {"osc_24m", "sys_pll1_800m", "sys= _pll3_out", "sys_pll2_1000m", "sys_pll2_500m", - "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; + "audio_pll1_out", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_noc_apb_sels[] =3D {"osc_24m", "sys_pll1_400m", = "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m", - "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", }; + "sys_pll1_800m", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m", "sys= _pll1_800m", "sys_pll1_400m", - "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", = }; + "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; =20 static const char *imx8mm_audio_ahb_sels[] =3D {"osc_24m", "sys_pll2_500m"= , "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_= out", }; + "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dram_alt_sels[] =3D {"osc_24m", "sys_pll1_800m",= "sys_pll1_100m", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_26= 6m", }; @@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] =3D {"osc_24m= ", "vpu_pll_out", "sys_pll1_8 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out"= , }; =20 static const char *imx8mm_disp_dtrc_sels[] =3D {"osc_24m", "dummy", "sys_p= ll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_= out", }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_o= ut", }; =20 static const char *imx8mm_disp_dc8000_sels[] =3D {"osc_24m", "dummy", "sys= _pll1_800m", "sys_pll2_1000m", - "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out",= }; + "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", = }; =20 static const char *imx8mm_pcie1_ctrl_sels[] =3D {"osc_24m", "sys_pll2_250m= ", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_o= ut", }; @@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] =3D {"osc_= 24m", "sys_pll2_100m", "sys_p static const char *imx8mm_pcie1_aux_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_50m", "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200= m", }; =20 -static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll1_out"= , "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_dc_pixel_sels[] =3D {"osc_24m", "video_pll_out",= "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll1_o= ut", "audio_pll2_out", "audio_pll1_out", +static const char *imx8mm_lcdif_pixel_sels[] =3D {"osc_24m", "video_pll_ou= t", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 -static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai1_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai2_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai3_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai4_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 -static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai5_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll1_out", +static const char *imx8mm_sai6_sels[] =3D {"osc_24m", "audio_pll1_out", "a= udio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 -static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif1_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 -static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll1_out", +static const char *imx8mm_spdif2_sels[] =3D {"osc_24m", "audio_pll1_out", = "audio_pll2_out", "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char *imx8mm_enet_ref_sels[] =3D {"osc_24m", "sys_pll2_125m",= "sys_pll2_50m", "sys_pll2_100m", - "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4",= }; + "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", = }; =20 static const char *imx8mm_enet_timer_sels[] =3D {"osc_24m", "sys_pll2_100m= ", "audio_pll1_out", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4", "video_pll1_out", }; + "clk_ext3", "clk_ext4", "video_pll_out", }; =20 static const char *imx8mm_enet_phy_sels[] =3D {"osc_24m", "sys_pll2_50m", = "sys_pll2_125m", "sys_pll2_200m", - "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; + "sys_pll2_500m", "video_pll_out", "audio_pll2_out", }; =20 static const char *imx8mm_nand_sels[] =3D {"osc_24m", "sys_pll2_500m", "au= dio_pll1_out", "sys_pll1_400m", - "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out",= }; + "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", = }; =20 static const char *imx8mm_qspi_sels[] =3D {"osc_24m", "sys_pll1_400m", "sy= s_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", = }; @@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] =3D {"osc_24m= ", "sys_pll1_400m", "sys_pll1 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160m", "sy= s_pll2_50m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; + "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char *imx8mm_uart1_sels[] =3D {"osc_24m", "sys_pll1_80m", "sy= s_pll2_200m", "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; @@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] =3D {"osc_24m= ", "sys_pll2_200m", "sys_pll1 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out"= , }; =20 static const char *imx8mm_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_160m", "sys_pll1_40m", - "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; =20 static const char *imx8mm_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100m", "sy= s_pll1_400m", "sys_pll1_40m", - "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; + "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char *imx8mm_wdog_sels[] =3D {"osc_24m", "sys_pll1_133m", "sy= s_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] =3D {"osc_24m"= , "sys_pll1_40m", "vpu_pll_ou "sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", }; =20 static const char *imx8mm_dsi_core_sels[] =3D {"osc_24m", "sys_pll1_266m",= "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_= out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_o= ut", }; =20 static const char *imx8mm_dsi_phy_sels[] =3D {"osc_24m", "sys_pll2_125m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out",= }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", = }; =20 static const char *imx8mm_dsi_dbi_sels[] =3D {"osc_24m", "sys_pll1_266m", = "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_o= ut", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_ou= t", }; =20 static const char *imx8mm_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_400m", "= sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m"= , }; =20 static const char *imx8mm_csi1_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi1_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi1_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; =20 static const char *imx8mm_csi2_core_sels[] =3D {"osc_24m", "sys_pll1_266m"= , "sys_pll2_250m", "sys_pll1_800m", - "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1= _out", }; + "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_= out", }; =20 static const char *imx8mm_csi2_phy_sels[] =3D {"osc_24m", "sys_pll2_333m",= "sys_pll2_100m", "sys_pll1_800m", - "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out"= , }; + "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out",= }; =20 static const char *imx8mm_csi2_esc_sels[] =3D {"osc_24m", "sys_pll2_100m",= "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", = }; @@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] =3D {"dram_p= ll_out", "dram_alt_root", } static const char *imx8mm_clko1_sels[] =3D {"osc_24m", "sys_pll1_800m", "d= ummy", "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", }; static const char *imx8mm_clko2_sels[] =3D {"osc_24m", "sys_pll2_200m", "s= ys_pll1_400m", "sys_pll2_166m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll1_out", +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); + hws[IMX8MM_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); @@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL bypass out */ hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); @@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) /* PLL out gate */ hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); + hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 728A0194A65 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:40:59 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Date: Sat, 18 Jan 2025 13:39:46 +0100 Message-ID: <20250118124044.157308-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's add the IMX8MP_VIDEO_PLL[_*] definitions to be consistent with the RM and avoid misunderstandings. The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure backward compatibility of the patch. No functional changes intended. Signed-off-by: Dario Binacchi Acked-by: Krzysztof Kozlowski --- (no changes since v6) Changes in v6: - Add 'Acked-by' tag of Krzysztof Kozlowski Changes in v5: - New include/dt-bindings/clock/imx8mp-clock.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 7da4243984b2..3235d7de3b62 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -16,7 +16,8 @@ #define IMX8MP_CLK_EXT4 7 #define IMX8MP_AUDIO_PLL1_REF_SEL 8 #define IMX8MP_AUDIO_PLL2_REF_SEL 9 -#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_VIDEO_PLL_REF_SEL 10 +#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL #define IMX8MP_DRAM_PLL_REF_SEL 11 #define IMX8MP_GPU_PLL_REF_SEL 12 #define IMX8MP_VPU_PLL_REF_SEL 13 @@ -26,7 +27,8 @@ #define IMX8MP_SYS_PLL3_REF_SEL 17 #define IMX8MP_AUDIO_PLL1 18 #define IMX8MP_AUDIO_PLL2 19 -#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_VIDEO_PLL 20 +#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL #define IMX8MP_DRAM_PLL 21 #define IMX8MP_GPU_PLL 22 #define IMX8MP_VPU_PLL 23 @@ -36,7 +38,8 @@ #define IMX8MP_SYS_PLL3 27 #define IMX8MP_AUDIO_PLL1_BYPASS 28 #define IMX8MP_AUDIO_PLL2_BYPASS 29 -#define IMX8MP_VIDEO_PLL1_BYPASS 30 +#define IMX8MP_VIDEO_PLL_BYPASS 30 +#define IMX8MP_VIDEO_PLL1_BYPASS IMX8MP_VIDEO_PLL_BYPASS #define IMX8MP_DRAM_PLL_BYPASS 31 #define IMX8MP_GPU_PLL_BYPASS 32 #define IMX8MP_VPU_PLL_BYPASS 33 @@ -46,7 +49,8 @@ #define IMX8MP_SYS_PLL3_BYPASS 37 #define IMX8MP_AUDIO_PLL1_OUT 38 #define IMX8MP_AUDIO_PLL2_OUT 39 -#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_VIDEO_PLL_OUT 40 +#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT #define IMX8MP_DRAM_PLL_OUT 41 #define IMX8MP_GPU_PLL_OUT 42 #define IMX8MP_VPU_PLL_OUT 43 --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E93A1198E77 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 04/23] clk: imx8mp: rename video_pll1 to video_pll Date: Sat, 18 Jan 2025 13:39:47 +0100 Message-ID: <20250118124044.157308-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the name used in the RM is video_pll. So, let's rename "video_pll1" to "video_pll" to be consistent with the RM and avoid misunderstandings. No functional changes intended. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- The patch, which simply replaces video_pll1 with video_pll, highlights many warnings raised by checkpatch.pl. These are not generated by the changes made but are inherited from how the module was originally written. Fixing them would have meant "obscuring" the actual changes introduced. (no changes since v7) Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v5: - Split the patch dropping the dt-bindings changes. Changes in v4: - New drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++++++++------------------ 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..e96460534e7d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -23,7 +23,7 @@ static u32 share_count_audio; static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll1_bypass_sels[] =3D {"video_pll1", "vid= eo_pll1_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; @@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] =3D {"= arm_a53_div", "arm_pll_out" =20 static const char * const imx8mp_m7_sels[] =3D {"osc_24m", "sys_pll2_200m"= , "sys_pll2_250m", "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_ml_sels[] =3D {"osc_24m", "gpu_pll_out", = "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_core_sels[] =3D {"osc_24m", "gpu_pl= l_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu3d_shader_sels[] =3D {"osc_24m", "gpu_= pll_out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu2d_sels[] =3D {"osc_24m", "gpu_pll_out= ", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_audio_axi_sels[] =3D {"osc_24m", "gpu_pll= _out", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_hsio_axi_sels[] =3D {"osc_24m", "sys_pll2= _500m", "sys_pll1_800m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", @@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] =3D {= "osc_24m", "sys_pll2_1000m" =20 static const char * const imx8mp_main_axi_sels[] =3D {"osc_24m", "sys_pll2= _333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "sys_pll1_100m",}; + "video_pll_out", "sys_pll1_100m",}; =20 static const char * const imx8mp_enet_axi_sels[] =3D {"osc_24m", "sys_pll1= _266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", - "video_pll1_out", "sys_pll3_out", }; + "video_pll_out", "sys_pll3_out", }; =20 static const char * const imx8mp_nand_usdhc_sels[] =3D {"osc_24m", "sys_pl= l1_266m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", @@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] =3D {= "osc_24m", "sys_pll2_125m", =20 static const char * const imx8mp_gpu_axi_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_gpu_ahb_sels[] =3D {"osc_24m", "sys_pll1_= 800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_sels[] =3D {"osc_24m", "sys_pll1_800m= ", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_noc_io_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_axi_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ml_ahb_sels[] =3D {"osc_24m", "sys_pll1_8= 00m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_ahb_sels[] =3D {"osc_24m", "sys_pll1_133m= ", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_audio_ahb_sels[] =3D {"osc_24m", "sys_pll= 2_500m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_mipi_dsi_esc_rx_sels[] =3D {"osc_24m", "s= ys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", @@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] =3D = {"osc_24m", "sys_pll2_200m", "sys_pll1_160m", "sys_pll1_200m", }; =20 static const char * const imx8mp_i2c5_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c6_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_sai1_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", }; =20 static const char * const imx8mp_sai2_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai3_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_sai5_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", }; =20 static const char * const imx8mp_sai6_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_qos_timer_sels[] =3D {"osc_24m", "sy= s_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_ref_sels[] =3D {"osc_24m", "sys_pll2= _125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", - "video_pll1_out", "clk_ext4", }; + "video_pll_out", "clk_ext4", }; =20 static const char * const imx8mp_enet_timer_sels[] =3D {"osc_24m", "sys_pl= l2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2", "clk_ext3", - "clk_ext4", "video_pll1_out", }; + "clk_ext4", "video_pll_out", }; =20 static const char * const imx8mp_enet_phy_ref_sels[] =3D {"osc_24m", "sys_= pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", - "video_pll1_out", "audio_pll2_out", }; + "video_pll_out", "audio_pll2_out", }; =20 static const char * const imx8mp_nand_sels[] =3D {"osc_24m", "sys_pll2_500= m", "audio_pll1_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", - "sys_pll2_250m", "video_pll1_out", }; + "sys_pll2_250m", "video_pll_out", }; =20 static const char * const imx8mp_qspi_sels[] =3D {"osc_24m", "sys_pll1_400= m", "sys_pll2_333m", "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", @@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s "audio_pll2_out", "sys_pll1_100m", }; =20 static const char * const imx8mp_i2c1_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c2_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c3_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_i2c4_sels[] =3D {"osc_24m", "sys_pll1_160= m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_uart1_sels[] =3D {"osc_24m", "sys_pll1_80= m", "sys_pll2_200m", @@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] =3D {"= osc_24m", "sys_pll2_200m", "s =20 static const char * const imx8mp_pwm1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_pwm4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", - "sys_pll1_80m", "video_pll1_out", }; + "sys_pll1_80m", "video_pll_out", }; =20 static const char * const imx8mp_gpt1_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt2_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt3_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_gpt4_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; =20 static const char * const imx8mp_gpt5_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext2" }; =20 static const char * const imx8mp_gpt6_sels[] =3D {"osc_24m", "sys_pll2_100= m", "sys_pll1_400m", - "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "sys_pll1_40m", "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext3" }; =20 static const char * const imx8mp_wdog_sels[] =3D {"osc_24m", "sys_pll1_133= m", "sys_pll1_160m", @@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = =3D {"osc_24m", "sys_pll1_800 =20 static const char * const imx8mp_ipp_do_clko2_sels[] =3D {"osc_24m", "sys_= pll2_200m", "sys_pll1_400m", "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", - "video_pll1_out", "osc_32k" }; + "video_pll_out", "osc_32k" }; =20 static const char * const imx8mp_hdmi_fdcc_tst_sels[] =3D {"osc_24m", "sys= _pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", - "audio_pll2_out", "video_pll1_out", }; + "audio_pll2_out", "video_pll_out", }; =20 static const char * const imx8mp_hdmi_24m_sels[] =3D {"osc_24m", "sys_pll1= _160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; =20 static const char * const imx8mp_hdmi_ref_266m_sels[] =3D {"osc_24m", "sys= _pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", - "audio_pll1_out", "video_pll1_out", }; + "audio_pll1_out", "video_pll_out", }; =20 static const char * const imx8mp_usdhc3_sels[] =3D {"osc_24m", "sys_pll1_4= 00m", "sys_pll1_800m", "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", @@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] =3D {"= osc_24m", "sys_pll1_400m", "s static const char * const imx8mp_media_cam1_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_mipi_phy1_ref_sels[] =3D {"osc_24m"= , "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 -static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll1_out", "audio_pll2_out", +static const char * const imx8mp_media_disp_pix_sels[] =3D {"osc_24m", "vi= deo_pll_out", "audio_pll2_out", "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; =20 static const char * const imx8mp_media_cam2_pix_sels[] =3D {"osc_24m", "sy= s_pll1_266m", "sys_pll2_250m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_media_ldb_sels[] =3D {"osc_24m", "sys_pll= 2_333m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; + "video_pll_out", }; =20 static const char * const imx8mp_memrepair_sels[] =3D {"osc_24m", "sys_pll= 2_100m", "sys_pll1_80m", "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", @@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = =3D {"osc_24m", "vpu_pll_out", "sys_pll3_out", "audio_pll1_out", }; =20 static const char * const imx8mp_sai7_sels[] =3D {"osc_24m", "audio_pll1_o= ut", "audio_pll2_out", - "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "video_pll_out", "sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", }; =20 static const char * const imx8mp_dram_core_sels[] =3D {"dram_pll_out", "dr= am_alt_root", }; =20 -static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll1_out", +static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll_out", "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; @@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", a= natop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", ana= top_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", anatop_= base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); @@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MP_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); @@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); hws[IMX8MP_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MP_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_byp= ass_sels), CLK_SET_RATE_PARENT); hws[IMX8MP_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); hws[IMX8MP_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); hws[IMX8MP_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", ana= top_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); @@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) =20 hws[IMX8MP_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:02 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Date: Sat, 18 Jan 2025 13:39:48 +0100 Message-ID: <20250118124044.157308-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though adding clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the anatop module uses the input oscillators to generate various PLLs. In turn, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Furthermore, as agreed in [1], this change represents the first step toward the implementation of the anatop driver. Currently, in fact, there is no dedicated anatop driver, but the CCM driver parses the anatop node and registers the PLLs it produces. [1] https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@ama= rulasolutions.com/ Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- (no changes since v7) Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve commit message - Merge it with patch 10, 11, and 12: - 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop - 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop - 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop Changes in v4: - New .../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++- include/dt-bindings/clock/imx8mm-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mn-clock.h | 64 +++++++++++++++++ include/dt-bindings/clock/imx8mp-clock.h | 68 +++++++++++++++++++ 4 files changed, 248 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml = b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..f439b0a94ce2 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -30,22 +30,73 @@ properties: interrupts: maxItems: 1 =20 + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + '#clock-cells': const: 1 =20 required: - compatible - reg + - clocks + - clock-names - '#clock-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-anatop + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: osc_32k + - const: osc_24m + additionalProperties: false =20 examples: - | - anatop: clock-controller@30360000 { + clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; + }; + + - | + clock-controller@30360000 { + compatible =3D "fsl,imx8mq-anatop"; + reg =3D <0x30360000 0x10000>; + #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 ... diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings= /clock/imx8mm-clock.h index 102d8a6cdb55..017c06e48430 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -287,4 +287,68 @@ =20 #define IMX8MM_CLK_END 258 =20 +#define IMX8MM_ANATOP_CLK_DUMMY 0 +#define IMX8MM_ANATOP_CLK_32K 1 +#define IMX8MM_ANATOP_CLK_24M 2 +#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MM_ANATOP_AUDIO_PLL1 11 +#define IMX8MM_ANATOP_AUDIO_PLL2 12 +#define IMX8MM_ANATOP_VIDEO_PLL 13 +#define IMX8MM_ANATOP_DRAM_PLL 14 +#define IMX8MM_ANATOP_GPU_PLL 15 +#define IMX8MM_ANATOP_VPU_PLL 16 +#define IMX8MM_ANATOP_ARM_PLL 17 +#define IMX8MM_ANATOP_SYS_PLL1 18 +#define IMX8MM_ANATOP_SYS_PLL2 19 +#define IMX8MM_ANATOP_SYS_PLL3 20 +#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26 +#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MM_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MM_ANATOP_GPU_PLL_OUT 33 +#define IMX8MM_ANATOP_VPU_PLL_OUT 34 +#define IMX8MM_ANATOP_ARM_PLL_OUT 35 +#define IMX8MM_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MM_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MM_ANATOP_SYS_PLL1_40M 38 +#define IMX8MM_ANATOP_SYS_PLL1_80M 39 +#define IMX8MM_ANATOP_SYS_PLL1_100M 40 +#define IMX8MM_ANATOP_SYS_PLL1_133M 41 +#define IMX8MM_ANATOP_SYS_PLL1_160M 42 +#define IMX8MM_ANATOP_SYS_PLL1_200M 43 +#define IMX8MM_ANATOP_SYS_PLL1_266M 44 +#define IMX8MM_ANATOP_SYS_PLL1_400M 45 +#define IMX8MM_ANATOP_SYS_PLL1_800M 46 +#define IMX8MM_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MM_ANATOP_SYS_PLL2_50M 48 +#define IMX8MM_ANATOP_SYS_PLL2_100M 49 +#define IMX8MM_ANATOP_SYS_PLL2_125M 50 +#define IMX8MM_ANATOP_SYS_PLL2_166M 51 +#define IMX8MM_ANATOP_SYS_PLL2_200M 52 +#define IMX8MM_ANATOP_SYS_PLL2_250M 53 +#define IMX8MM_ANATOP_SYS_PLL2_333M 54 +#define IMX8MM_ANATOP_SYS_PLL2_500M 55 +#define IMX8MM_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MM_ANATOP_CLK_CLKOUT1 59 +#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MM_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings= /clock/imx8mn-clock.h index 04809edab33c..b2fa73803d45 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -267,4 +267,68 @@ =20 #define IMX8MN_CLK_END 235 =20 +#define IMX8MN_ANATOP_CLK_DUMMY 0 +#define IMX8MN_ANATOP_CLK_32K 1 +#define IMX8MN_ANATOP_CLK_24M 2 +#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8 +#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MN_ANATOP_AUDIO_PLL1 11 +#define IMX8MN_ANATOP_AUDIO_PLL2 12 +#define IMX8MN_ANATOP_VIDEO_PLL 13 +#define IMX8MN_ANATOP_DRAM_PLL 14 +#define IMX8MN_ANATOP_GPU_PLL 15 +#define IMX8MN_ANATOP_M7_ALT_PLL 16 +#define IMX8MN_ANATOP_ARM_PLL 17 +#define IMX8MN_ANATOP_SYS_PLL1 18 +#define IMX8MN_ANATOP_SYS_PLL2 19 +#define IMX8MN_ANATOP_SYS_PLL3 20 +#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26 +#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MN_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MN_ANATOP_GPU_PLL_OUT 33 +#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34 +#define IMX8MN_ANATOP_ARM_PLL_OUT 35 +#define IMX8MN_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MN_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MN_ANATOP_SYS_PLL1_40M 38 +#define IMX8MN_ANATOP_SYS_PLL1_80M 39 +#define IMX8MN_ANATOP_SYS_PLL1_100M 40 +#define IMX8MN_ANATOP_SYS_PLL1_133M 41 +#define IMX8MN_ANATOP_SYS_PLL1_160M 42 +#define IMX8MN_ANATOP_SYS_PLL1_200M 43 +#define IMX8MN_ANATOP_SYS_PLL1_266M 44 +#define IMX8MN_ANATOP_SYS_PLL1_400M 45 +#define IMX8MN_ANATOP_SYS_PLL1_800M 46 +#define IMX8MN_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MN_ANATOP_SYS_PLL2_50M 48 +#define IMX8MN_ANATOP_SYS_PLL2_100M 49 +#define IMX8MN_ANATOP_SYS_PLL2_125M 50 +#define IMX8MN_ANATOP_SYS_PLL2_166M 51 +#define IMX8MN_ANATOP_SYS_PLL2_200M 52 +#define IMX8MN_ANATOP_SYS_PLL2_250M 53 +#define IMX8MN_ANATOP_SYS_PLL2_333M 54 +#define IMX8MN_ANATOP_SYS_PLL2_500M 55 +#define IMX8MN_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MN_ANATOP_CLK_CLKOUT1 59 +#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MN_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings= /clock/imx8mp-clock.h index 3235d7de3b62..8c076225fd9e 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -402,4 +402,72 @@ =20 #define IMX8MP_CLK_AUDIOMIX_END 59 =20 +#define IMX8MP_ANATOP_CLK_DUMMY 0 +#define IMX8MP_ANATOP_CLK_24M 1 +#define IMX8MP_ANATOP_CLK_32K 2 +#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10 +#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11 +#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12 +#define IMX8MP_ANATOP_AUDIO_PLL1 13 +#define IMX8MP_ANATOP_AUDIO_PLL2 14 +#define IMX8MP_ANATOP_VIDEO_PLL 15 +#define IMX8MP_ANATOP_DRAM_PLL 16 +#define IMX8MP_ANATOP_GPU_PLL 17 +#define IMX8MP_ANATOP_VPU_PLL 18 +#define IMX8MP_ANATOP_ARM_PLL 19 +#define IMX8MP_ANATOP_SYS_PLL1 20 +#define IMX8MP_ANATOP_SYS_PLL2 21 +#define IMX8MP_ANATOP_SYS_PLL3 22 +#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23 +#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24 +#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25 +#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26 +#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27 +#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28 +#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29 +#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30 +#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31 +#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32 +#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33 +#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34 +#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35 +#define IMX8MP_ANATOP_DRAM_PLL_OUT 36 +#define IMX8MP_ANATOP_GPU_PLL_OUT 37 +#define IMX8MP_ANATOP_VPU_PLL_OUT 38 +#define IMX8MP_ANATOP_ARM_PLL_OUT 39 +#define IMX8MP_ANATOP_SYS_PLL3_OUT 40 +#define IMX8MP_ANATOP_SYS_PLL1_OUT 41 +#define IMX8MP_ANATOP_SYS_PLL1_40M 42 +#define IMX8MP_ANATOP_SYS_PLL1_80M 43 +#define IMX8MP_ANATOP_SYS_PLL1_100M 44 +#define IMX8MP_ANATOP_SYS_PLL1_133M 45 +#define IMX8MP_ANATOP_SYS_PLL1_160M 46 +#define IMX8MP_ANATOP_SYS_PLL1_200M 47 +#define IMX8MP_ANATOP_SYS_PLL1_266M 48 +#define IMX8MP_ANATOP_SYS_PLL1_400M 49 +#define IMX8MP_ANATOP_SYS_PLL1_800M 50 +#define IMX8MP_ANATOP_SYS_PLL2_OUT 51 +#define IMX8MP_ANATOP_SYS_PLL2_50M 52 +#define IMX8MP_ANATOP_SYS_PLL2_100M 53 +#define IMX8MP_ANATOP_SYS_PLL2_125M 54 +#define IMX8MP_ANATOP_SYS_PLL2_166M 55 +#define IMX8MP_ANATOP_SYS_PLL2_200M 56 +#define IMX8MP_ANATOP_SYS_PLL2_250M 57 +#define IMX8MP_ANATOP_SYS_PLL2_333M 58 +#define IMX8MP_ANATOP_SYS_PLL2_500M 59 +#define IMX8MP_ANATOP_SYS_PLL2_1000M 60 +#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61 +#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62 +#define IMX8MP_ANATOP_CLK_CLKOUT1 63 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:04 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 06/23] arm64: dts: imx8mm: add anatop clocks Date: Sat, 18 Jan 2025 13:39:49 +0100 Message-ID: <20250118124044.157308-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Add the bindings definitions for the anatop node. The patch is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 4de3bf22902b..597041a05073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -600,6 +600,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B5919D072 for ; Sat, 18 Jan 2025 12:41:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204069; cv=none; b=AZerd2cQXotdMRbztM3/pJ0t6nTF+M9j7Rp3F7iFz+sn5vRVr5oIHZweW9qdggh9/WKSazBrMRqw2t/BO2aYY924+QBqCu0lfeSkEw+Xm1U57fWxBq3fAAhm09EqVnRVe7V+POG7Q5HFfm64qg5YEH+Yi4zQWLKSCv1hmFfeRMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204069; c=relaxed/simple; bh=MWwhsP/1Gq2jtC+XMH/+PSmlpfJmY2R2gm9uwDR4fZI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ls0TQdvuSQpd833ue5sdxuj8zAIiIyqF1pcnVW3bGUsHQ26D/PYSlucNVPrQ+SRw+gssN8nmuUf8aibsgcGGlMhyfeDp/Gx0EiMl4Fhd1V+Qlxkf5La+B7zKzZHm3hKHRGnTd+yZYe4pab+amHYGDMu7S3AjUtnf1OdV6jtOTC8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=fZTlIMtZ; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fZTlIMtZ" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5da12292b67so4904421a12.3 for ; Sat, 18 Jan 2025 04:41:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1737204066; x=1737808866; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=fZTlIMtZHCS/asv5p8T8OBNwLN97bX+5fv3DVpHIFFS5v+XKOoDt6TvbCmOzdVzUwV pc0EsWBXwMKkRSqtyOaSQRaaYEQybI7nuZr64DAYtvDZ3P7bvcy5/p5tLa9gdq/bYK6R 1ACnvf+7Y9K/4rWcVElbu1hukI9bdxupDylQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737204066; x=1737808866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mr8rvSiMKhhr7+g2wBjSbr4ZapMlTY5YRIRH4XPzpek=; b=ppzPj/45gPrAylzvoNJoadJMHKh67pT4t1h4WNj+5+hXc42USNuc3tVDFSPJwiPn1g VM8VURwsuvAJula5YJlfrXDZ2KPh+jaqsneTET9RREUukay8KolOKIZxJv9v0xWgUfFe CiQywjrJzxmX0EPsNrlhkwuYArI4d5CcDYTh16dcl7+CN0AtA4ziO6G4ujz9RH9ZSA3r Og1QLUmrEm2vjksPvIvcYARy2AOfaLoVW14rYuVo4Okp9AL0Ead7UlQYwFbGfOSjcR5c uxxYEWrwP1oeOqSM321Om5iUFMVrNuqIWOH4rO8W8lHYW4AdFLCyqvgQ9Hy80cxpuhnh ig5w== X-Gm-Message-State: AOJu0YzSjTGp7qQji2W2TrmC8vftoCHmL9/p5TZQPA33DUenaujtZCEt OrolL2kNSWaTVtV1zBvK/X1FO1qBdL8jgy8bQwh/JRbJf6br8Oskew5Ws3kPFEVde4/c1ZtYn4K G X-Gm-Gg: ASbGncuEnNNJ/r+RJAwMM0i4QbO5EVbylyshrUV3glHVAl0zdIOWi8cN3g0nQvpgkWJ 9rnpGCexgGb9mpQiU0SWkbJg1vWRt3XY4EbCQbr5Pn7GucptZbQyCxq3w7E65PwiIDn3joKA3vX KEcu3WKdVcJ8qUiDkJ1u1jaSK0noXr+p0yTGZKZYCvJkAA+rYiTkl2bwEvme1Deicyt5cV7FKw3 8AYiXM6sHNJRRoSXtMRxd2UNcXgxIihHkaDlIdrtI2O/GH0P33jt/ZOQ6sZ0YJOZT5n2ZGlTj3r Qk1vfeLSC4S91OT1/v+HR1C8wDWyrcA3t/TrwztztDCVXwb7T+xUQXq/P/2E/fbt7nuOXzJa3rQ EYIW9xJUXcEEOpYKeZbp3RH73jYPkHh2qh3Z0 X-Google-Smtp-Source: AGHT+IFd8SJOuPnbNHYayMQ2pJl2dtTRvVnOeDARGIr6v9/DddrHyT5J/QNi2xGLWBTU+gDaqVLJPQ== X-Received: by 2002:a05:6402:849:b0:5d9:857e:b259 with SMTP id 4fb4d7f45d1cf-5db7db2becemr12516818a12.31.1737204065870; Sat, 18 Jan 2025 04:41:05 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:05 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 07/23] arm64: dts: imx8mn: add anatop clocks Date: Sat, 18 Jan 2025 13:39:50 +0100 Message-ID: <20250118124044.157308-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index a5f9cfb46e5d..49be492b5687 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -606,6 +606,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA94919DF5F for ; Sat, 18 Jan 2025 12:41:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204070; cv=none; b=QGIXG2d8YveDFYpRS2P0fFvHLVYcOTkuibwe4M/aEFB8qYfCpmkxzy6TBSqpWQiaAp4PnKh/x/OO14BwA2LHhKl9o6M/aD9H76J65QCCaXB+tNrCUSnOCtqsw+KLFWYMAgTbIc62JKjd+xXhBSDPiZI3i2oQbRTgWo/JwypMqq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204070; c=relaxed/simple; bh=EfuJYR878rJ4Cw+YuO97nDjgeWj+F6WJVMj2hzhOd0Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HJfmfg5BWz95BMG+fpvLewP2d24bQx5F+/1NpGhK1OEVine3pe7+/0o3Ka0a0IzbH0qU1UUQZqUXC5cchs6CXXc/AyMdO2uVInTTQGOyIZ/4K/djfJIdXbNOMwZTPmiHfMSDy/3jerdWAjRUkXKJy/owIiAqKSOYMFtE7muLo14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=BN3OLU0w; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="BN3OLU0w" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-aaf60d85238so494629766b.0 for ; Sat, 18 Jan 2025 04:41:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1737204067; x=1737808867; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=BN3OLU0wE5oIiv+Pa18/hfEP26B2vvVUkA8K/3LE7u3YXN0D3RJaLLtGtt0Bb1Sgjb S5wRgwPjWsDBryQDiA5gcSaEmyTo5vW+AEdkoIKgu/yrQGL/J4nGrMhjYH++bhF3c8P8 kaUlz1h9TOSF5pfcNAnGFVe6ACrzhJgkE9Ii4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737204067; x=1737808867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JTseU8DWKtdHNNseUc2PJ1vcygpii+LlAX++fbmk+pc=; b=k+yKwWOU3Sb8G31Zx+lfKxa752PoKOHASxn8PGI6v2jXn1pNZjE5baWIz3G3jkVmzA 5h/W0UE8spWBzN2GOBmWX51YK/FEXw8ev+yRhgHDjdHTUM5H5jXPahptdKYkd6hj8V7+ KzeWfSWnuSjDIc8KQ3TrW+/rcUGxr8SBWfaSBhIEi7DDl60VfKXFPOS78taedIZyigoE CH7ZGDZ17A28yrGsjcSh4WNgw92X/+Tur1IFOJGlaVlYQG32Fafp7DUyjmIMMjlKKZWv h9bAe/SL6S8JDNCqIPQuG1V4+tIzF1XttktlriAFz1RuFx6hCYEM1uRfUuw7E8kP6j3q WAOQ== X-Gm-Message-State: AOJu0Yy4sP9IrIinVMMvOQR6QCHBfLJZf9JUP2CKxS2itPUcK4UJgnCa vEwQauafFrcp1tPHQGoB8e1gx9FwHEpkxpLnePCPbT+4T43/dlx2Ag6MFOLPv6GK2dCvNqkVEom i X-Gm-Gg: ASbGnctSkP1HntCKMlPdkB9BYWKt9yGPeMIyU/FYKtjknpEmKl0T65/5V56JTWR9FAs aqB3rcMvaNk6CCMDCRys0/yc/r0WqWE2bRulLsuX3SGTwN857NnDw+W2KpeP5CjeZFpJJAI0O/k gReRCE1QaTgY5gZXxMH2L0TO0HjoSP2VxzyTdyz61Xvxj1HVfAzvtMylFItoPAosa8ruhm1AsOM cVJCu9PskUsMax6dKsByaWOnzPEMRPSdqR4pmt2Ce+pqwAYsoVzH6Xe5mHQH6vqXTyXS71On8LF V4mZOFxiLeG3To+qgs5rJa9aSXVRSUxYV6zg2MBPLrMUCF1eFNe5estiztmu/Db3xf3nwxNaQYI XfqcSCIJ9U3gZ5J5pOrtdD3GJkgQMXPT0TbO6 X-Google-Smtp-Source: AGHT+IHX2I9yy/tg03FjOqBgNh1ud5x4FkNGAAghKsVjSyjjnfF7XR2jyfI8B0AX0C2mCSM8Nkikkw== X-Received: by 2002:a17:907:7256:b0:aae:85b4:a07 with SMTP id a640c23a62f3a-ab38b19146dmr492323466b.8.1737204067196; Sat, 18 Jan 2025 04:41:07 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:06 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 08/23] arm64: dts: imx8mp: add anatop clocks Date: Sat, 18 Jan 2025 13:39:51 +0100 Message-ID: <20250118124044.157308-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index e0d3b8cba221..0b928e173f29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -709,6 +709,8 @@ anatop: clock-controller@30360000 { compatible =3D "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg =3D <0x30360000 0x10000>; #clock-cells =3D <1>; + clocks =3D <&osc_32k>, <&osc_24m>; + clock-names =3D "osc_32k", "osc_24m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8624F19D089 for ; Sat, 18 Jan 2025 12:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204072; cv=none; b=uHBH8RM2ccd+nBomL7bLHjnv4w8DKz3PMrN8gYpAB0GxqKpBr8aZgsOJgXsaHZIO2ZpZMV2yN4bAo8/FUFDJSHeCcbXXdMct5FhxPWBUptLExOK8ODoIXMpBCyKCOplhLZxUWTNtREt8lSvoxciAyOhu/qI0V5I3ny5A9Bpl2pw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204072; c=relaxed/simple; bh=vc25/TFqvg0Ekr2Sm4G/VkkviBdPeMF5e7FdTWNCvAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=INa/PkxsSbjcEQDMZjthKhyYZMeidzYxpbqfoypKXHXGRZx42mrr4DVCdV3VLMHogASYuDp8UJKkyv8PUQe4NWfEP4f4TGUg66IYWtsOscKBUZN98uEgiC7NFpiPEorvhs1zvUDwWEeKTINlDk9o71oKafDpqdlXk3yCR0zHIr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=YfzDnRCj; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="YfzDnRCj" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-aa6c0d1833eso600046166b.1 for ; Sat, 18 Jan 2025 04:41:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1737204068; x=1737808868; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=YfzDnRCjHQOJQ9Wd3ZAPtQNvmtxWQRdO65n3Ve9UTzm4F80g5ud4YMLihrKTi6ntQL q1HQx33s0ZRpYnBwgve8Qtr2R6uBqpGyWqqxe8LwugBKvpP2n/cm4u3i4qe65DQpMoVd o7oIIeEutgd9BoZisfcKUP0zqB29rzLCAJ4u8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737204068; x=1737808868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BHj8xJJDjB/nn7+FV+WNgNcGZHPneQlK/63TZumKERk=; b=B+axWt7z7HZFx3p5MvmpZn1VmpwKLN+N+XFDiDSmxX0vpwGNVM4VFqwb37OqcwPLAk 0WzVQXAeomhzBZKbqLyYIGVRCb1CFLJ3Ye9kVFZC21ATaydxK3Z4mvt7E6iDDEeNY7xs mIgsPGKtyd1PDNl/pslUVbmu/pFCWf+RzkgoCXVTfu3SSZbGVAr9vsnVClWq0WT/jrID Rv0+QZuthuvFc8ePAbyF0ga0/AL6lrb152X4aO1nCrQyjD/hQ//ul8OxeYfWzVCRaieL ozZ72HZFbDbW3yYc8bwAIewECSQ7KJH15T03aHX7Borj12DN/guuN+PXhpYtTe7Ucp9T cSGQ== X-Gm-Message-State: AOJu0YypxJcllzHdCTkQMIg470rEB4mRAg3jPOx5uuKKYl8oyn9WMtNR P8JgxNtEy0lCZ1ET3qgKl4Mvrg70cpCBDrVo2VCu4n4M6gDipzwFIMxInZ2QKK0glBpAEHQ3NIO U X-Gm-Gg: ASbGncvHjNKuDCCN7A6NA0fM7PjvbYAWo1kqfQBiG56VZHVgqcQBMlD2kGaieVMDds0 VVBu3bX6yA7tn17ZEqavXVEljD4FrzOFxeKUtTV+X3x7jND7NnLGV6DL6Q8eSYKrLhQz4r6bRMa 4wmdX5iMDjNSgrUa9uwAUZ0hlu1hYDoJNcs7DXmNwIP37HD6IUk678tUbi5gjn8zJl2AKmY707B 4paKG/Rs4qmcHoMqnPuAP/a2TWDWv2Ji2zTtw/onJluNq6tDAO8ZvWTEviBV4nzPPT4bQDeg3YM 6nLmqNSJXSdRarWAYUnXFKgFenlmQlquv2ZgtKpWzVbRYvocc6GXpjX43/aSncvqfYmv91zMX4x OAZzBYKKGrKuech9RN+BA2xqJogE0uEJ0eBmq X-Google-Smtp-Source: AGHT+IEjVsxeqV3q0cuCfowb8sHunl1c2U0QJyl0v84iVeugrlhDgI71TwU/pUagXm7GAT1GfAlb1g== X-Received: by 2002:a17:907:940b:b0:aac:619:7ed8 with SMTP id a640c23a62f3a-ab38b1e651bmr538826966b.7.1737204068521; Sat, 18 Jan 2025 04:41:08 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:08 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 09/23] arm64: dts: imx8mq: add anatop clocks Date: Sat, 18 Jan 2025 13:39:52 +0100 Message-ID: <20250118124044.157308-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clocks to anatop node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index d51de8d899b2..1d1424a136f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -817,6 +817,8 @@ anatop: clock-controller@30360000 { reg =3D <0x30360000 0x10000>; interrupts =3D ; #clock-cells =3D <1>; + clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names =3D "ckil", "osc_25m", "osc_27m"; }; =20 snvs: snvs@30370000 { --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0CCE19068E for ; Sat, 18 Jan 2025 12:41:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204073; cv=none; b=DbvYJ9Sevuj/EJ4hW93Ss1+MG2LL8xzjHE0yKfCirxvKJf3lv1jbWmz/ccGgRvKh9WjpC9VxLgtzqbQZ9Au/ckv3CsBE7ZmR3JtCfVZyRoOzCHhk7uPiCF0l3TRSmYna349RmxO3WoRv7ngZYe3OG8ZahzHC+1KzlXdRilcne+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737204073; c=relaxed/simple; bh=9GxDbQvN0FsobifitL/iQ8hAJbEhDXi2QaB7Iaq7RJI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vDdgzeoUlUQPPdC0iiqThhebeWfHBo2SZbMblkjPmoyNgy2X87Uf26YcX+GZhLWNO90gpWc7gcyuLd9uxR17n6dhsgfcCnwSTbwJbvllJQxvle2lAmLg2Ck/oNZfAqF2To9zkjf1wQALeLoPiWF1boY7P/zo/f018+wIMrl9ZG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=F7qHzor9; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="F7qHzor9" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-ab34a170526so416934166b.0 for ; Sat, 18 Jan 2025 04:41:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1737204070; x=1737808870; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SjKk3n/EWVmeikEmbqzIG+MPD0szAgZhKNxV6SUP6YY=; b=F7qHzor94/ehWtC5r6Qe8VSuCkDL/s0h3JTdv3noA95FUs0TGeO3RhpQC8+BI+x5lh DcdupWHSzHK01kfPNRz7vvhM3hArChZ3t3SovSRrcNhx49iA2kmTTzQGn7o7e1Qr+a4I F+akRZuQW7HcQwyyTD67naMS5Pey/kXOrExN0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737204070; x=1737808870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SjKk3n/EWVmeikEmbqzIG+MPD0szAgZhKNxV6SUP6YY=; b=Sb+8vpXgLFoJaZXBRXk0QX0E/31L8Zn3cV6A0twVFDuPBSHt9pwm29wnv1MB3Bm3k0 bw1gspWAa0KDCrEnL6fpyL/i0dXFeluWpF+eCVrO3/B4tp2HD7Vq46W5IaiSTeSXkwBk WyIF9e8mRPKPVaREoBZu1TAlSLanra6L2zFJacYDL57eXG8BnKDxS6zlawk2rjdq6gUx lOubYiN/8IaK+jGUiB54/IHNDn1jN8KPCq8KZ8YshlavJsTfoBY6ocJ8sOPujHMOKl5j fgsRZM6U3AnuHxmWQ1bbRKW1QG11H4TWlFENN31wGDGQqrCU3j9KB67PqucVOte9ESPm c8gQ== X-Gm-Message-State: AOJu0YyyIvp8HbObqqjqQ9Re2lzxms+ZXwnLXbf2GesZXgR92nqUUKGQ JAm3M3pkH/JP1dcCSCklMZFQJ25J+NhuhcVneiJl+hqYY/7tagR1lHQQxoL6VCmbF1YkfXHFRfY o X-Gm-Gg: ASbGncvLVe/cc3ZKLjOKPLrqt56XLAihRMyyuhQ4lq+Cr2tEVaZEFoG+ukxSLHNjvp+ bsrbVTfX2y4VEEgQuQxnG7rzSzmtqQhsizeWgjNWAaNkDNNoy3MB78r8eM9Ni5tq65+AufwwzNA Xa4AreCH9t40OnRCG3dwZUWb9iXnlLBFLCnoU/6Ka2mhdbiPJG2eCz0AzCtqV4tJsWkjXnjPUCz mwlOw0s2eGqP23rWbX5QYIQdZrCOYYJ4JWqOZNmL/lfMlx8nToEVcORTA1udKY84V/MMZOd8AZU 3Xj3Ez3YcazKR8NyrHBQDt0GAyR/SyWfNFNsqH6unggjysUVETobbbUBfc+Pf0NllXrdAM3HPDL SJXhg39znAk1FlVqH+WDxOS0Og039ADPbqTkz X-Google-Smtp-Source: AGHT+IG+E9QI4nYzoY+YN1QOMcP80jWKF/DOpc0bYiVCZW9BPZzE9/t7StCYdIbpqJGBKvVbQm3HcQ== X-Received: by 2002:a17:906:c108:b0:aa6:79fa:b47d with SMTP id a640c23a62f3a-ab38b0b8138mr568616566b.1.1737204069853; Sat, 18 Jan 2025 04:41:09 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:09 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 10/23] clk: imx: add hw API imx_anatop_get_clk_hw Date: Sat, 18 Jan 2025 13:39:53 +0100 Message-ID: <20250118124044.157308-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v9: - Add 'Reviewed-by' tag of Peng Fan Changes in v7: - Add device_node type parameter to imx8m_anatop_get_clk_hw() - Rename imx8m_anatop_get_clk_hw() to imx_anatop_get_clk_hw() - Drop the gaurding macros so the code can be used also by i.MX9 Changes in v5: - Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors Changes in v4: - New drivers/clk/imx/clk.c | 15 +++++++++++++++ drivers/clk/imx/clk.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index df83bd939492..a906d3cd960b 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -128,6 +128,21 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_no= de *np, const char *name) } EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); =20 +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id) +{ + struct of_phandle_args args; + struct clk_hw *hw; + + args.np =3D np; + args.args_count =3D 1; + args.args[0] =3D id; + + hw =3D __clk_get_hw(of_clk_get_from_provider(&args)); + pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw)); + return hw; +} +EXPORT_SYMBOL_GPL(imx_anatop_get_clk_hw); + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..50e407cf48d9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -487,4 +487,6 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const = char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); =20 +struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); + #endif --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32C311A8400 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:11 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Dan Carpenter , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 11/23] clk: imx: add support for i.MX8MN anatop clock driver Date: Sat, 18 Jan 2025 13:39:54 +0100 Message-ID: <20250118124044.157308-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v9: - Fix a build warning raised by the kernel test robot - Add 'Reviewed-by' tag of Peng Fan Changes in v8: - Drop call of of_parse_phandle() to get the anatop's device node. Changes in v7: - Update the code based on the changes made to the imx8m_anatop_get_clk_hw(): - Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw - Add device_node type parameter - Call of_parse_phandle() to get the anatop's device node. Changes in v6: - Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben removed from include/dt-bindings/clock/imx8mn-clock.h. Changes in v4: - New drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mn.c | 183 ++++++++---------- 3 files changed, 364 insertions(+), 104 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..f0f1d01c68f8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -26,7 +26,7 @@ mxc-clk-objs +=3D clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o -obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o =20 diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8= mn-anatop.c new file mode 100644 index 000000000000..5091794948eb --- /dev/null +++ b/drivers/clk/imx/clk-imx8mn-anatop.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver + * + * Copyright (c) 2024 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MN_ANATOP_CLK_END (IMX8MN_ANATOP_CLK_CLKOUT2 + 1) + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "dummy", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MN_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MN_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MN_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =3D + imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MN_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MN_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MN_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, + &imx_1443x_dram_pll); + hws[IMX8MN_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_M7_ALT_PLL] =3D + imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MN_ANATOP_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MN_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, + &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, + m7_alt_pll_bypass_sels, + ARRAY_SIZE(m7_alt_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MN_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =3D + imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", + base + 0x74, 11); + hws[IMX8MN_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); + hws[IMX8MN_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); + hws[IMX8MN_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =3D + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mn_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mn-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match); + +static struct platform_driver imx8mn_anatop_clk_driver =3D { + .probe =3D imx8mn_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mn-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mn_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mn_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..c3a3d063d58e 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -24,16 +24,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; =20 -static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; -static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; -static const char * const m7_alt_pll_bypass_sels[] =3D {"m7_alt_pll", "m7_= alt_pll_ref_sel", }; -static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; -static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; - static const char * const imx8mn_a53_sels[] =3D {"osc_24m", "arm_pll_out",= "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] =3D {"o= sc_24m", "sys_pll2_200m", "sy "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "dummy", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; =20 static int imx8mn_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; + struct device_node *np =3D dev->of_node, *anp; void __iomem *base; int ret; =20 + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MN_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -331,99 +320,90 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MN_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MN_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MN_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + anp =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MN_CLK_DUMMY] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DU= MMY); + hws[IMX8MN_CLK_24M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M); + hws[IMX8MN_CLK_32K] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K); hws[IMX8MN_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MN_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MN_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } - - hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); - hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_AUDIO_PLL1_REF_SEL); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_AUDIO_PLL2_REF_SEL); + hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_VIDEO_PLL_REF_SEL); + hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _DRAM_PLL_REF_SEL); + hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= GPU_PLL_REF_SEL); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANAT= OP_M7_ALT_PLL_REF_SEL); + hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= ARM_PLL_REF_SEL); + hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _SYS_PLL3_REF_SEL); + + hws[IMX8MN_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL1); + hws[IMX8MN_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL2); + hws[IMX8MN_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_= PLL); + hws[IMX8MN_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PL= L); + hws[IMX8MN_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); + hws[IMX8MN_M7_ALT_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_AL= T_PLL); + hws[IMX8MN_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); + hws[IMX8MN_SYS_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 1); + hws[IMX8MN_SYS_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 2); + hws[IMX8MN_SYS_PLL3] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL= 3); =20 /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_AUDIO_PLL1_BYPASS); + hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_AUDIO_PLL2_BYPASS); + hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _VIDEO_PLL_BYPASS); + hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= DRAM_PLL_BYPASS); + hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_G= PU_PLL_BYPASS); + hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATO= P_M7_ALT_PLL_BYPASS); + hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= RM_PLL_BYPASS); + hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= SYS_PLL3_BYPASS); =20 /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= UDIO_PLL1_OUT); + hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_A= UDIO_PLL2_OUT); + hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VI= DEO_PLL_OUT); + hws[IMX8MN_DRAM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRA= M_PLL_OUT); + hws[IMX8MN_GPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_= PLL_OUT); + hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M= 7_ALT_PLL_OUT); + hws[IMX8MN_ARM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_= PLL_OUT); + hws[IMX8MN_SYS_PLL3_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL3_OUT); =20 /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); - hws[IMX8MN_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); + hws[IMX8MN_SYS_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_OUT); + hws[IMX8MN_SYS_PLL1_40M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_40M); + hws[IMX8MN_SYS_PLL1_80M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL1_80M); + hws[IMX8MN_SYS_PLL1_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_100M); + hws[IMX8MN_SYS_PLL1_133M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_133M); + hws[IMX8MN_SYS_PLL1_160M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_160M); + hws[IMX8MN_SYS_PLL1_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_200M); + hws[IMX8MN_SYS_PLL1_266M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_266M); + hws[IMX8MN_SYS_PLL1_400M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_400M); + hws[IMX8MN_SYS_PLL1_800M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL1_800M); =20 /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); - hws[IMX8MN_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MN_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MN_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); - - np =3D dev->of_node; - base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); - goto unregister_hws; - } + hws[IMX8MN_SYS_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL2_OUT); + hws[IMX8MN_SYS_PLL2_50M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS= _PLL2_50M); + hws[IMX8MN_SYS_PLL2_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_100M); + hws[IMX8MN_SYS_PLL2_125M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_125M); + hws[IMX8MN_SYS_PLL2_166M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_166M); + hws[IMX8MN_SYS_PLL2_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_200M); + hws[IMX8MN_SYS_PLL2_250M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_250M); + hws[IMX8MN_SYS_PLL2_333M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_333M); + hws[IMX8MN_SYS_PLL2_500M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SY= S_PLL2_500M); + hws[IMX8MN_SYS_PLL2_1000M] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_S= YS_PLL2_1000M); + + hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT1_SEL); + hws[IMX8MN_CLK_CLKOUT1_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT1_DIV); + hws[IMX8MN_CLK_CLKOUT1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_= CLKOUT1); + hws[IMX8MN_CLK_CLKOUT2_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT2_SEL); + hws[IMX8MN_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_= CLK_CLKOUT2_DIV); + hws[IMX8MN_CLK_CLKOUT2] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_= CLKOUT2); =20 /* CORE */ hws[IMX8MN_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mn_a53_sels, base + 0x8000); @@ -599,18 +579,15 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) =20 ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); if (ret < 0) { - dev_err(dev, "failed to register hws for i.MX8MN\n"); - goto unregister_hws; + imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); + return dev_err_probe(dev, ret, + "failed to register hws for i.MX8MN\n"); } =20 imx_register_uart_clocks(); =20 + dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n"); return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:12 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 12/23] dt-bindings: clock: imx8m-clock: add PLLs Date: Sat, 18 Jan 2025 13:39:55 +0100 Message-ID: <20250118124044.157308-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though adding the PLLs to clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- (no changes since v7) Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - New .../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..d96570bf60dc 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -29,12 +29,12 @@ properties: maxItems: 2 =20 clocks: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 clock-names: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 '#clock-cells': const: 1 @@ -86,6 +86,10 @@ allOf: - description: ext2 clock input - description: ext3 clock input - description: ext4 clock input + - description: audio1 PLL input + - description: audio2 PLL input + - description: dram PLL input + - description: video PLL input =20 clock-names: items: @@ -95,20 +99,31 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + - const: audio_pll1 + - const: audio_pll2 + - const: dram_pll + - const: video_pll =20 additionalProperties: false =20 examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible =3D "fsl,imx8mm-ccm"; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 13/23] arm64: dts: imx8mm: add PLLs to clock controller module (CCM) Date: Sat, 18 Jan 2025 13:39:56 +0100 Message-ID: <20250118124044.157308-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 597041a05073..79f4c1ae7d8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -642,9 +642,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL2>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MM_CLK_A53_SRC>, <&clk IMX8MM_CLK_A53_CORE>, <&clk IMX8MM_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC1D01AE875 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:15 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 14/23] arm64: dts: imx8mn: add PLLs to clock controller module (CCM) Date: Sat, 18 Jan 2025 13:39:57 +0100 Message-ID: <20250118124044.157308-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index 49be492b5687..01013c1fd61d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -643,9 +643,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MN_ANATOP_AUDIO_PLL2>, + <&anatop IMX8MN_ANATOP_DRAM_PLL>, + <&anatop IMX8MN_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3C6B1B0416 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:16 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v9 15/23] arm64: dts: imx8mp: add PLLs to clock controller module (CCM) Date: Sat, 18 Jan 2025 13:39:58 +0100 Message-ID: <20250118124044.157308-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the PLLs generated by anatop to the clock list of the Clock Controller Module (CCM) node. Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - New arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 0b928e173f29..eab05170442d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -751,9 +751,14 @@ clk: clock-controller@30380000 { ; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MP_ANATOP_AUDIO_PLL2>, + <&anatop IMX8MP_ANATOP_DRAM_PLL>, + <&anatop IMX8MP_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; assigned-clocks =3D <&clk IMX8MP_CLK_A53_SRC>, <&clk IMX8MP_CLK_A53_CORE>, <&clk IMX8MP_CLK_NOC>, --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE521B0410 for ; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:18 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Krzysztof Kozlowski , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Date: Sat, 18 Jan 2025 13:39:59 +0100 Message-ID: <20250118124044.157308-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The addition of DT bindings for enabling and tuning spread spectrum clocking generation can be applied specifically to the PLLs. The "" value for the fsl,ssc-method property is specifically intended to specify a "no SSC" case, as in the example, when you don't want to configure spread spectrum for one of the PLLs, thus avoiding the use of a method that would only make sense if SSC were being set. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- (no changes since v7) Changes in v7: - List the PLLs to strictly define the setup order for each of the added properties - Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent" properties - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - Improve the commit message - change minItems from 7 to 1 for all the ssc properties added - change maxItems from 10 to 4 for alle the ssc properties added - update the DTS example Changes in v4: - Drop "fsl,ssc-clocks" property. The other added properties now refer to the clock list. - Updated minItems and maxItems of - clocks - clock-names - fsl,ssc-modfreq-hz - fsl,ssc-modrate-percent - fsl,ssc-modmethod - Updated the dts examples Changes in v3: - Added in v3 - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. .../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index d96570bf60dc..d347d630764a 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,6 +43,46 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m= -clock.h for the full list of i.MX8M clock IDs. =20 + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate for each clock + supporting spread spectrum. + minItems: 1 + items: + - description: audio_pll1 + - description: audio_pll2 + - description: dram_pll + - description: video_pll + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + The modulation techniques for each clock supporting spread + spectrum in this order:: + - audio_pll1 + - audio_pll2 + - dram_pll + - video_pll + minItems: 1 + maxItems: 4 + items: + enum: + - "" + - down-spread + - up-spread + - center-spread + required: - compatible - reg @@ -76,6 +116,10 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + else: properties: clocks: @@ -124,6 +168,9 @@ examples: clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", "dram_pll", "video_pll"; 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:20 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 17/23] clk: imx: pll14xx: support spread spectrum clock generation Date: Sat, 18 Jan 2025 13:40:00 +0100 Message-ID: <20250118124044.157308-18-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock (SSC) generation to the pll14xxx driver. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- (no changes since v7) Changes in v7: - Add 'Reviewed-by' tag of Peng Fan Changes in v6: - Update the code based on the changes made to the DT bindings drivers/clk/imx/clk-pll14xx.c | 134 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 16 ++++ 2 files changed, 150 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..c20f1ade9dff 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + bool ssc_enable; + struct imx_pll14xx_ssc ssc_conf; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long paren= t_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *conf =3D &pll->ssc_conf; + u32 sscg_ctrl, mfr, mrr; + + sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + mfr =3D parent_rate / (conf->mod_freq * pdiv * (1 << 5)); + mrr =3D (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, conf->mod_type); + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -542,3 +577,102 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *= dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc = *conf) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + + pll->ssc_enable =3D true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc); + +static int clk_pll14xx_ssc_mod_type(const char *name, + enum imx_pll14xx_ssc_mod_type *mod_type) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_types[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i =3D 0; i < ARRAY_SIZE(mod_types); i++) { + if (!strcmp(name, mod_types[i].name)) { + *mod_type =3D mod_types[i].id; + return 0; + } + } + + return -EINVAL; +} + +static int clk_pll14xx_ssc_index(const char *pll_name) +{ + static const char *const pll_names[] =3D { + "audio_pll1", + "audio_pll2", + "dram_pll", + "video_pll" + }; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pll_names); i++) { + if (!strcmp(pll_names[i], pll_name)) + return i; + } + + return -ENODEV; +} + +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_n= ame, + struct imx_pll14xx_ssc *conf) +{ + int index, ret; + const char *s; + + if (!conf) + return -EINVAL; + + index =3D clk_pll14xx_ssc_index(pll_name); + if (index < 0) + return index; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", index, + &conf->mod_freq); + if (ret) + return ret; + + ret =3D of_property_read_u32_index(np, "fsl,ssc-modrate-percent", index, + &conf->mod_rate); + if (ret) { + pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n", + np); + return ret; + } + + ret =3D of_property_read_string_index(np, "fsl,ssc-modmethod", index, &s); + if (ret) { + pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n", + np); + return ret; + } + + if (strlen(s) =3D=3D 0) + return -ENODEV; + + ret =3D clk_pll14xx_ssc_mod_type(s, &conf->mod_type); + if (ret) { + pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np); + return ret; + } + + pr_debug("%s: SSC %s settings: mod_freq: %d, mod_rate: %d: mod_method: %s= [%d]\n", + __func__, pll_name, conf->mod_freq, conf->mod_rate, s, conf->mod_type); + + return 0; +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 50e407cf48d9..38e4a4cf253d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -69,6 +69,18 @@ struct imx_pll14xx_clk { int flags; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; @@ -489,4 +501,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const = char *compatible, =20 struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id); =20 +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc = *conf); +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_n= ame, + struct imx_pll14xx_ssc *conf); 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:21 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Peng Fan , Abel Vesa , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 18/23] clk: imx8mn: support spread spectrum clock generation Date: Sat, 18 Jan 2025 13:40:01 +0100 Message-ID: <20250118124044.157308-19-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v9: - Add 'Reviewed-by' tag of Peng Fan drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index c3a3d063d58e..090b5924fa01 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -344,9 +345,21 @@ static int imx8mn_clocks_probe(struct platform_device = *pdev) hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP= _SYS_PLL3_REF_SEL); =20 hws[IMX8MN_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO= _PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf); 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:22 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 19/23] clk: imx: add support for i.MX8MP anatop clock driver Date: Sat, 18 Jan 2025 13:40:02 +0100 Message-ID: <20250118124044.157308-20-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8P anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mp-anatop.c | 305 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mp.c | 187 ++++++++--------- 3 files changed, 390 insertions(+), 104 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mp-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index f0f1d01c68f8..0c28a4727e9c 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn-anatop.o clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-audiomix.o +obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp-anatop.o clk-imx8mp.o clk-imx8mp-= audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o =20 obj-$(CONFIG_CLK_IMX93) +=3D clk-imx93.o diff --git a/drivers/clk/imx/clk-imx8mp-anatop.c b/drivers/clk/imx/clk-imx8= mp-anatop.c new file mode 100644 index 000000000000..95ddc3fbadd3 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mp-anatop.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mp-anatop.c - NXP i.MX8MP anatop clock driver + * + * Copyright (c) 2025 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MP_ANATOP_CLK_END (IMX8MP_ANATOP_CLK_CLKOUT2 + 1) + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll1_bypass_sels[] =3D {"sys_pll1", "sys_pll= 1_ref_sel", }; +static const char * const sys_pll2_bypass_sels[] =3D {"sys_pll2", "sys_pll= 2_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mp_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MP_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MP_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MP_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MP_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MP_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_VPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_SYS_PLL1_REF_SEL] =3D + imx_clk_hw_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_SYS_PLL2_REF_SEL] =3D + imx_clk_hw_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MP_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MP_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MP_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MP_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MP_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", + base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MP_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", + base + 0x64, &imx_1416x_pll); + hws[IMX8MP_ANATOP_VPU_PLL] =3D + imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MP_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", + base + 0x84, &imx_1416x_pll); + hws[IMX8MP_ANATOP_SYS_PLL1] =3D + imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", + base + 0x94, &imx_1416x_pll); + hws[IMX8MP_ANATOP_SYS_PLL2] =3D + imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", + base + 0x104, &imx_1416x_pll); + hws[IMX8MP_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", + base + 0x114, &imx_1416x_pll); + + hws[IMX8MP_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, + 16, 1, audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, + 16, 1, video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, + 16, 1, dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, + 28, 1, gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_VPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, + 28, 1, vpu_pll_bypass_sels, + ARRAY_SIZE(vpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, + 28, 1, arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_SYS_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll1_bypass", base + 0x94, + 28, 1, sys_pll1_bypass_sels, + ARRAY_SIZE(sys_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_SYS_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll2_bypass", base + 0x104, + 28, 1, sys_pll2_bypass_sels, + ARRAY_SIZE(sys_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MP_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, + 28, 1, sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + hws[IMX8MP_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MP_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MP_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MP_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MP_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MP_ANATOP_VPU_PLL_OUT] =3D + imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", + base + 0x74, 11); + hws[IMX8MP_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MP_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + hws[IMX8MP_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", + base + 0x94, 11); + + hws[IMX8MP_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MP_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MP_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MP_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MP_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MP_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MP_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MP_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MP_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + hws[IMX8MP_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", + base + 0x104, 11); + + hws[IMX8MP_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MP_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MP_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MP_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MP_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MP_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MP_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MP_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MP_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MP_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MP_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MP_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MP_ANATOP_CLK_CLKOUT2_SEL] =3D + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MP_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MP_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MP_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MP_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MP anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mp_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mp-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mp_anatop_clk_of_match); + +static struct platform_driver imx8mp_anatop_clk_driver =3D { + .probe =3D imx8mp_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mp-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mp_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mp_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MP anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index e96460534e7d..9dda576e5fbd 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -20,18 +20,6 @@ static u32 share_count_media; static u32 share_count_usb; static u32 share_count_audio; =20 -static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; -static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; -static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; -static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; -static const char * const sys_pll1_bypass_sels[] =3D {"sys_pll1", "sys_pll= 1_ref_sel", }; -static const char * const sys_pll2_bypass_sels[] =3D {"sys_pll2", "sys_pll= 2_ref_sel", }; -static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; - static const char * const imx8mp_a53_sels[] =3D {"osc_24m", "arm_pll_out",= "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -397,28 +385,16 @@ static const char * const imx8mp_sai7_sels[] =3D {"os= c_24m", "audio_pll1_out", "au =20 static const char * const imx8mp_dram_core_sels[] =3D {"dram_pll_out", "dr= am_alt_root", }; =20 -static const char * const imx8mp_clkout_sels[] =3D {"audio_pll1_out", "aud= io_pll2_out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; =20 static int imx8mp_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np; - void __iomem *anatop_base, *ccm_base; + struct device_node *np =3D dev->of_node, *anp; + void __iomem *ccm_base; int err; =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); - anatop_base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(anatop_base))) - return PTR_ERR(anatop_base); - - np =3D dev->of_node; ccm_base =3D devm_platform_ioremap_resource(pdev, 0); if (WARN_ON(IS_ERR(ccm_base))) return PTR_ERR(ccm_base); @@ -430,88 +406,92 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MP_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + anp =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MP_CLK_DUMMY] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_DU= MMY); + hws[IMX8MP_CLK_24M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_24M); + hws[IMX8MP_CLK_32K] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_32K); hws[IMX8MP_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MP_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MP_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MP_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - hws[IMX8MP_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", ana= top_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", anatop_= base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_SYS_PLL1_REF_SEL] =3D imx_clk_hw_mux("sys_pll1_ref_sel", anato= p_base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_SYS_PLL2_REF_SEL] =3D imx_clk_hw_mux("sys_pll2_ref_sel", anato= p_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); - hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); - hws[IMX8MP_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); - hws[IMX8MP_SYS_PLL1] =3D imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel= ", anatop_base + 0x94, &imx_1416x_pll); - hws[IMX8MP_SYS_PLL2] =3D imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel= ", anatop_base + 0x104, &imx_1416x_pll); - hws[IMX8MP_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", anatop_base + 0x114, &imx_1416x_pll); - - hws[IMX8MP_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_byp= ass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); - hws[IMX8MP_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", ana= top_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); - hws[IMX8MP_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", ana= top_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels= ), CLK_SET_RATE_PARENT); - hws[IMX8MP_SYS_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll1_bypass", a= natop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_= sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_SYS_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll2_bypass", a= natop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MP_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", a= natop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass= _sels), CLK_SET_RATE_PARENT); - - hws[IMX8MP_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); - hws[IMX8MP_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", anatop_base + 0x14, 13); - hws[IMX8MP_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", anatop_base + 0x28, 13); - hws[IMX8MP_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", anatop_base + 0x50, 13); - hws[IMX8MP_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", anatop_base + 0x64, 11); - hws[IMX8MP_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", anatop_base + 0x74, 11); - hws[IMX8MP_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", anatop_base + 0x84, 11); - hws[IMX8MP_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", anatop_base + 0x114, 11); - - hws[IMX8MP_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1_by= pass", anatop_base + 0x94, 11); - - hws[IMX8MP_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MP_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MP_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MP_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MP_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MP_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MP_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MP_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MP_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); - - hws[IMX8MP_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2_by= pass", anatop_base + 0x104, 11); - - hws[IMX8MP_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MP_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MP_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MP_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MP_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MP_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MP_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MP_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MP_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MP_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", anatop_bas= e + 0x128, 4, 4, - imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); - hws[IMX8MP_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", anatop_base + 0x128, 0, 4); - hws[IMX8MP_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", ana= top_base + 0x128, 8); - hws[IMX8MP_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", anatop_bas= e + 0x128, 20, 4, - imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); - hws[IMX8MP_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", anatop_base + 0x128, 16, 4); - hws[IMX8MP_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", ana= top_base + 0x128, 24); + hws[IMX8MP_AUDIO_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANAT= OP_AUDIO_PLL1_REF_SEL); + hws[IMX8MP_AUDIO_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANAT= OP_AUDIO_PLL2_REF_SEL); + hws[IMX8MP_VIDEO_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATO= P_VIDEO_PLL_REF_SEL); + hws[IMX8MP_DRAM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _DRAM_PLL_REF_SEL); + hws[IMX8MP_GPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= GPU_PLL_REF_SEL); + hws[IMX8MP_VPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= VPU_PLL_REF_SEL); + hws[IMX8MP_ARM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= ARM_PLL_REF_SEL); + hws[IMX8MP_SYS_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _SYS_PLL1_REF_SEL); + hws[IMX8MP_SYS_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _SYS_PLL2_REF_SEL); + hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _SYS_PLL3_REF_SEL); + + hws[IMX8MP_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO= _PLL1); + hws[IMX8MP_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO= _PLL2); + hws[IMX8MP_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_= PLL); + hws[IMX8MP_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PL= L); + hws[IMX8MP_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL); + hws[IMX8MP_VPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL); + hws[IMX8MP_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL); + hws[IMX8MP_SYS_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL= 1); + hws[IMX8MP_SYS_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL= 2); + hws[IMX8MP_SYS_PLL3] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL= 3); + + hws[IMX8MP_AUDIO_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATO= P_AUDIO_PLL1_BYPASS); + hws[IMX8MP_AUDIO_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATO= P_AUDIO_PLL2_BYPASS); + hws[IMX8MP_VIDEO_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _VIDEO_PLL_BYPASS); + hws[IMX8MP_DRAM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= DRAM_PLL_BYPASS); + hws[IMX8MP_GPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_G= PU_PLL_BYPASS); + hws[IMX8MP_VPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_V= PU_PLL_BYPASS); + hws[IMX8MP_ARM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_A= RM_PLL_BYPASS); + hws[IMX8MP_SYS_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= SYS_PLL1_BYPASS); + hws[IMX8MP_SYS_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= SYS_PLL2_BYPASS); + hws[IMX8MP_SYS_PLL3_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= SYS_PLL3_BYPASS); + + hws[IMX8MP_AUDIO_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_A= UDIO_PLL1_OUT); + hws[IMX8MP_AUDIO_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_A= UDIO_PLL2_OUT); + hws[IMX8MP_VIDEO_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VI= DEO_PLL_OUT); + hws[IMX8MP_DRAM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRA= M_PLL_OUT); + hws[IMX8MP_GPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_= PLL_OUT); + hws[IMX8MP_VPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_= PLL_OUT); + hws[IMX8MP_ARM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_= PLL_OUT); + hws[IMX8MP_SYS_PLL3_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL3_OUT); + + hws[IMX8MP_SYS_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL1_OUT); + + hws[IMX8MP_SYS_PLL1_40M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL1_40M); + hws[IMX8MP_SYS_PLL1_80M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL1_80M); + hws[IMX8MP_SYS_PLL1_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_100M); + hws[IMX8MP_SYS_PLL1_133M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_133M); + hws[IMX8MP_SYS_PLL1_160M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_160M); + hws[IMX8MP_SYS_PLL1_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_200M); + hws[IMX8MP_SYS_PLL1_266M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_266M); + hws[IMX8MP_SYS_PLL1_400M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_400M); + hws[IMX8MP_SYS_PLL1_800M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL1_800M); + + hws[IMX8MP_SYS_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL2_OUT); + + hws[IMX8MP_SYS_PLL2_50M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS= _PLL2_50M); + hws[IMX8MP_SYS_PLL2_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_100M); + hws[IMX8MP_SYS_PLL2_125M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_125M); + hws[IMX8MP_SYS_PLL2_166M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_166M); + hws[IMX8MP_SYS_PLL2_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_200M); + hws[IMX8MP_SYS_PLL2_250M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_250M); + hws[IMX8MP_SYS_PLL2_333M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_333M); + hws[IMX8MP_SYS_PLL2_500M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SY= S_PLL2_500M); + hws[IMX8MP_SYS_PLL2_1000M] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_S= YS_PLL2_1000M); + + hws[IMX8MP_CLK_CLKOUT1_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT1_SEL); + hws[IMX8MP_CLK_CLKOUT1_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT1_DIV); + hws[IMX8MP_CLK_CLKOUT1] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_= CLKOUT1); + hws[IMX8MP_CLK_CLKOUT2_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT2_SEL); + hws[IMX8MP_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT2_DIV); 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[79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:24 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 20/23] clk: imx8mp: rename ccm_base to base Date: Sat, 18 Jan 2025 13:40:03 +0100 Message-ID: <20250118124044.157308-21-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The old code also accessed the anatop address space and therefore used the variables anatop_base and ccm_base to distinguish between the two address spaces. However, now that a specific anatop driver exists for the i.MX8MP platform, the variable ccm_base can be renamed to base, as is usually the case for the variable pointing to the memory region managed by a Linux driver. The patch does not introduce any functional changes. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 378 +++++++++++++++++------------------ 1 file changed, 189 insertions(+), 189 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 9dda576e5fbd..012cd3b52e3f 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -392,12 +392,12 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; - void __iomem *ccm_base; + void __iomem *base; int err; =20 - ccm_base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(ccm_base))) - return PTR_ERR(ccm_base); + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CL= K_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -493,198 +493,198 @@ static int imx8mp_clocks_probe(struct platform_devi= ce *pdev) hws[IMX8MP_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT2_DIV); hws[IMX8MP_CLK_CLKOUT2] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_= CLKOUT2); =20 - hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mp_a53_sels, ccm_base + 0x8000); + hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mp_a53_sels, base + 0x8000); hws[IMX8MP_CLK_A53_SRC] =3D hws[IMX8MP_CLK_A53_DIV]; hws[IMX8MP_CLK_A53_CG] =3D hws[IMX8MP_CLK_A53_DIV]; - hws[IMX8MP_CLK_M7_CORE] =3D imx8m_clk_hw_composite_core("m7_core", imx8mp= _m7_sels, ccm_base + 0x8080); - hws[IMX8MP_CLK_ML_CORE] =3D imx8m_clk_hw_composite_core("ml_core", imx8mp= _ml_sels, ccm_base + 0x8100); - hws[IMX8MP_CLK_GPU3D_CORE] =3D imx8m_clk_hw_composite_core("gpu3d_core", = imx8mp_gpu3d_core_sels, ccm_base + 0x8180); - hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =3D imx8m_clk_hw_composite("gpu3d_shade= r_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200); - hws[IMX8MP_CLK_GPU2D_CORE] =3D imx8m_clk_hw_composite("gpu2d_core", imx8m= p_gpu2d_sels, ccm_base + 0x8280); - hws[IMX8MP_CLK_AUDIO_AXI] =3D imx8m_clk_hw_composite("audio_axi", imx8mp_= audio_axi_sels, ccm_base + 0x8300); + hws[IMX8MP_CLK_M7_CORE] =3D imx8m_clk_hw_composite_core("m7_core", imx8mp= _m7_sels, base + 0x8080); + hws[IMX8MP_CLK_ML_CORE] =3D imx8m_clk_hw_composite_core("ml_core", imx8mp= _ml_sels, base + 0x8100); + hws[IMX8MP_CLK_GPU3D_CORE] =3D imx8m_clk_hw_composite_core("gpu3d_core", = imx8mp_gpu3d_core_sels, base + 0x8180); + hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =3D imx8m_clk_hw_composite("gpu3d_shade= r_core", imx8mp_gpu3d_shader_sels, base + 0x8200); + hws[IMX8MP_CLK_GPU2D_CORE] =3D imx8m_clk_hw_composite("gpu2d_core", imx8m= p_gpu2d_sels, base + 0x8280); + hws[IMX8MP_CLK_AUDIO_AXI] =3D imx8m_clk_hw_composite("audio_axi", imx8mp_= audio_axi_sels, base + 0x8300); hws[IMX8MP_CLK_AUDIO_AXI_SRC] =3D hws[IMX8MP_CLK_AUDIO_AXI]; - hws[IMX8MP_CLK_HSIO_AXI] =3D imx8m_clk_hw_composite("hsio_axi", imx8mp_hs= io_axi_sels, ccm_base + 0x8380); - hws[IMX8MP_CLK_MEDIA_ISP] =3D imx8m_clk_hw_composite("media_isp", imx8mp_= media_isp_sels, ccm_base + 0x8400); + hws[IMX8MP_CLK_HSIO_AXI] =3D imx8m_clk_hw_composite("hsio_axi", imx8mp_hs= io_axi_sels, base + 0x8380); + hws[IMX8MP_CLK_MEDIA_ISP] =3D imx8m_clk_hw_composite("media_isp", imx8mp_= media_isp_sels, base + 0x8400); =20 /* CORE SEL */ - hws[IMX8MP_CLK_A53_CORE] =3D imx_clk_hw_mux2("arm_a53_core", ccm_base + 0= x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); - - hws[IMX8MP_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_bus_critical("main_ax= i", imx8mp_main_axi_sels, ccm_base + 0x8800); - hws[IMX8MP_CLK_ENET_AXI] =3D imx8m_clk_hw_composite_bus("enet_axi", imx8m= p_enet_axi_sels, ccm_base + 0x8880); - hws[IMX8MP_CLK_NAND_USDHC_BUS] =3D imx8m_clk_hw_composite("nand_usdhc_bus= ", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); - hws[IMX8MP_CLK_VPU_BUS] =3D imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_= vpu_bus_sels, ccm_base + 0x8980); - hws[IMX8MP_CLK_MEDIA_AXI] =3D imx8m_clk_hw_composite_bus("media_axi", imx= 8mp_media_axi_sels, ccm_base + 0x8a00); - hws[IMX8MP_CLK_MEDIA_APB] =3D imx8m_clk_hw_composite_bus("media_apb", imx= 8mp_media_apb_sels, ccm_base + 0x8a80); - hws[IMX8MP_CLK_HDMI_APB] =3D imx8m_clk_hw_composite_bus("hdmi_apb", imx8m= p_media_apb_sels, ccm_base + 0x8b00); - hws[IMX8MP_CLK_HDMI_AXI] =3D imx8m_clk_hw_composite_bus("hdmi_axi", imx8m= p_media_axi_sels, ccm_base + 0x8b80); - hws[IMX8MP_CLK_GPU_AXI] =3D imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_= gpu_axi_sels, ccm_base + 0x8c00); - hws[IMX8MP_CLK_GPU_AHB] =3D imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_= gpu_ahb_sels, ccm_base + 0x8c80); - hws[IMX8MP_CLK_NOC] =3D imx8m_clk_hw_composite_bus_critical("noc", imx8mp= _noc_sels, ccm_base + 0x8d00); - hws[IMX8MP_CLK_NOC_IO] =3D imx8m_clk_hw_composite_bus_critical("noc_io", = imx8mp_noc_io_sels, ccm_base + 0x8d80); - hws[IMX8MP_CLK_ML_AXI] =3D imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml= _axi_sels, ccm_base + 0x8e00); - hws[IMX8MP_CLK_ML_AHB] =3D imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml= _ahb_sels, ccm_base + 0x8e80); - - hws[IMX8MP_CLK_AHB] =3D imx8m_clk_hw_composite_bus_critical("ahb_root", i= mx8mp_ahb_sels, ccm_base + 0x9000); - hws[IMX8MP_CLK_AUDIO_AHB] =3D imx8m_clk_hw_composite_bus("audio_ahb", imx= 8mp_audio_ahb_sels, ccm_base + 0x9100); - hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] =3D imx8m_clk_hw_composite_bus("mipi_dsi_= esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_= PARENT); - - hws[IMX8MP_CLK_IPG_ROOT] =3D imx_clk_hw_divider2("ipg_root", "ahb_root", = ccm_base + 0x9080, 0, 1); - - hws[IMX8MP_CLK_DRAM_ALT] =3D imx8m_clk_hw_fw_managed_composite("dram_alt"= , imx8mp_dram_alt_sels, ccm_base + 0xa000); - hws[IMX8MP_CLK_DRAM_APB] =3D imx8m_clk_hw_fw_managed_composite_critical("= dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); - hws[IMX8MP_CLK_VPU_G1] =3D imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1= _sels, ccm_base + 0xa100); - hws[IMX8MP_CLK_VPU_G2] =3D imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2= _sels, ccm_base + 0xa180); - hws[IMX8MP_CLK_CAN1] =3D imx8m_clk_hw_composite("can1", imx8mp_can1_sels,= ccm_base + 0xa200); - hws[IMX8MP_CLK_CAN2] =3D imx8m_clk_hw_composite("can2", imx8mp_can2_sels,= ccm_base + 0xa280); - hws[IMX8MP_CLK_PCIE_AUX] =3D imx8m_clk_hw_composite("pcie_aux", imx8mp_pc= ie_aux_sels, ccm_base + 0xa400); - hws[IMX8MP_CLK_I2C5] =3D imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels,= ccm_base + 0xa480); - hws[IMX8MP_CLK_I2C6] =3D imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels,= ccm_base + 0xa500); - hws[IMX8MP_CLK_SAI1] =3D imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels,= ccm_base + 0xa580); - hws[IMX8MP_CLK_SAI2] =3D imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels,= ccm_base + 0xa600); - hws[IMX8MP_CLK_SAI3] =3D imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels,= ccm_base + 0xa680); - hws[IMX8MP_CLK_SAI5] =3D imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels,= ccm_base + 0xa780); - hws[IMX8MP_CLK_SAI6] =3D imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels,= ccm_base + 0xa800); - hws[IMX8MP_CLK_ENET_QOS] =3D imx8m_clk_hw_composite("enet_qos", imx8mp_en= et_qos_sels, ccm_base + 0xa880); - hws[IMX8MP_CLK_ENET_QOS_TIMER] =3D imx8m_clk_hw_composite("enet_qos_timer= ", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900); - hws[IMX8MP_CLK_ENET_REF] =3D imx8m_clk_hw_composite("enet_ref", imx8mp_en= et_ref_sels, ccm_base + 0xa980); - hws[IMX8MP_CLK_ENET_TIMER] =3D imx8m_clk_hw_composite("enet_timer", imx8m= p_enet_timer_sels, ccm_base + 0xaa00); - hws[IMX8MP_CLK_ENET_PHY_REF] =3D imx8m_clk_hw_composite("enet_phy_ref", i= mx8mp_enet_phy_ref_sels, ccm_base + 0xaa80); - hws[IMX8MP_CLK_NAND] =3D imx8m_clk_hw_composite("nand", imx8mp_nand_sels,= ccm_base + 0xab00); - hws[IMX8MP_CLK_QSPI] =3D imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels,= ccm_base + 0xab80); - hws[IMX8MP_CLK_USDHC1] =3D imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1= _sels, ccm_base + 0xac00); - hws[IMX8MP_CLK_USDHC2] =3D imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2= _sels, ccm_base + 0xac80); - hws[IMX8MP_CLK_I2C1] =3D imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels,= ccm_base + 0xad00); - hws[IMX8MP_CLK_I2C2] =3D imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels,= ccm_base + 0xad80); - hws[IMX8MP_CLK_I2C3] =3D imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels,= ccm_base + 0xae00); - hws[IMX8MP_CLK_I2C4] =3D imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels,= ccm_base + 0xae80); - - hws[IMX8MP_CLK_UART1] =3D imx8m_clk_hw_composite("uart1", imx8mp_uart1_se= ls, ccm_base + 0xaf00); - hws[IMX8MP_CLK_UART2] =3D imx8m_clk_hw_composite("uart2", imx8mp_uart2_se= ls, ccm_base + 0xaf80); - hws[IMX8MP_CLK_UART3] =3D imx8m_clk_hw_composite("uart3", imx8mp_uart3_se= ls, ccm_base + 0xb000); - hws[IMX8MP_CLK_UART4] =3D imx8m_clk_hw_composite("uart4", imx8mp_uart4_se= ls, ccm_base + 0xb080); - hws[IMX8MP_CLK_USB_CORE_REF] =3D imx8m_clk_hw_composite("usb_core_ref", i= mx8mp_usb_core_ref_sels, ccm_base + 0xb100); - hws[IMX8MP_CLK_USB_PHY_REF] =3D imx8m_clk_hw_composite("usb_phy_ref", imx= 8mp_usb_phy_ref_sels, ccm_base + 0xb180); - hws[IMX8MP_CLK_GIC] =3D imx8m_clk_hw_composite_critical("gic", imx8mp_gic= _sels, ccm_base + 0xb200); - hws[IMX8MP_CLK_ECSPI1] =3D imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1= _sels, ccm_base + 0xb280); - hws[IMX8MP_CLK_ECSPI2] =3D imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2= _sels, ccm_base + 0xb300); - hws[IMX8MP_CLK_PWM1] =3D imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels,= ccm_base + 0xb380); - hws[IMX8MP_CLK_PWM2] =3D imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels,= ccm_base + 0xb400); - hws[IMX8MP_CLK_PWM3] =3D imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels,= ccm_base + 0xb480); - hws[IMX8MP_CLK_PWM4] =3D imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels,= ccm_base + 0xb500); - - hws[IMX8MP_CLK_GPT1] =3D imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels,= ccm_base + 0xb580); - hws[IMX8MP_CLK_GPT2] =3D imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels,= ccm_base + 0xb600); - hws[IMX8MP_CLK_GPT3] =3D imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels,= ccm_base + 0xb680); - hws[IMX8MP_CLK_GPT4] =3D imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels,= ccm_base + 0xb700); - hws[IMX8MP_CLK_GPT5] =3D imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels,= ccm_base + 0xb780); - hws[IMX8MP_CLK_GPT6] =3D imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels,= ccm_base + 0xb800); - hws[IMX8MP_CLK_WDOG] =3D imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels,= ccm_base + 0xb900); - hws[IMX8MP_CLK_WRCLK] =3D imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_se= ls, ccm_base + 0xb980); - hws[IMX8MP_CLK_IPP_DO_CLKO1] =3D imx8m_clk_hw_composite("ipp_do_clko1", i= mx8mp_ipp_do_clko1_sels, ccm_base + 0xba00); - hws[IMX8MP_CLK_IPP_DO_CLKO2] =3D imx8m_clk_hw_composite("ipp_do_clko2", i= mx8mp_ipp_do_clko2_sels, ccm_base + 0xba80); - hws[IMX8MP_CLK_HDMI_FDCC_TST] =3D imx8m_clk_hw_composite("hdmi_fdcc_tst",= imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00); - hws[IMX8MP_CLK_HDMI_24M] =3D imx8m_clk_hw_composite("hdmi_24m", imx8mp_hd= mi_24m_sels, ccm_base + 0xbb80); - hws[IMX8MP_CLK_HDMI_REF_266M] =3D imx8m_clk_hw_composite("hdmi_ref_266m",= imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00); - hws[IMX8MP_CLK_USDHC3] =3D imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3= _sels, ccm_base + 0xbc80); - hws[IMX8MP_CLK_MEDIA_CAM1_PIX] =3D imx8m_clk_hw_composite("media_cam1_pix= ", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); - hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] =3D imx8m_clk_hw_composite("media_mip= i_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_= PARENT); - hws[IMX8MP_CLK_MEDIA_CAM2_PIX] =3D imx8m_clk_hw_composite("media_cam2_pix= ", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); - hws[IMX8MP_CLK_MEDIA_LDB] =3D imx8m_clk_hw_composite("media_ldb", imx8mp_= media_ldb_sels, ccm_base + 0xbf00); - hws[IMX8MP_CLK_MEMREPAIR] =3D imx8m_clk_hw_composite_critical("mem_repair= ", imx8mp_memrepair_sels, ccm_base + 0xbf80); - hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] =3D imx8m_clk_hw_composite("media_mi= pi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); - hws[IMX8MP_CLK_ECSPI3] =3D imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3= _sels, ccm_base + 0xc180); - hws[IMX8MP_CLK_PDM] =3D imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, cc= m_base + 0xc200); - hws[IMX8MP_CLK_VPU_VC8000E] =3D imx8m_clk_hw_composite("vpu_vc8000e", imx= 8mp_vpu_vc8000e_sels, ccm_base + 0xc280); - hws[IMX8MP_CLK_SAI7] =3D imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels,= ccm_base + 0xc300); + hws[IMX8MP_CLK_A53_CORE] =3D imx_clk_hw_mux2("arm_a53_core", base + 0x988= 0, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); + + hws[IMX8MP_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_bus_critical("main_ax= i", imx8mp_main_axi_sels, base + 0x8800); + hws[IMX8MP_CLK_ENET_AXI] =3D imx8m_clk_hw_composite_bus("enet_axi", imx8m= p_enet_axi_sels, base + 0x8880); + hws[IMX8MP_CLK_NAND_USDHC_BUS] =3D imx8m_clk_hw_composite("nand_usdhc_bus= ", imx8mp_nand_usdhc_sels, base + 0x8900); + hws[IMX8MP_CLK_VPU_BUS] =3D imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_= vpu_bus_sels, base + 0x8980); + hws[IMX8MP_CLK_MEDIA_AXI] =3D imx8m_clk_hw_composite_bus("media_axi", imx= 8mp_media_axi_sels, base + 0x8a00); + hws[IMX8MP_CLK_MEDIA_APB] =3D imx8m_clk_hw_composite_bus("media_apb", imx= 8mp_media_apb_sels, base + 0x8a80); + hws[IMX8MP_CLK_HDMI_APB] =3D imx8m_clk_hw_composite_bus("hdmi_apb", imx8m= p_media_apb_sels, base + 0x8b00); + hws[IMX8MP_CLK_HDMI_AXI] =3D imx8m_clk_hw_composite_bus("hdmi_axi", imx8m= p_media_axi_sels, base + 0x8b80); + hws[IMX8MP_CLK_GPU_AXI] =3D imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_= gpu_axi_sels, base + 0x8c00); + hws[IMX8MP_CLK_GPU_AHB] =3D imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_= gpu_ahb_sels, base + 0x8c80); + hws[IMX8MP_CLK_NOC] =3D imx8m_clk_hw_composite_bus_critical("noc", imx8mp= _noc_sels, base + 0x8d00); + hws[IMX8MP_CLK_NOC_IO] =3D imx8m_clk_hw_composite_bus_critical("noc_io", = imx8mp_noc_io_sels, base + 0x8d80); + hws[IMX8MP_CLK_ML_AXI] =3D imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml= _axi_sels, base + 0x8e00); + hws[IMX8MP_CLK_ML_AHB] =3D imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml= _ahb_sels, base + 0x8e80); + + hws[IMX8MP_CLK_AHB] =3D imx8m_clk_hw_composite_bus_critical("ahb_root", i= mx8mp_ahb_sels, base + 0x9000); + hws[IMX8MP_CLK_AUDIO_AHB] =3D imx8m_clk_hw_composite_bus("audio_ahb", imx= 8mp_audio_ahb_sels, base + 0x9100); + hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] =3D imx8m_clk_hw_composite_bus("mipi_dsi_= esc_rx", imx8mp_mipi_dsi_esc_rx_sels, base + 0x9200); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300, CLK_SET_RATE_PARE= NT); + + hws[IMX8MP_CLK_IPG_ROOT] =3D imx_clk_hw_divider2("ipg_root", "ahb_root", = base + 0x9080, 0, 1); + + hws[IMX8MP_CLK_DRAM_ALT] =3D imx8m_clk_hw_fw_managed_composite("dram_alt"= , imx8mp_dram_alt_sels, base + 0xa000); + hws[IMX8MP_CLK_DRAM_APB] =3D imx8m_clk_hw_fw_managed_composite_critical("= dram_apb", imx8mp_dram_apb_sels, base + 0xa080); + hws[IMX8MP_CLK_VPU_G1] =3D imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1= _sels, base + 0xa100); + hws[IMX8MP_CLK_VPU_G2] =3D imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2= _sels, base + 0xa180); + hws[IMX8MP_CLK_CAN1] =3D imx8m_clk_hw_composite("can1", imx8mp_can1_sels,= base + 0xa200); + hws[IMX8MP_CLK_CAN2] =3D imx8m_clk_hw_composite("can2", imx8mp_can2_sels,= base + 0xa280); + hws[IMX8MP_CLK_PCIE_AUX] =3D imx8m_clk_hw_composite("pcie_aux", imx8mp_pc= ie_aux_sels, base + 0xa400); + hws[IMX8MP_CLK_I2C5] =3D imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels,= base + 0xa480); + hws[IMX8MP_CLK_I2C6] =3D imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels,= base + 0xa500); + hws[IMX8MP_CLK_SAI1] =3D imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels,= base + 0xa580); + hws[IMX8MP_CLK_SAI2] =3D imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels,= base + 0xa600); + hws[IMX8MP_CLK_SAI3] =3D imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels,= base + 0xa680); + hws[IMX8MP_CLK_SAI5] =3D imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels,= base + 0xa780); + hws[IMX8MP_CLK_SAI6] =3D imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels,= base + 0xa800); + hws[IMX8MP_CLK_ENET_QOS] =3D imx8m_clk_hw_composite("enet_qos", imx8mp_en= et_qos_sels, base + 0xa880); + hws[IMX8MP_CLK_ENET_QOS_TIMER] =3D imx8m_clk_hw_composite("enet_qos_timer= ", imx8mp_enet_qos_timer_sels, base + 0xa900); + hws[IMX8MP_CLK_ENET_REF] =3D imx8m_clk_hw_composite("enet_ref", imx8mp_en= et_ref_sels, base + 0xa980); + hws[IMX8MP_CLK_ENET_TIMER] =3D imx8m_clk_hw_composite("enet_timer", imx8m= p_enet_timer_sels, base + 0xaa00); + hws[IMX8MP_CLK_ENET_PHY_REF] =3D imx8m_clk_hw_composite("enet_phy_ref", i= mx8mp_enet_phy_ref_sels, base + 0xaa80); + hws[IMX8MP_CLK_NAND] =3D imx8m_clk_hw_composite("nand", imx8mp_nand_sels,= base + 0xab00); + hws[IMX8MP_CLK_QSPI] =3D imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels,= base + 0xab80); + hws[IMX8MP_CLK_USDHC1] =3D imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1= _sels, base + 0xac00); + hws[IMX8MP_CLK_USDHC2] =3D imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2= _sels, base + 0xac80); + hws[IMX8MP_CLK_I2C1] =3D imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels,= base + 0xad00); + hws[IMX8MP_CLK_I2C2] =3D imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels,= base + 0xad80); + hws[IMX8MP_CLK_I2C3] =3D imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels,= base + 0xae00); + hws[IMX8MP_CLK_I2C4] =3D imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels,= base + 0xae80); + + hws[IMX8MP_CLK_UART1] =3D imx8m_clk_hw_composite("uart1", imx8mp_uart1_se= ls, base + 0xaf00); + hws[IMX8MP_CLK_UART2] =3D imx8m_clk_hw_composite("uart2", imx8mp_uart2_se= ls, base + 0xaf80); + hws[IMX8MP_CLK_UART3] =3D imx8m_clk_hw_composite("uart3", imx8mp_uart3_se= ls, base + 0xb000); + hws[IMX8MP_CLK_UART4] =3D imx8m_clk_hw_composite("uart4", imx8mp_uart4_se= ls, base + 0xb080); + hws[IMX8MP_CLK_USB_CORE_REF] =3D imx8m_clk_hw_composite("usb_core_ref", i= mx8mp_usb_core_ref_sels, base + 0xb100); + hws[IMX8MP_CLK_USB_PHY_REF] =3D imx8m_clk_hw_composite("usb_phy_ref", imx= 8mp_usb_phy_ref_sels, base + 0xb180); + hws[IMX8MP_CLK_GIC] =3D imx8m_clk_hw_composite_critical("gic", imx8mp_gic= _sels, base + 0xb200); + hws[IMX8MP_CLK_ECSPI1] =3D imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1= _sels, base + 0xb280); + hws[IMX8MP_CLK_ECSPI2] =3D imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2= _sels, base + 0xb300); + hws[IMX8MP_CLK_PWM1] =3D imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels,= base + 0xb380); + hws[IMX8MP_CLK_PWM2] =3D imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels,= base + 0xb400); + hws[IMX8MP_CLK_PWM3] =3D imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels,= base + 0xb480); + hws[IMX8MP_CLK_PWM4] =3D imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels,= base + 0xb500); + + hws[IMX8MP_CLK_GPT1] =3D imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels,= base + 0xb580); + hws[IMX8MP_CLK_GPT2] =3D imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels,= base + 0xb600); + hws[IMX8MP_CLK_GPT3] =3D imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels,= base + 0xb680); + hws[IMX8MP_CLK_GPT4] =3D imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels,= base + 0xb700); + hws[IMX8MP_CLK_GPT5] =3D imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels,= base + 0xb780); + hws[IMX8MP_CLK_GPT6] =3D imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels,= base + 0xb800); + hws[IMX8MP_CLK_WDOG] =3D imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels,= base + 0xb900); + hws[IMX8MP_CLK_WRCLK] =3D imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_se= ls, base + 0xb980); + hws[IMX8MP_CLK_IPP_DO_CLKO1] =3D imx8m_clk_hw_composite("ipp_do_clko1", i= mx8mp_ipp_do_clko1_sels, base + 0xba00); + hws[IMX8MP_CLK_IPP_DO_CLKO2] =3D imx8m_clk_hw_composite("ipp_do_clko2", i= mx8mp_ipp_do_clko2_sels, base + 0xba80); + hws[IMX8MP_CLK_HDMI_FDCC_TST] =3D imx8m_clk_hw_composite("hdmi_fdcc_tst",= imx8mp_hdmi_fdcc_tst_sels, base + 0xbb00); + hws[IMX8MP_CLK_HDMI_24M] =3D imx8m_clk_hw_composite("hdmi_24m", imx8mp_hd= mi_24m_sels, base + 0xbb80); + hws[IMX8MP_CLK_HDMI_REF_266M] =3D imx8m_clk_hw_composite("hdmi_ref_266m",= imx8mp_hdmi_ref_266m_sels, base + 0xbc00); + hws[IMX8MP_CLK_USDHC3] =3D imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3= _sels, base + 0xbc80); + hws[IMX8MP_CLK_MEDIA_CAM1_PIX] =3D imx8m_clk_hw_composite("media_cam1_pix= ", imx8mp_media_cam1_pix_sels, base + 0xbd00); + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] =3D imx8m_clk_hw_composite("media_mip= i_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, base + 0xbd80); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00, CLK_SET_RATE_PARE= NT); + hws[IMX8MP_CLK_MEDIA_CAM2_PIX] =3D imx8m_clk_hw_composite("media_cam2_pix= ", imx8mp_media_cam2_pix_sels, base + 0xbe80); + hws[IMX8MP_CLK_MEDIA_LDB] =3D imx8m_clk_hw_composite("media_ldb", imx8mp_= media_ldb_sels, base + 0xbf00); + hws[IMX8MP_CLK_MEMREPAIR] =3D imx8m_clk_hw_composite_critical("mem_repair= ", imx8mp_memrepair_sels, base + 0xbf80); + hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] =3D imx8m_clk_hw_composite("media_mi= pi_test_byte", imx8mp_media_mipi_test_byte_sels, base + 0xc100); + hws[IMX8MP_CLK_ECSPI3] =3D imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3= _sels, base + 0xc180); + hws[IMX8MP_CLK_PDM] =3D imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ba= se + 0xc200); + hws[IMX8MP_CLK_VPU_VC8000E] =3D imx8m_clk_hw_composite("vpu_vc8000e", imx= 8mp_vpu_vc8000e_sels, base + 0xc280); + hws[IMX8MP_CLK_SAI7] =3D imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels,= base + 0xc300); =20 hws[IMX8MP_CLK_DRAM_ALT_ROOT] =3D imx_clk_hw_fixed_factor("dram_alt_root"= , "dram_alt", 1, 4); - hws[IMX8MP_CLK_DRAM_CORE] =3D imx_clk_hw_mux2_flags("dram_core_clk", ccm_= base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_se= ls), CLK_IS_CRITICAL); - - hws[IMX8MP_CLK_DRAM1_ROOT] =3D imx_clk_hw_gate4_flags("dram1_root_clk", "= dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL); - hws[IMX8MP_CLK_ECSPI1_ROOT] =3D imx_clk_hw_gate4("ecspi1_root_clk", "ecsp= i1", ccm_base + 0x4070, 0); - hws[IMX8MP_CLK_ECSPI2_ROOT] =3D imx_clk_hw_gate4("ecspi2_root_clk", "ecsp= i2", ccm_base + 0x4080, 0); - hws[IMX8MP_CLK_ECSPI3_ROOT] =3D imx_clk_hw_gate4("ecspi3_root_clk", "ecsp= i3", ccm_base + 0x4090, 0); - hws[IMX8MP_CLK_ENET1_ROOT] =3D imx_clk_hw_gate4("enet1_root_clk", "enet_a= xi", ccm_base + 0x40a0, 0); - hws[IMX8MP_CLK_GPIO1_ROOT] =3D imx_clk_hw_gate4("gpio1_root_clk", "ipg_ro= ot", ccm_base + 0x40b0, 0); - hws[IMX8MP_CLK_GPIO2_ROOT] =3D imx_clk_hw_gate4("gpio2_root_clk", "ipg_ro= ot", ccm_base + 0x40c0, 0); - hws[IMX8MP_CLK_GPIO3_ROOT] =3D imx_clk_hw_gate4("gpio3_root_clk", "ipg_ro= ot", ccm_base + 0x40d0, 0); - hws[IMX8MP_CLK_GPIO4_ROOT] =3D imx_clk_hw_gate4("gpio4_root_clk", "ipg_ro= ot", ccm_base + 0x40e0, 0); - hws[IMX8MP_CLK_GPIO5_ROOT] =3D imx_clk_hw_gate4("gpio5_root_clk", "ipg_ro= ot", ccm_base + 0x40f0, 0); - hws[IMX8MP_CLK_GPT1_ROOT] =3D imx_clk_hw_gate4("gpt1_root_clk", "gpt1", c= cm_base + 0x4100, 0); - hws[IMX8MP_CLK_GPT2_ROOT] =3D imx_clk_hw_gate4("gpt2_root_clk", "gpt2", c= cm_base + 0x4110, 0); - hws[IMX8MP_CLK_GPT3_ROOT] =3D imx_clk_hw_gate4("gpt3_root_clk", "gpt3", c= cm_base + 0x4120, 0); - hws[IMX8MP_CLK_GPT4_ROOT] =3D imx_clk_hw_gate4("gpt4_root_clk", "gpt4", c= cm_base + 0x4130, 0); - hws[IMX8MP_CLK_GPT5_ROOT] =3D imx_clk_hw_gate4("gpt5_root_clk", "gpt5", c= cm_base + 0x4140, 0); - hws[IMX8MP_CLK_GPT6_ROOT] =3D imx_clk_hw_gate4("gpt6_root_clk", "gpt6", c= cm_base + 0x4150, 0); - hws[IMX8MP_CLK_I2C1_ROOT] =3D imx_clk_hw_gate4("i2c1_root_clk", "i2c1", c= cm_base + 0x4170, 0); - hws[IMX8MP_CLK_I2C2_ROOT] =3D imx_clk_hw_gate4("i2c2_root_clk", "i2c2", c= cm_base + 0x4180, 0); - hws[IMX8MP_CLK_I2C3_ROOT] =3D imx_clk_hw_gate4("i2c3_root_clk", "i2c3", c= cm_base + 0x4190, 0); - hws[IMX8MP_CLK_I2C4_ROOT] =3D imx_clk_hw_gate4("i2c4_root_clk", "i2c4", c= cm_base + 0x41a0, 0); - hws[IMX8MP_CLK_MU_ROOT] =3D imx_clk_hw_gate4("mu_root_clk", "ipg_root", c= cm_base + 0x4210, 0); - hws[IMX8MP_CLK_OCOTP_ROOT] =3D imx_clk_hw_gate4("ocotp_root_clk", "ipg_ro= ot", ccm_base + 0x4220, 0); - hws[IMX8MP_CLK_PCIE_ROOT] =3D imx_clk_hw_gate4("pcie_root_clk", "pcie_aux= ", ccm_base + 0x4250, 0); - hws[IMX8MP_CLK_PWM1_ROOT] =3D imx_clk_hw_gate4("pwm1_root_clk", "pwm1", c= cm_base + 0x4280, 0); - hws[IMX8MP_CLK_PWM2_ROOT] =3D imx_clk_hw_gate4("pwm2_root_clk", "pwm2", c= cm_base + 0x4290, 0); - hws[IMX8MP_CLK_PWM3_ROOT] =3D imx_clk_hw_gate4("pwm3_root_clk", "pwm3", c= cm_base + 0x42a0, 0); - hws[IMX8MP_CLK_PWM4_ROOT] =3D imx_clk_hw_gate4("pwm4_root_clk", "pwm4", c= cm_base + 0x42b0, 0); - hws[IMX8MP_CLK_QOS_ROOT] =3D imx_clk_hw_gate4("qos_root_clk", "ipg_root",= ccm_base + 0x42c0, 0); - hws[IMX8MP_CLK_QOS_ENET_ROOT] =3D imx_clk_hw_gate4("qos_enet_root_clk", "= ipg_root", ccm_base + 0x42e0, 0); - hws[IMX8MP_CLK_QSPI_ROOT] =3D imx_clk_hw_gate4("qspi_root_clk", "qspi", c= cm_base + 0x42f0, 0); - hws[IMX8MP_CLK_NAND_ROOT] =3D imx_clk_hw_gate2_shared2("nand_root_clk", "= nand", ccm_base + 0x4300, 0, &share_count_nand); - hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] =3D imx_clk_hw_gate2_shared2("= nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_cou= nt_nand); - hws[IMX8MP_CLK_I2C5_ROOT] =3D imx_clk_hw_gate2("i2c5_root_clk", "i2c5", c= cm_base + 0x4330, 0); - hws[IMX8MP_CLK_I2C6_ROOT] =3D imx_clk_hw_gate2("i2c6_root_clk", "i2c6", c= cm_base + 0x4340, 0); - hws[IMX8MP_CLK_CAN1_ROOT] =3D imx_clk_hw_gate2("can1_root_clk", "can1", c= cm_base + 0x4350, 0); - hws[IMX8MP_CLK_CAN2_ROOT] =3D imx_clk_hw_gate2("can2_root_clk", "can2", c= cm_base + 0x4360, 0); - hws[IMX8MP_CLK_SDMA1_ROOT] =3D imx_clk_hw_gate4("sdma1_root_clk", "ipg_ro= ot", ccm_base + 0x43a0, 0); - hws[IMX8MP_CLK_SIM_ENET_ROOT] =3D imx_clk_hw_gate4("sim_enet_root_clk", "= enet_axi", ccm_base + 0x4400, 0); - hws[IMX8MP_CLK_ENET_QOS_ROOT] =3D imx_clk_hw_gate4("enet_qos_root_clk", "= sim_enet_root_clk", ccm_base + 0x43b0, 0); - hws[IMX8MP_CLK_GPU2D_ROOT] =3D imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_= core", ccm_base + 0x4450, 0); - hws[IMX8MP_CLK_GPU3D_ROOT] =3D imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_= core", ccm_base + 0x4460, 0); - hws[IMX8MP_CLK_UART1_ROOT] =3D imx_clk_hw_gate4("uart1_root_clk", "uart1"= , ccm_base + 0x4490, 0); - hws[IMX8MP_CLK_UART2_ROOT] =3D imx_clk_hw_gate4("uart2_root_clk", "uart2"= , ccm_base + 0x44a0, 0); - hws[IMX8MP_CLK_UART3_ROOT] =3D imx_clk_hw_gate4("uart3_root_clk", "uart3"= , ccm_base + 0x44b0, 0); - hws[IMX8MP_CLK_UART4_ROOT] =3D imx_clk_hw_gate4("uart4_root_clk", "uart4"= , ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] =3D imx_clk_hw_gate2_shared2("usb_root_clk", "hs= io_axi", ccm_base + 0x44d0, 0, &share_count_usb); - hws[IMX8MP_CLK_USB_SUSP] =3D imx_clk_hw_gate2_shared2("usb_suspend_clk", = "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb); - hws[IMX8MP_CLK_USB_PHY_ROOT] =3D imx_clk_hw_gate4("usb_phy_root_clk", "us= b_phy_ref", ccm_base + 0x44f0, 0); - hws[IMX8MP_CLK_USDHC1_ROOT] =3D imx_clk_hw_gate4("usdhc1_root_clk", "usdh= c1", ccm_base + 0x4510, 0); - hws[IMX8MP_CLK_USDHC2_ROOT] =3D imx_clk_hw_gate4("usdhc2_root_clk", "usdh= c2", ccm_base + 0x4520, 0); - hws[IMX8MP_CLK_WDOG1_ROOT] =3D imx_clk_hw_gate4("wdog1_root_clk", "wdog",= ccm_base + 0x4530, 0); - hws[IMX8MP_CLK_WDOG2_ROOT] =3D imx_clk_hw_gate4("wdog2_root_clk", "wdog",= ccm_base + 0x4540, 0); - hws[IMX8MP_CLK_WDOG3_ROOT] =3D imx_clk_hw_gate4("wdog3_root_clk", "wdog",= ccm_base + 0x4550, 0); - hws[IMX8MP_CLK_VPU_G1_ROOT] =3D imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_= g1", ccm_base + 0x4560, 0); - hws[IMX8MP_CLK_GPU_ROOT] =3D imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", = ccm_base + 0x4570, 0); - hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =3D imx_clk_hw_gate4("vpu_vc8ke_root_clk",= "vpu_vc8000e", ccm_base + 0x4590, 0); - hws[IMX8MP_CLK_VPU_G2_ROOT] =3D imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_= g2", ccm_base + 0x45a0, 0); - hws[IMX8MP_CLK_NPU_ROOT] =3D imx_clk_hw_gate4("npu_root_clk", "ml_core", = ccm_base + 0x45b0, 0); - hws[IMX8MP_CLK_HSIO_ROOT] =3D imx_clk_hw_gate4("hsio_root_clk", "ipg_root= ", ccm_base + 0x45c0, 0); - hws[IMX8MP_CLK_MEDIA_APB_ROOT] =3D imx_clk_hw_gate2_shared2("media_apb_ro= ot_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("media_axi_ro= ot_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_med= ia); - hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_med= ia); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_= media); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_= media); - hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] =3D imx_clk_hw_gate2_shared2("me= dia_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &shar= e_count_media); - hws[IMX8MP_CLK_MEDIA_LDB_ROOT] =3D imx_clk_hw_gate2_shared2("media_ldb_ro= ot_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =3D imx_clk_hw_gate2_shared2("media_isp_ro= ot_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media); - - hws[IMX8MP_CLK_USDHC3_ROOT] =3D imx_clk_hw_gate4("usdhc3_root_clk", "usdh= c3", ccm_base + 0x45e0, 0); - hws[IMX8MP_CLK_HDMI_ROOT] =3D imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi= ", ccm_base + 0x45f0, 0); - hws[IMX8MP_CLK_TSENSOR_ROOT] =3D imx_clk_hw_gate4("tsensor_root_clk", "ip= g_root", ccm_base + 0x4620, 0); - hws[IMX8MP_CLK_VPU_ROOT] =3D imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", = ccm_base + 0x4630, 0); - - hws[IMX8MP_CLK_AUDIO_AHB_ROOT] =3D imx_clk_hw_gate2_shared2("audio_ahb_ro= ot", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_AUDIO_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("audio_axi_ro= ot", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI1_ROOT] =3D imx_clk_hw_gate2_shared2("sai1_root", "sai1= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI2_ROOT] =3D imx_clk_hw_gate2_shared2("sai2_root", "sai2= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI3_ROOT] =3D imx_clk_hw_gate2_shared2("sai3_root", "sai3= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI5_ROOT] =3D imx_clk_hw_gate2_shared2("sai5_root", "sai5= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI6_ROOT] =3D imx_clk_hw_gate2_shared2("sai6_root", "sai6= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI7_ROOT] =3D imx_clk_hw_gate2_shared2("sai7_root", "sai7= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_PDM_ROOT] =3D imx_clk_hw_gate2_shared2("pdm_root", "pdm", = ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_DRAM_CORE] =3D imx_clk_hw_mux2_flags("dram_core_clk", base= + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels),= CLK_IS_CRITICAL); + + hws[IMX8MP_CLK_DRAM1_ROOT] =3D imx_clk_hw_gate4_flags("dram1_root_clk", "= dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL); + hws[IMX8MP_CLK_ECSPI1_ROOT] =3D imx_clk_hw_gate4("ecspi1_root_clk", "ecsp= i1", base + 0x4070, 0); + hws[IMX8MP_CLK_ECSPI2_ROOT] =3D imx_clk_hw_gate4("ecspi2_root_clk", "ecsp= i2", base + 0x4080, 0); + hws[IMX8MP_CLK_ECSPI3_ROOT] =3D imx_clk_hw_gate4("ecspi3_root_clk", "ecsp= i3", base + 0x4090, 0); + hws[IMX8MP_CLK_ENET1_ROOT] =3D imx_clk_hw_gate4("enet1_root_clk", "enet_a= xi", base + 0x40a0, 0); + hws[IMX8MP_CLK_GPIO1_ROOT] =3D imx_clk_hw_gate4("gpio1_root_clk", "ipg_ro= ot", base + 0x40b0, 0); + hws[IMX8MP_CLK_GPIO2_ROOT] =3D imx_clk_hw_gate4("gpio2_root_clk", "ipg_ro= ot", base + 0x40c0, 0); + hws[IMX8MP_CLK_GPIO3_ROOT] =3D imx_clk_hw_gate4("gpio3_root_clk", "ipg_ro= ot", base + 0x40d0, 0); + hws[IMX8MP_CLK_GPIO4_ROOT] =3D imx_clk_hw_gate4("gpio4_root_clk", "ipg_ro= ot", base + 0x40e0, 0); + hws[IMX8MP_CLK_GPIO5_ROOT] =3D imx_clk_hw_gate4("gpio5_root_clk", "ipg_ro= ot", base + 0x40f0, 0); + hws[IMX8MP_CLK_GPT1_ROOT] =3D imx_clk_hw_gate4("gpt1_root_clk", "gpt1", b= ase + 0x4100, 0); + hws[IMX8MP_CLK_GPT2_ROOT] =3D imx_clk_hw_gate4("gpt2_root_clk", "gpt2", b= ase + 0x4110, 0); + hws[IMX8MP_CLK_GPT3_ROOT] =3D imx_clk_hw_gate4("gpt3_root_clk", "gpt3", b= ase + 0x4120, 0); + hws[IMX8MP_CLK_GPT4_ROOT] =3D imx_clk_hw_gate4("gpt4_root_clk", "gpt4", b= ase + 0x4130, 0); + hws[IMX8MP_CLK_GPT5_ROOT] =3D imx_clk_hw_gate4("gpt5_root_clk", "gpt5", b= ase + 0x4140, 0); + hws[IMX8MP_CLK_GPT6_ROOT] =3D imx_clk_hw_gate4("gpt6_root_clk", "gpt6", b= ase + 0x4150, 0); + hws[IMX8MP_CLK_I2C1_ROOT] =3D imx_clk_hw_gate4("i2c1_root_clk", "i2c1", b= ase + 0x4170, 0); + hws[IMX8MP_CLK_I2C2_ROOT] =3D imx_clk_hw_gate4("i2c2_root_clk", "i2c2", b= ase + 0x4180, 0); + hws[IMX8MP_CLK_I2C3_ROOT] =3D imx_clk_hw_gate4("i2c3_root_clk", "i2c3", b= ase + 0x4190, 0); + hws[IMX8MP_CLK_I2C4_ROOT] =3D imx_clk_hw_gate4("i2c4_root_clk", "i2c4", b= ase + 0x41a0, 0); + hws[IMX8MP_CLK_MU_ROOT] =3D imx_clk_hw_gate4("mu_root_clk", "ipg_root", b= ase + 0x4210, 0); + hws[IMX8MP_CLK_OCOTP_ROOT] =3D imx_clk_hw_gate4("ocotp_root_clk", "ipg_ro= ot", base + 0x4220, 0); + hws[IMX8MP_CLK_PCIE_ROOT] =3D imx_clk_hw_gate4("pcie_root_clk", "pcie_aux= ", base + 0x4250, 0); + hws[IMX8MP_CLK_PWM1_ROOT] =3D imx_clk_hw_gate4("pwm1_root_clk", "pwm1", b= ase + 0x4280, 0); + hws[IMX8MP_CLK_PWM2_ROOT] =3D imx_clk_hw_gate4("pwm2_root_clk", "pwm2", b= ase + 0x4290, 0); + hws[IMX8MP_CLK_PWM3_ROOT] =3D imx_clk_hw_gate4("pwm3_root_clk", "pwm3", b= ase + 0x42a0, 0); + hws[IMX8MP_CLK_PWM4_ROOT] =3D imx_clk_hw_gate4("pwm4_root_clk", "pwm4", b= ase + 0x42b0, 0); + hws[IMX8MP_CLK_QOS_ROOT] =3D imx_clk_hw_gate4("qos_root_clk", "ipg_root",= base + 0x42c0, 0); + hws[IMX8MP_CLK_QOS_ENET_ROOT] =3D imx_clk_hw_gate4("qos_enet_root_clk", "= ipg_root", base + 0x42e0, 0); + hws[IMX8MP_CLK_QSPI_ROOT] =3D imx_clk_hw_gate4("qspi_root_clk", "qspi", b= ase + 0x42f0, 0); + hws[IMX8MP_CLK_NAND_ROOT] =3D imx_clk_hw_gate2_shared2("nand_root_clk", "= nand", base + 0x4300, 0, &share_count_nand); + hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] =3D imx_clk_hw_gate2_shared2("= nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_n= and); + hws[IMX8MP_CLK_I2C5_ROOT] =3D imx_clk_hw_gate2("i2c5_root_clk", "i2c5", b= ase + 0x4330, 0); + hws[IMX8MP_CLK_I2C6_ROOT] =3D imx_clk_hw_gate2("i2c6_root_clk", "i2c6", b= ase + 0x4340, 0); + hws[IMX8MP_CLK_CAN1_ROOT] =3D imx_clk_hw_gate2("can1_root_clk", "can1", b= ase + 0x4350, 0); + hws[IMX8MP_CLK_CAN2_ROOT] =3D imx_clk_hw_gate2("can2_root_clk", "can2", b= ase + 0x4360, 0); + hws[IMX8MP_CLK_SDMA1_ROOT] =3D imx_clk_hw_gate4("sdma1_root_clk", "ipg_ro= ot", base + 0x43a0, 0); + hws[IMX8MP_CLK_SIM_ENET_ROOT] =3D imx_clk_hw_gate4("sim_enet_root_clk", "= enet_axi", base + 0x4400, 0); + hws[IMX8MP_CLK_ENET_QOS_ROOT] =3D imx_clk_hw_gate4("enet_qos_root_clk", "= sim_enet_root_clk", base + 0x43b0, 0); + hws[IMX8MP_CLK_GPU2D_ROOT] =3D imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_= core", base + 0x4450, 0); + hws[IMX8MP_CLK_GPU3D_ROOT] =3D imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_= core", base + 0x4460, 0); + hws[IMX8MP_CLK_UART1_ROOT] =3D imx_clk_hw_gate4("uart1_root_clk", "uart1"= , base + 0x4490, 0); + hws[IMX8MP_CLK_UART2_ROOT] =3D imx_clk_hw_gate4("uart2_root_clk", "uart2"= , base + 0x44a0, 0); + hws[IMX8MP_CLK_UART3_ROOT] =3D imx_clk_hw_gate4("uart3_root_clk", "uart3"= , base + 0x44b0, 0); + hws[IMX8MP_CLK_UART4_ROOT] =3D imx_clk_hw_gate4("uart4_root_clk", "uart4"= , base + 0x44c0, 0); + hws[IMX8MP_CLK_USB_ROOT] =3D imx_clk_hw_gate2_shared2("usb_root_clk", "hs= io_axi", base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_SUSP] =3D imx_clk_hw_gate2_shared2("usb_suspend_clk", = "osc_32k", base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_PHY_ROOT] =3D imx_clk_hw_gate4("usb_phy_root_clk", "us= b_phy_ref", base + 0x44f0, 0); + hws[IMX8MP_CLK_USDHC1_ROOT] =3D imx_clk_hw_gate4("usdhc1_root_clk", "usdh= c1", base + 0x4510, 0); + hws[IMX8MP_CLK_USDHC2_ROOT] =3D imx_clk_hw_gate4("usdhc2_root_clk", "usdh= c2", base + 0x4520, 0); + hws[IMX8MP_CLK_WDOG1_ROOT] =3D imx_clk_hw_gate4("wdog1_root_clk", "wdog",= base + 0x4530, 0); + hws[IMX8MP_CLK_WDOG2_ROOT] =3D imx_clk_hw_gate4("wdog2_root_clk", "wdog",= base + 0x4540, 0); + hws[IMX8MP_CLK_WDOG3_ROOT] =3D imx_clk_hw_gate4("wdog3_root_clk", "wdog",= base + 0x4550, 0); + hws[IMX8MP_CLK_VPU_G1_ROOT] =3D imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_= g1", base + 0x4560, 0); + hws[IMX8MP_CLK_GPU_ROOT] =3D imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", = base + 0x4570, 0); + hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =3D imx_clk_hw_gate4("vpu_vc8ke_root_clk",= "vpu_vc8000e", base + 0x4590, 0); + hws[IMX8MP_CLK_VPU_G2_ROOT] =3D imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_= g2", base + 0x45a0, 0); + hws[IMX8MP_CLK_NPU_ROOT] =3D imx_clk_hw_gate4("npu_root_clk", "ml_core", = base + 0x45b0, 0); + hws[IMX8MP_CLK_HSIO_ROOT] =3D imx_clk_hw_gate4("hsio_root_clk", "ipg_root= ", base + 0x45c0, 0); + hws[IMX8MP_CLK_MEDIA_APB_ROOT] =3D imx_clk_hw_gate2_shared2("media_apb_ro= ot_clk", "media_apb", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("media_axi_ro= ot_clk", "media_axi", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am1_pix_root_clk", "media_cam1_pix", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am2_pix_root_clk", "media_cam2_pix", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_medi= a); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_medi= a); + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] =3D imx_clk_hw_gate2_shared2("me= dia_mipi_phy1_ref_root", "media_mipi_phy1_ref", base + 0x45d0, 0, &share_co= unt_media); + hws[IMX8MP_CLK_MEDIA_LDB_ROOT] =3D imx_clk_hw_gate2_shared2("media_ldb_ro= ot_clk", "media_ldb", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =3D imx_clk_hw_gate2_shared2("media_isp_ro= ot_clk", "media_isp", base + 0x45d0, 0, &share_count_media); + + hws[IMX8MP_CLK_USDHC3_ROOT] =3D imx_clk_hw_gate4("usdhc3_root_clk", "usdh= c3", base + 0x45e0, 0); + hws[IMX8MP_CLK_HDMI_ROOT] =3D imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi= ", base + 0x45f0, 0); + hws[IMX8MP_CLK_TSENSOR_ROOT] =3D imx_clk_hw_gate4("tsensor_root_clk", "ip= g_root", base + 0x4620, 0); + hws[IMX8MP_CLK_VPU_ROOT] =3D imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", = base + 0x4630, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] =3D imx_clk_hw_gate2_shared2("audio_ahb_ro= ot", "audio_ahb", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("audio_axi_ro= ot", "audio_axi", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] =3D imx_clk_hw_gate2_shared2("sai1_root", "sai1= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] =3D imx_clk_hw_gate2_shared2("sai2_root", "sai2= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] =3D imx_clk_hw_gate2_shared2("sai3_root", "sai3= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] =3D imx_clk_hw_gate2_shared2("sai5_root", "sai5= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] =3D imx_clk_hw_gate2_shared2("sai6_root", "sai6= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] =3D imx_clk_hw_gate2_shared2("sai7_root", "sai7= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] =3D imx_clk_hw_gate2_shared2("pdm_root", "pdm", = base + 0x4650, 0, &share_count_audio); =20 hws[IMX8MP_CLK_ARM] =3D imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 149561DEFDC for ; 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Sat, 18 Jan 2025 04:41:26 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:25 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 21/23] clk: imx8mp: support spread spectrum clock generation Date: Sat, 18 Jan 2025 13:40:04 +0100 Message-ID: <20250118124044.157308-22-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 012cd3b52e3f..560f51d9232d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -393,6 +393,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int err; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -432,9 +433,21 @@ static int imx8mp_clocks_probe(struct platform_device = *pdev) hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP= _SYS_PLL3_REF_SEL); =20 hws[IMX8MP_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO= _PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL1], &ssc_conf); + hws[IMX8MP_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO= _PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL2], &ssc_conf); + hws[IMX8MP_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_= PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_VIDEO_PLL], &ssc_conf); + hws[IMX8MP_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PL= L); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MP_DRAM_PLL], &ssc_conf); + hws[IMX8MP_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL); hws[IMX8MP_VPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL); hws[IMX8MP_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL); --=20 2.43.0 From nobody Sun Feb 8 02:42:08 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2C541DEFF3 for ; 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Sat, 18 Jan 2025 04:41:27 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:27 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 22/23] clk: imx: add support for i.MX8MM anatop clock driver Date: Sat, 18 Jan 2025 13:40:05 +0100 Message-ID: <20250118124044.157308-23-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mm-anatop.c | 287 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mm.c | 172 ++++++++--------- 3 files changed, 367 insertions(+), 94 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mm-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 0c28a4727e9c..311a557900a9 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -25,7 +25,7 @@ mxc-clk-objs +=3D clk-sscg-pll.o mxc-clk-objs +=3D clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 -obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o +obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm-anatop.o clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp-anatop.o clk-imx8mp.o clk-imx8mp-= audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mm-anatop.c b/drivers/clk/imx/clk-imx8= mm-anatop.c new file mode 100644 index 000000000000..4ac870df6370 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mm-anatop.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mm-anatop.c - NXP i.MX8MM anatop clock driver + * + * Copyright (c) 2025 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MM_ANATOP_CLK_END (IMX8MM_ANATOP_CLK_CLKOUT2 + 1) + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mm_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MM_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MM_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MM_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MM_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MM_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MM_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MM_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MM_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MM_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", + base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MM_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", + base + 0x64, &imx_1416x_pll); + hws[IMX8MM_ANATOP_VPU_PLL] =3D + imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MM_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", + base + 0x84, &imx_1416x_pll); + hws[IMX8MM_ANATOP_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MM_ANATOP_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MM_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", + base + 0x114, &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, + vpu_pll_bypass_sels, + ARRAY_SIZE(vpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MM_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MM_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MM_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MM_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MM_ANATOP_VPU_PLL_OUT] =3D + imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", + base + 0x74, 11); + hws[IMX8MM_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MM_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", + base + 0x94, 11); + + hws[IMX8MM_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", + base + 0x104, 11); + + hws[IMX8MM_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MM_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", + base + 0x128, 0, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_SEL] =3D + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MM_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MM_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MM anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mm_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mm-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mm_anatop_clk_of_match); + +static struct platform_driver imx8mm_anatop_clk_driver =3D { + .probe =3D imx8mm_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mm-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mm_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mm_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MM anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 8a1fc7e17ba2..d39de0a81a6f 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -25,16 +25,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; =20 -static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "dumm= y", }; -static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pll1= _ref_sel", }; -static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pll2= _ref_sel", }; -static const char *video_pll_bypass_sels[] =3D {"video_pll", "video_pll_re= f_sel", }; -static const char *dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pll_ref_s= el", }; -static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; -static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; -static const char *arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_ref_sel"= , }; -static const char *sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll3_ref_s= el", }; - /* CCM ROOT */ static const char *imx8mm_a53_sels[] =3D {"osc_24m", "arm_pll_out", "sys_p= ll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -288,21 +278,20 @@ static const char *imx8mm_clko1_sels[] =3D {"osc_24m"= , "sys_pll1_800m", "dummy", " static const char *imx8mm_clko2_sels[] =3D {"osc_24m", "sys_pll2_200m", "s= ys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; =20 static int imx8mm_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; + struct device_node *np =3D dev->of_node, *anp; void __iomem *base; int ret; =20 + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, IMX8MM_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -311,96 +300,92 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MM_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MM_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MM_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MM_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + anp =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MM_CLK_DUMMY] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_DU= MMY); + hws[IMX8MM_CLK_24M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_24M); + hws[IMX8MM_CLK_32K] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_32K); hws[IMX8MM_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MM_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MM_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MM_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); - base =3D of_iomap(np, 0); - of_node_put(np); - if (WARN_ON(!base)) - return -ENOMEM; - - hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); - hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); - hws[IMX8MM_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MM_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MM_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANAT= OP_AUDIO_PLL1_REF_SEL); + hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANAT= OP_AUDIO_PLL2_REF_SEL); + hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_VIDEO_PLL_REF_SEL); + hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _DRAM_PLL_REF_SEL); + hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= GPU_PLL_REF_SEL); + hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= VPU_PLL_REF_SEL); + hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= ARM_PLL_REF_SEL); + hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _SYS_PLL3_REF_SEL); + + hws[IMX8MM_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL1); + hws[IMX8MM_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL2); + hws[IMX8MM_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_= PLL); + hws[IMX8MM_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PL= L); + hws[IMX8MM_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL); + hws[IMX8MM_VPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL); + hws[IMX8MM_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL); + hws[IMX8MM_SYS_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 1); + hws[IMX8MM_SYS_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 2); + hws[IMX8MM_SYS_PLL3] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 3); =20 /* PLL bypass out */ - hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_AUDIO_PLL1_BYPASS); + hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_AUDIO_PLL2_BYPASS); + hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _VIDEO_PLL_BYPASS); + hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= DRAM_PLL_BYPASS); + hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_G= PU_PLL_BYPASS); + hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_V= PU_PLL_BYPASS); + hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= RM_PLL_BYPASS); + hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= SYS_PLL3_BYPASS); =20 /* PLL out gate */ - hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); - hws[IMX8MM_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= UDIO_PLL1_OUT); + hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= UDIO_PLL2_OUT); + hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VI= DEO_PLL_OUT); + hws[IMX8MM_DRAM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRA= M_PLL_OUT); + hws[IMX8MM_GPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_= PLL_OUT); + hws[IMX8MM_VPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_= PLL_OUT); + hws[IMX8MM_ARM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_= PLL_OUT); + hws[IMX8MM_SYS_PLL3_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL3_OUT); =20 /* SYS PLL1 fixed output */ - hws[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); - - hws[IMX8MM_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MM_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MM_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MM_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MM_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MM_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MM_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MM_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MM_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); + hws[IMX8MM_SYS_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_OUT); + + hws[IMX8MM_SYS_PLL1_40M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_40M); + hws[IMX8MM_SYS_PLL1_80M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_80M); + hws[IMX8MM_SYS_PLL1_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_100M); + hws[IMX8MM_SYS_PLL1_133M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_133M); + hws[IMX8MM_SYS_PLL1_160M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_160M); + hws[IMX8MM_SYS_PLL1_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_200M); + hws[IMX8MM_SYS_PLL1_266M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_266M); + hws[IMX8MM_SYS_PLL1_400M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_400M); + hws[IMX8MM_SYS_PLL1_800M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_800M); =20 /* SYS PLL2 fixed output */ - hws[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); - hws[IMX8MM_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MM_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MM_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MM_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MM_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MM_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MM_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MM_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MM_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MM_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MM_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); - - np =3D dev->of_node; - base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) - return PTR_ERR(base); + hws[IMX8MM_SYS_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL2_OUT); + + hws[IMX8MM_SYS_PLL2_50M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL2_50M); + hws[IMX8MM_SYS_PLL2_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_100M); + hws[IMX8MM_SYS_PLL2_125M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_125M); + hws[IMX8MM_SYS_PLL2_166M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_166M); + hws[IMX8MM_SYS_PLL2_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_200M); + hws[IMX8MM_SYS_PLL2_250M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_250M); + hws[IMX8MM_SYS_PLL2_333M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_333M); + hws[IMX8MM_SYS_PLL2_500M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_500M); + hws[IMX8MM_SYS_PLL2_1000M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_S= YS_PLL2_1000M); + + hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT1_SEL); + hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT1_DIV); + hws[IMX8MM_CLK_CLKOUT1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_= CLKOUT1); + hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT2_SEL); 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Sat, 18 Jan 2025 04:41:29 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-30-28-209.retail.telecomitalia.it. [79.30.28.209]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab384fcd73dsm332562366b.178.2025.01.18.04.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jan 2025 04:41:29 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v9 23/23] clk: imx8mm: support spread spectrum clock generation Date: Sat, 18 Jan 2025 13:40:06 +0100 Message-ID: <20250118124044.157308-24-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> References: <20250118124044.157308-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v9: - Add 'Reviewed-by' tag of Peng Fan for imx8mn platform patches - Fix building warning raised by the kernel test robot for patch v8, 11/18 clk: imx: add support for i.MX8MN anatop clock driver - Add patches for imx8m{m,p} platforms: - 23/23 clk: imx8mm: support spread spectrum clock generation - 22/23 clk: imx: add support for i.MX8MM anatop clock driver - 21/23 clk: imx8mp: support spread spectrum clock generation - 20/23 clk: imx8mp: rename ccm_base to base - 19/23 clk: imx: add support for i.MX8MP anatop clock driver Changes in v8: - Drop the patches added in version 7: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v7: - Add and manage fsl,anatop property as phandle to the anatop node with the new patches: - 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop - 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM - 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM - 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM - 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM Changes in v6: - Merge patches: 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop to 05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names now renamed 05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs - Split the patch 15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch into 12/18 dt-bindings: clock: imx8m-clock: add PLLs 16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking Changes in v5: - Fix compilation errors. - Separate driver code from dt-bindings Changes in v4: - Add dt-bindings for anatop - Add anatop driver - Drop fsl,ssc-clocks from spread spectrum dt-bindings Changes in v3: - Patches 1/8 has been added in version 3. The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. - Patches {3,5}/8 have been added in version 3. - Patches {4,6,8}/8 use ccm device node instead of the anatop one. Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. drivers/clk/imx/clk-imx8mm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index d39de0a81a6f..f8413f495d5d 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -286,6 +286,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; void __iomem *base; + struct imx_pll14xx_ssc ssc_conf; int ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -324,9 +325,21 @@ static int imx8mm_clocks_probe(struct platform_device = *pdev) hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _SYS_PLL3_REF_SEL); =20 hws[IMX8MM_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL1); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MM_AUDIO_PLL1], &ssc_conf); + hws[IMX8MM_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL2); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MM_AUDIO_PLL2], &ssc_conf); + hws[IMX8MM_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_= PLL); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MM_VIDEO_PLL], &ssc_conf); + hws[IMX8MM_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PL= L); + if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf)) + imx_clk_pll14xx_enable_ssc(hws[IMX8MM_DRAM_PLL], &ssc_conf); + hws[IMX8MM_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL); hws[IMX8MM_VPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL); hws[IMX8MM_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL); --=20 2.43.0