From nobody Tue Feb 10 19:53:09 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95DB319AD86 for ; Fri, 17 Jan 2025 16:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129705; cv=none; b=eUWBHZT1Cv/Acrnnl25cSbugfFMtLuk67VXpkVVPYl4gFaHGmV0FLDNWe2hHJ4ZawEHabwb+46zgkEyWT0+llmHxDw7DmhzJQhUgzO1kHR1EWXtu+laRqMjGwoJZNlF2NU5CxLY9urt9iyNeXcaoYaaBo6iWZYJj7IKgCOTd8IQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737129705; c=relaxed/simple; bh=PxddNtBEA4VAAhtLK+nYutVGLEKgnoRp41bcJi/iMzA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ULWUAHHZQHHJlUtgmTZJq17Ogvn6KlcpseuBLOMmipCDkRzqqCPcj3X3A7Ot8wvEwqMgdY0QlKmkd6t/NsMclEstnJH80x/Qi16tebqiETu7lsiQWsmbZNsxdz0v4sfpncy9cENofRRxjlh4AJdbSnmhg7J1u1e6X4zKpo18RJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PbMa+uP/; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PbMa+uP/" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-21661be2c2dso45386285ad.1 for ; Fri, 17 Jan 2025 08:01:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737129703; x=1737734503; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MEf37YiQnbvCQ7bZ2njtxuZKF/UJvCXNFAR5fUzDSTs=; b=PbMa+uP/OFC7cViPh8AKhjATMqYbioy3DiOpySZ1bX+VVmrysM8vSyHcexpC+iaSsD 9/U/RFmRX4OMOlPbHnL5o6Zfk69tf/yD9KKqTVcNymcbKDZv3zkYMU9u5wS5qGj4WB3U VYU6Fdss6aKTXNst4mE7M6kmeTmFi4191ZsrvzJWZfdruOZTgUP2zYr5uHq5d2et4SKO jDU9CVtFdYsVHFwPAhjwctt5X4U5RpjU7crHebPplWQR52JR+wdF1rg3LB68ZJD9BT7B 0vDD6QO6zFyVEYsjR1U5rWlNZT91n2iTk5vlKVpvukbwqr+CRPsKDNWNj8wSoPfjyUaM 35mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737129703; x=1737734503; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MEf37YiQnbvCQ7bZ2njtxuZKF/UJvCXNFAR5fUzDSTs=; b=txgEvfkkhsycggagNmMWdHBSJ+89lGuQKfvUXoc2U0GvSZM4v9ClLRu+N4tZCyavfm /wWPwK8wrrp4f5NS9A+wAnA2bBXWoBF/DQv8gFUd+5SGat4x6o5PngLHuQjfV/Cthb2n hAt+aXSihiSkRR0wEfvmDz8fReXH+ooGd3XDnLXXGJF7yPtepjTbeliajCPQXw+Nwmz1 2xuhQsXXgD/LUbpUSOGa0zrIl+egEm4YjL1dEef53nLVsjZeeyRx5ErMvZML+IN4qUKc rqGIu46XcAQNb8F9bqcLg8dIHmPBWp+uQl9ygOJSYmqJ1Cnjh4okIzklqe4Y1DTHDdxX pnyA== X-Forwarded-Encrypted: i=1; AJvYcCW4G6fnx5udaqFIF+P905dMlQ1uEM76D/VukYFAfgQmcGeLbEiRF4YDF6jTvyToCBp7wLrlHsYcBx99IdI=@vger.kernel.org X-Gm-Message-State: AOJu0YwNzyvnt0NEsG/gpCcjv5rrCg0AMaQwjpH+JWTr+1TTgnIy9KMF +nz1DINmvoRzgyqQu9JA5ShWZqoCLRYTq867uLd6OClrmRxHQ6TNv5bQble0eek= X-Gm-Gg: ASbGncsHqR18vPCwEKCl/AgFsNtQYixwttqORUVSpELnrJueX7Rw5r+AFQWIUd0O4BL EFEJCySgGEaaOV+uD9Bf1/OyLev7qjPkFA3y+7a1HxO0Gtyx1KSvyOjaGXCJg8uXyrMMNsfGG28 q2Nhy4cHrffwSak+EoBvlNB+A0yXbZftgi9K1Qh0K2FesIfJGtNQhuy/fZHCwqhuZgvV0w1Be0r Rt42F8fJls9HVUqs+ai80wZbzzMhq0X9SjH+zI6V3Bed7Fdt6Nlww== X-Google-Smtp-Source: AGHT+IEJZ2kI5uBRDML1k/NgyZDQ0oAP/B2bCqDRMPIUXnBmIZcuvSdH13kMnK8Z68XMSLJ3NNyC4Q== X-Received: by 2002:a17:902:ea02:b0:215:19ae:77bf with SMTP id d9443c01a7336-21c355028e9mr53606705ad.19.1737129702982; Fri, 17 Jan 2025 08:01:42 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21c2d3e0df9sm17879755ad.196.2025.01.17.08.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jan 2025 08:01:42 -0800 (PST) From: Jun Nie Date: Sat, 18 Jan 2025 00:00:49 +0800 Subject: [PATCH v5 06/15] drm/msm/dpu: fix mixer number counter on allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-6-9701a16340da@linaro.org> References: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737129659; l=1195; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=PxddNtBEA4VAAhtLK+nYutVGLEKgnoRp41bcJi/iMzA=; b=p8ecOW+PR5hW+4VzbQheLYOLcsmGULaSOX4TeuTvLGFdCcOz3AFZ86zrqMqAnGU6Jcfj8eEgt yEGFx2lO2SlB8pL6GZ0RPhJhob8OZHkj8jiovg3LIPolEOT9T684vwY X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Current code only supports usage cases with one pair of mixers at most. To support quad-pipe usage case, two pairs of mixers need to be reserved. The lm_count for all pairs is cleared if a peer allocation fails in current implementation. Reset the current lm_count to an even number instead of completely clearing it. This prevents all pairs from being cleared in cases where multiple LM pairs are needed. Signed-off-by: Jun Nie Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 24e085437039e..3b3660d0b166d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -321,7 +321,11 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!rm->mixer_blks[i]) continue; =20 - lm_count =3D 0; + /* + * Reset lm_count to an even index. This will drop the previous + * primary mixer if failed to find its peer. + */ + lm_count &=3D ~1; lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, --=20 2.34.1