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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-11-9701a16340da@linaro.org> References: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> In-Reply-To: <20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737129659; l=4903; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=sUuICZ08SQSbhFJWF/1DzEd5meA+YJyjVUzug+zCHWE=; b=XMbzeZ8vKLkKszBj/CrueBgL0Rn9VV3nlJqpBrI8X2Qr+d3eeKrtKvJxNGN0iMHtCLtGLuO5G ei8Uefp5jusDS1BPbHodcm0nC59purvp0tOndC1NucQCxwsVwps4yL4 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The stage contains configuration for a mixer pair. Currently the plane supports just one stage and 2 pipes. Quad-pipe support will require handling 2 stages and 4 pipes at the same time. In preparation for that add a separate define, PIPES_PER_PLANE, to denote number of pipes that can be used by the plane. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 14 +++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 193818b02197d..81474823e6799 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, fetch_active); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index ba7bb05efe9b8..5f010d36672cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 +#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index ef44af5ab681c..d67f2ad20b475 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1078,7 +1078,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 return 0; @@ -1129,7 +1129,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pipe_cfg =3D &pstate->pipe_cfg[0]; r_pipe_cfg =3D &pstate->pipe_cfg[1]; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) @@ -1241,7 +1241,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 @@ -1364,7 +1364,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 /* move the assignment here, to ease handling to another pairs later */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1378,7 +1378,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, =20 pstate->plane_fetch_bw =3D 0; pstate->plane_clk =3D 0; - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1397,7 +1397,7 @@ static void _dpu_plane_atomic_disable(struct drm_plan= e *plane) struct dpu_sw_pipe *pipe; int i; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + for (i =3D 0; i < PIPES_PER_PLANE; i +=3D 1) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1519,7 +1519,7 @@ static void dpu_plane_atomic_print_state(struct drm_p= rinter *p, =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index 052fd046e8463..18ff5ec2603ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -33,8 +33,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; --=20 2.34.1