From nobody Mon Feb 9 13:00:32 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BBCD1DEFCC for ; Fri, 17 Jan 2025 23:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737157333; cv=none; b=Wf1B7z4UpIvUMRwNNJ2pRt9PSgaPhY4QneGe8K7PcG8YOMHJpNhei6PoUXgVtOSDuH0lYinR11LcHl6eO452E9T3NNZtWov52CKkfnRyz7qQD414LxVyRLWbleHo5s/m7fB92d6ITu7KPl0a2tTOrEk8eLq3u4XFrT+wFBp80N0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737157333; c=relaxed/simple; bh=UgNzJe2HpFIZOmF+tKSnwRW92d2shs8YrcRwvXNVrKA=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=DfMOeUq/mQEla863l8bWl+xW6Mbfc8krFOJ/Gc7rSdUU2ortwoh4LYO33nXcor6uFKNzzoDtcas7wGTYSVcdGUANMrMIAbMPeGyJX71qkiE+3l/8OWcptRkorO/8Iqu8tnoFrN4NMLfo3xUMq95LGPUhJZixl3I3bS5MEfJ6UUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=QTQIc0kt; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="QTQIc0kt" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-21648c8601cso47495135ad.2 for ; Fri, 17 Jan 2025 15:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1737157331; x=1737762131; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=F2492f7FPUKL3RQM1y5e+QPeaYBUqrrlq2XUG+1uNeI=; b=QTQIc0ktWy/K/nbmTD2o7Wm9lruGxnLybuSVz6V6GVLsZWOGtFHeWUmKH99HR3rOJx xkJ4WzEiBazESX58cCe9HTKMO6/mvtGF271pbq9SCzYKaPImXrkSa0RqdWQI4hRS+skZ QM+14ha1XE9hvkeJuuStgfC6KXTPoBqC01Wd69lTzYlYpUafMptgAeaYOgFhTUGrQQYs HZxLvbmbAkyEEmdvtTtoRY0SxeXQyk0FsWp89b8NNJC39a3rmDJbym7TjS+AKQTAzNY+ IsFBHjYXYTTn2M67Cx7hsDPSbOrzE8tEy+UWyPP57kkDuZrMQskgInORO0Llj9BxnfnB YX9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737157331; x=1737762131; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=F2492f7FPUKL3RQM1y5e+QPeaYBUqrrlq2XUG+1uNeI=; b=Vg/+80oq0ObymBumMbqvTuIyL+wIHvl8JgIrBh8xNcQKewN0/qz9xSdRiz8oz564L6 zJyWHuUnOTOFAU7Aet28rxMnIB2yQoXi58bkCkQbfbw34UFWH0+v6q+4vs9YiYVYzpa6 S68n7O9IFq4KyOPPh6YVkF8uYnH/kA30dg6lsJ6gqOGi2AnZjJP8DsFbq3sCxbeREZUr jEXQCVTIljmhWL1QrLFMuIXnO9D2ekHaWuqaZNpYbuh0l8Bl0C8Uw0gOXFGUzW+Sx/1G cDj+bg0mg6MX1apFLby2ptgtuLrvb1WIh3TwuQFmp1o7G4rtwI1UxvsYPOF+wjMsRxiJ N2nQ== X-Forwarded-Encrypted: i=1; AJvYcCX59V9otrDERTsBqkKu/nw4w4UBXQqCAkUKiSDF1pL+coFB37rKxbUTo5BrRZs2a9qr97UUmijgjUNBscY=@vger.kernel.org X-Gm-Message-State: AOJu0YxCa9k13t4xpGPy1nevmJs8baj/9XvL0mVHah08/USxs+u49YPU oEV1zaTKFxe+jgUBWobYYA9KTUstJe6VH6jfoqZgBMLyNp+FQGel8ZDyyPOEeVyV6F2z0bD/K9z j8g== X-Google-Smtp-Source: AGHT+IEutRKWetWajOjuPthgKFxwMopyW+ltQmCIIbAd9AjyS3fmj4hN5vvPtxTp1Msub1a8TFENrUJtLiI= X-Received: from pgbcm6.prod.google.com ([2002:a05:6a02:a06:b0:801:d783:5f1e]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:32a3:b0:1e8:bd15:6801 with SMTP id adf61e73a8af0-1eb2158bd23mr7439870637.29.1737157330717; Fri, 17 Jan 2025 15:42:10 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 17 Jan 2025 15:42:01 -0800 In-Reply-To: <20250117234204.2600624-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250117234204.2600624-1-seanjc@google.com> X-Mailer: git-send-email 2.48.0.rc2.279.g1de40edade-goog Message-ID: <20250117234204.2600624-4-seanjc@google.com> Subject: [PATCH 3/5] KVM: selftests: Remove dead code in Intel PMU counters test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the local "nr_arch_events" in the Intel PMU counters test as the test asserts that "nr_arch_events <=3D NR_INTEL_ARCH_EVENTS", and then sets nr_arch_events to the max of the two. I.e. nr_arch_events is guaranteed to be NR_INTEL_ARCH_EVENTS for the meat of the test, just use NR_INTEL_ARCH_EVENTS directly. No functional change intended. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 8159615ad492..5d6a5b9c17b3 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -563,7 +563,6 @@ static void test_fixed_counters(uint8_t pmu_version, ui= nt64_t perf_capabilities, =20 static void test_intel_counters(void) { - uint8_t nr_arch_events =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VEC= TOR_LENGTH); uint8_t nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_= COUNTERS); uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); @@ -588,9 +587,10 @@ static void test_intel_counters(void) * This will (obviously) fail any time hardware adds support for a new * event, but it's worth paying that price to keep the test fresh. */ - TEST_ASSERT(nr_arch_events <=3D NR_INTEL_ARCH_EVENTS, + TEST_ASSERT(this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH) <= =3D NR_INTEL_ARCH_EVENTS, "New architectural event(s) detected; please update this test (lengt= h =3D %u, mask =3D %x)", - nr_arch_events, this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); + this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH), + this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); =20 /* * Iterate over known arch events irrespective of KVM/hardware support @@ -600,8 +600,7 @@ static void test_intel_counters(void) * count correctly, even if *enumeration* of the event is unsupported * by KVM and/or isn't exposed to the guest. */ - nr_arch_events =3D max_t(typeof(nr_arch_events), nr_arch_events, NR_INTEL= _ARCH_EVENTS); - for (i =3D 0; i < nr_arch_events; i++) { + for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) { if (this_pmu_has(intel_event_to_feature(i).gp_event)) hardware_pmu_arch_events |=3D BIT(i); } @@ -620,8 +619,8 @@ static void test_intel_counters(void) * vector length. */ if (v =3D=3D pmu_version) { - for (k =3D 1; k < (BIT(nr_arch_events) - 1); k++) - test_arch_events(v, perf_caps[i], nr_arch_events, k); + for (k =3D 1; k < (BIT(NR_INTEL_ARCH_EVENTS) - 1); k++) + test_arch_events(v, perf_caps[i], NR_INTEL_ARCH_EVENTS, k); } /* * Test single bits for all PMU version and lengths up @@ -630,11 +629,11 @@ static void test_intel_counters(void) * host length). Explicitly test a mask of '0' and all * ones i.e. all events being available and unavailable. */ - for (j =3D 0; j <=3D nr_arch_events + 1; j++) { + for (j =3D 0; j <=3D NR_INTEL_ARCH_EVENTS + 1; j++) { test_arch_events(v, perf_caps[i], j, 0); test_arch_events(v, perf_caps[i], j, 0xff); =20 - for (k =3D 0; k < nr_arch_events; k++) + for (k =3D 0; k < NR_INTEL_ARCH_EVENTS; k++) test_arch_events(v, perf_caps[i], j, BIT(k)); } =20 --=20 2.48.0.rc2.279.g1de40edade-goog