From nobody Mon Feb 9 06:00:03 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29FD11DED45 for ; Fri, 17 Jan 2025 23:42:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737157331; cv=none; b=kHFEh8zlL2hQzqnTMZd6JDZLSBP143qCZOD3U3ruticoGs3L3Zd4L9M3gBLXheR/Iv+lR6Qq7HjBiZeBn+3Y6g4F4LGh8UEWtFJlvXTzjaTNddVkBDwNvSusu/A9DTLFwCKLrZ3G2iX+nDwjZ6rVnx2W1R63lcDAAhFJRCXm720= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737157331; c=relaxed/simple; bh=POfrsUNWIq048XGnB7sBSN8xdPfF9XX/t9xz+NiNUvk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=SoMrE6aTcaLoTa/gM0nk34IIO4VrLN48UiAd06n1UGytT0k9qPVhOM9Wwe7czgYx3xh20IoFIQ7DJgssgSt+Jy45Er6aOOTxefHKgaJk31hCH5HafOmH6EWFfCNSPZ0Tmnc5WGb0d22g9W3cAIoLJFLjsy+X9PB2G9tHPUUQl2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=zaJAw/tq; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="zaJAw/tq" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2f129f7717fso5182323a91.0 for ; Fri, 17 Jan 2025 15:42:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1737157327; x=1737762127; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=u5+M48xEYsPxfpNh5jdjkOZetq5qZE6t5SXp0yc/k2M=; b=zaJAw/tqRmIs1TdEJJKbSEHfCyDrrCvpuUlSbJlAYMOdbIbpo14Y9bEzXe2dicGGGq LyAUYK3RP9IV34VjwqNPg1cgWhnf4dOj0+4qTQ2sC+rF25aCsstuTsNGHaQxHKarKHYe oPoT3BhDCLaTVBB6/NEuCyptJ4EWGuzYmw3Q9heuEjTmZh9PAVH5c8mKjQ+O60wpBNSE rzrsKK+vqkTju3zg6J1zXX8Aw+QRukvfWOazSpha9ceqfa1FLs1OlqKYO1Ti7YqQSQTv B6Ob0HRftwY1aH1ytjoXVRWh48T5GpPGSBRHLj/y2nmvzZgXsysDfm0S4+FyW+ALNaPt /sQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737157327; x=1737762127; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=u5+M48xEYsPxfpNh5jdjkOZetq5qZE6t5SXp0yc/k2M=; b=MprM8iWUe084g5MWGcr6xHVlbjttMnYJWsrtSrjdGEpr8QHvgsy6kwQF/LuTQ6S7sy rhvAopgIjO/W9WJbp3E/PijnoJw5LDWrpuhltP2RQ6s1NjGn3JV5PPQTtwc9KyOu3mxO iWBfpaN23DSS6+gSEXqcTE5uocoAWXN4D8eXnCxN9pEYdP9IfNho2tiQHKyoYRAlge9k i8X3tivJHoGMQciPiYkxsfq4ksd67PjA17a2nM93kXEf3JY8X0TG6UAOV5T1zjNq2Wtg yAtc1pLwVG0v8rifZu0g50YzJCFzqSyadCCBdqozzdkmySqZfLihagw0OjMzQuD+NER6 Mvcw== X-Forwarded-Encrypted: i=1; AJvYcCUPWt1+k1zsGN7YFfLPe2LyT0V5Hd3jeMzGruw0cGe8aFlQ9xS5KbW8EDI8SXa0CQxtFLazEjFKGjRCB/A=@vger.kernel.org X-Gm-Message-State: AOJu0YyT1mhPmG2NvcjWbiCsA1Y/1JcJ+fgB3Z4pHxF/BLShucL4eGf1 85tOPDs9E9uhwBNyQoKxLusRQeziuA4CsMXRr4HCrMFM2MT8fIblPr5EI3WpEjwd8KePZQYNvTb Ewg== X-Google-Smtp-Source: AGHT+IGl6m0HjxHGktxDhc1qkC2rHr/QX1dmPhJzqq7Pyp3+7VIqcRHqfV4KIdxMFGQd93i0eQhdjm9Q+jM= X-Received: from pfbcg12.prod.google.com ([2002:a05:6a00:290c:b0:72d:b526:23ec]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:338b:b0:729:597:4f97 with SMTP id d2e1a72fcca58-72dafbd26d3mr8487641b3a.20.1737157327404; Fri, 17 Jan 2025 15:42:07 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 17 Jan 2025 15:41:59 -0800 In-Reply-To: <20250117234204.2600624-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250117234204.2600624-1-seanjc@google.com> X-Mailer: git-send-email 2.48.0.rc2.279.g1de40edade-goog Message-ID: <20250117234204.2600624-2-seanjc@google.com> Subject: [PATCH 1/5] KVM: selftests: Make Intel arch events globally available in PMU counters test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wrap PMU counter test's array of Intel architectrual in a helper function so that the events can be queried in multiple locations. Add a comment to explain the need for a wrapper. No functional change intended. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 84 +++++++++++-------- 1 file changed, 49 insertions(+), 35 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index accd7ecd3e5f..fe7d72fc8a75 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -33,6 +33,53 @@ static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; =20 +#define X86_PMU_FEATURE_NULL \ +({ \ + struct kvm_x86_pmu_feature feature =3D {}; \ + \ + feature; \ +}) + +static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) +{ + return !(*(u64 *)&event); +} + +struct kvm_intel_pmu_event { + struct kvm_x86_pmu_feature gp_event; + struct kvm_x86_pmu_feature fixed_event; +}; + +/* + * Wrap the array to appease the compiler, as the macros used to construct= each + * kvm_x86_pmu_feature use syntax that's only valid in function scope, and= the + * compiler often thinks the feature definitions aren't compile-time const= ants. + */ +static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx) +{ + const struct kvm_intel_pmu_event __intel_event_to_feature[] =3D { + [INTEL_ARCH_CPU_CYCLES_INDEX] =3D { X86_PMU_FEATURE_CPU_CYCLES, X86_PM= U_FEATURE_CPU_CYCLES_FIXED }, + [INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] =3D { X86_PMU_FEATURE_INSNS_RET= IRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED }, + /* + * Note, the fixed counter for reference cycles is NOT the same as the + * general purpose architectural event. The fixed counter explicitly + * counts at the same frequency as the TSC, whereas the GP event counts + * at a fixed, but uarch specific, frequency. Bundle them here for + * simplicity. + */ + [INTEL_ARCH_REFERENCE_CYCLES_INDEX] =3D { X86_PMU_FEATURE_REFERENCE_CYC= LES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED }, + [INTEL_ARCH_LLC_REFERENCES_INDEX] =3D { X86_PMU_FEATURE_LLC_REFERENCES,= X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_LLC_MISSES_INDEX] =3D { X86_PMU_FEATURE_LLC_MISSES, X86_PM= U_FEATURE_NULL }, + [INTEL_ARCH_BRANCHES_RETIRED_INDEX] =3D { X86_PMU_FEATURE_BRANCH_INSNS_= RETIRED, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] =3D { X86_PMU_FEATURE_BRANCHES_= MISPREDICTED, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_TOPDOWN_SLOTS_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_SLOTS, X= 86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED }, + }; + + kvm_static_assert(ARRAY_SIZE(__intel_event_to_feature) =3D=3D NR_INTEL_AR= CH_EVENTS); + + return __intel_event_to_feature[idx]; +} + static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, void *guest_code, uint8_t pmu_version, @@ -197,41 +244,8 @@ static void __guest_test_arch_event(uint8_t idx, struc= t kvm_x86_pmu_feature even GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM= _FEP); } =20 -#define X86_PMU_FEATURE_NULL \ -({ \ - struct kvm_x86_pmu_feature feature =3D {}; \ - \ - feature; \ -}) - -static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) -{ - return !(*(u64 *)&event); -} - static void guest_test_arch_event(uint8_t idx) { - const struct { - struct kvm_x86_pmu_feature gp_event; - struct kvm_x86_pmu_feature fixed_event; - } intel_event_to_feature[] =3D { - [INTEL_ARCH_CPU_CYCLES_INDEX] =3D { X86_PMU_FEATURE_CPU_CYCLES, X86_PM= U_FEATURE_CPU_CYCLES_FIXED }, - [INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] =3D { X86_PMU_FEATURE_INSNS_RET= IRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED }, - /* - * Note, the fixed counter for reference cycles is NOT the same - * as the general purpose architectural event. The fixed counter - * explicitly counts at the same frequency as the TSC, whereas - * the GP event counts at a fixed, but uarch specific, frequency. - * Bundle them here for simplicity. - */ - [INTEL_ARCH_REFERENCE_CYCLES_INDEX] =3D { X86_PMU_FEATURE_REFERENCE_CYC= LES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED }, - [INTEL_ARCH_LLC_REFERENCES_INDEX] =3D { X86_PMU_FEATURE_LLC_REFERENCES,= X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_LLC_MISSES_INDEX] =3D { X86_PMU_FEATURE_LLC_MISSES, X86_PM= U_FEATURE_NULL }, - [INTEL_ARCH_BRANCHES_RETIRED_INDEX] =3D { X86_PMU_FEATURE_BRANCH_INSNS_= RETIRED, X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] =3D { X86_PMU_FEATURE_BRANCHES_= MISPREDICTED, X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_TOPDOWN_SLOTS_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_SLOTS, X= 86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED }, - }; - uint32_t nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUN= TERS); uint32_t pmu_version =3D guest_get_pmu_version(); /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ @@ -249,7 +263,7 @@ static void guest_test_arch_event(uint8_t idx) else base_pmc_msr =3D MSR_IA32_PERFCTR0; =20 - gp_event =3D intel_event_to_feature[idx].gp_event; + gp_event =3D intel_event_to_feature(idx).gp_event; GUEST_ASSERT_EQ(idx, gp_event.f.bit); =20 GUEST_ASSERT(nr_gp_counters); @@ -270,7 +284,7 @@ static void guest_test_arch_event(uint8_t idx) if (!guest_has_perf_global_ctrl) return; =20 - fixed_event =3D intel_event_to_feature[idx].fixed_event; + fixed_event =3D intel_event_to_feature(idx).fixed_event; if (pmu_is_null_feature(fixed_event) || !this_pmu_has(fixed_event)) return; =20 --=20 2.48.0.rc2.279.g1de40edade-goog