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Add a comment to explain the need for a wrapper. No functional change intended. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 84 +++++++++++-------- 1 file changed, 49 insertions(+), 35 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index accd7ecd3e5f..fe7d72fc8a75 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -33,6 +33,53 @@ static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; =20 +#define X86_PMU_FEATURE_NULL \ +({ \ + struct kvm_x86_pmu_feature feature =3D {}; \ + \ + feature; \ +}) + +static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) +{ + return !(*(u64 *)&event); +} + +struct kvm_intel_pmu_event { + struct kvm_x86_pmu_feature gp_event; + struct kvm_x86_pmu_feature fixed_event; +}; + +/* + * Wrap the array to appease the compiler, as the macros used to construct= each + * kvm_x86_pmu_feature use syntax that's only valid in function scope, and= the + * compiler often thinks the feature definitions aren't compile-time const= ants. + */ +static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx) +{ + const struct kvm_intel_pmu_event __intel_event_to_feature[] =3D { + [INTEL_ARCH_CPU_CYCLES_INDEX] =3D { X86_PMU_FEATURE_CPU_CYCLES, X86_PM= U_FEATURE_CPU_CYCLES_FIXED }, + [INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] =3D { X86_PMU_FEATURE_INSNS_RET= IRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED }, + /* + * Note, the fixed counter for reference cycles is NOT the same as the + * general purpose architectural event. The fixed counter explicitly + * counts at the same frequency as the TSC, whereas the GP event counts + * at a fixed, but uarch specific, frequency. Bundle them here for + * simplicity. + */ + [INTEL_ARCH_REFERENCE_CYCLES_INDEX] =3D { X86_PMU_FEATURE_REFERENCE_CYC= LES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED }, + [INTEL_ARCH_LLC_REFERENCES_INDEX] =3D { X86_PMU_FEATURE_LLC_REFERENCES,= X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_LLC_MISSES_INDEX] =3D { X86_PMU_FEATURE_LLC_MISSES, X86_PM= U_FEATURE_NULL }, + [INTEL_ARCH_BRANCHES_RETIRED_INDEX] =3D { X86_PMU_FEATURE_BRANCH_INSNS_= RETIRED, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] =3D { X86_PMU_FEATURE_BRANCHES_= MISPREDICTED, X86_PMU_FEATURE_NULL }, + [INTEL_ARCH_TOPDOWN_SLOTS_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_SLOTS, X= 86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED }, + }; + + kvm_static_assert(ARRAY_SIZE(__intel_event_to_feature) =3D=3D NR_INTEL_AR= CH_EVENTS); + + return __intel_event_to_feature[idx]; +} + static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu, void *guest_code, uint8_t pmu_version, @@ -197,41 +244,8 @@ static void __guest_test_arch_event(uint8_t idx, struc= t kvm_x86_pmu_feature even GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM= _FEP); } =20 -#define X86_PMU_FEATURE_NULL \ -({ \ - struct kvm_x86_pmu_feature feature =3D {}; \ - \ - feature; \ -}) - -static bool pmu_is_null_feature(struct kvm_x86_pmu_feature event) -{ - return !(*(u64 *)&event); -} - static void guest_test_arch_event(uint8_t idx) { - const struct { - struct kvm_x86_pmu_feature gp_event; - struct kvm_x86_pmu_feature fixed_event; - } intel_event_to_feature[] =3D { - [INTEL_ARCH_CPU_CYCLES_INDEX] =3D { X86_PMU_FEATURE_CPU_CYCLES, X86_PM= U_FEATURE_CPU_CYCLES_FIXED }, - [INTEL_ARCH_INSTRUCTIONS_RETIRED_INDEX] =3D { X86_PMU_FEATURE_INSNS_RET= IRED, X86_PMU_FEATURE_INSNS_RETIRED_FIXED }, - /* - * Note, the fixed counter for reference cycles is NOT the same - * as the general purpose architectural event. The fixed counter - * explicitly counts at the same frequency as the TSC, whereas - * the GP event counts at a fixed, but uarch specific, frequency. - * Bundle them here for simplicity. - */ - [INTEL_ARCH_REFERENCE_CYCLES_INDEX] =3D { X86_PMU_FEATURE_REFERENCE_CYC= LES, X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED }, - [INTEL_ARCH_LLC_REFERENCES_INDEX] =3D { X86_PMU_FEATURE_LLC_REFERENCES,= X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_LLC_MISSES_INDEX] =3D { X86_PMU_FEATURE_LLC_MISSES, X86_PM= U_FEATURE_NULL }, - [INTEL_ARCH_BRANCHES_RETIRED_INDEX] =3D { X86_PMU_FEATURE_BRANCH_INSNS_= RETIRED, X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_BRANCHES_MISPREDICTED_INDEX] =3D { X86_PMU_FEATURE_BRANCHES_= MISPREDICTED, X86_PMU_FEATURE_NULL }, - [INTEL_ARCH_TOPDOWN_SLOTS_INDEX] =3D { X86_PMU_FEATURE_TOPDOWN_SLOTS, X= 86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED }, - }; - uint32_t nr_gp_counters =3D this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUN= TERS); uint32_t pmu_version =3D guest_get_pmu_version(); /* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */ @@ -249,7 +263,7 @@ static void guest_test_arch_event(uint8_t idx) else base_pmc_msr =3D MSR_IA32_PERFCTR0; =20 - gp_event =3D intel_event_to_feature[idx].gp_event; + gp_event =3D intel_event_to_feature(idx).gp_event; GUEST_ASSERT_EQ(idx, gp_event.f.bit); =20 GUEST_ASSERT(nr_gp_counters); @@ -270,7 +284,7 @@ static void guest_test_arch_event(uint8_t idx) if (!guest_has_perf_global_ctrl) return; =20 - fixed_event =3D intel_event_to_feature[idx].fixed_event; + fixed_event =3D intel_event_to_feature(idx).fixed_event; if (pmu_is_null_feature(fixed_event) || !this_pmu_has(fixed_event)) return; =20 --=20 2.48.0.rc2.279.g1de40edade-goog From nobody Sat Feb 7 23:10:56 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47651DED6A for ; Fri, 17 Jan 2025 23:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 17 Jan 2025 15:42:09 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 17 Jan 2025 15:42:00 -0800 In-Reply-To: <20250117234204.2600624-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250117234204.2600624-1-seanjc@google.com> X-Mailer: git-send-email 2.48.0.rc2.279.g1de40edade-goog Message-ID: <20250117234204.2600624-3-seanjc@google.com> Subject: [PATCH 2/5] KVM: selftests: Only validate counts for hardware-supported arch events From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the Intel PMU counters test, only validate the counts for architectural events that are supported in hardware. If an arch event isn't supported, the event selector may enable a completely different event, and thus the logic for the expected count is bogus. This fixes test failures on pre-Icelake systems due to the encoding for the architectural Top-Down Slots event corresponding to something else (at least on the Skylake family of CPUs). Note, validation relies on *hardware* support, not KVM support and not guest support. Architectural events are all about enumerating the event selector encoding; lack of enumeration for an architectural event doesn't mean the event itself is unsupported, i.e. the event should still count as expected even if KVM and/or guest CPUID doesn't enumerate the event as being "architectural". Note #2, it's desirable to _program_ the architectural event encoding even if hardware doesn't support the event. The count can't be validated when the event is fully enabled, but KVM should still let the guest program the event selector, and the PMC shouldn't count if the event is disabled. Fixes: 4f1bd6b16074 ("KVM: selftests: Test Intel PMU architectural events o= n gp counters") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-lkp/202501141009.30c629b4-lkp@intel.com Debugged-by: Dapeng Mi Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index fe7d72fc8a75..8159615ad492 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -29,6 +29,8 @@ /* Total number of instructions retired within the measured section. */ #define NUM_INSNS_RETIRED (NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INS= NS) =20 +/* Track which architectural events are supported by hardware. */ +static uint32_t hardware_pmu_arch_events; =20 static uint8_t kvm_pmu_version; static bool kvm_has_perf_caps; @@ -89,6 +91,7 @@ static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct = kvm_vcpu **vcpu, =20 vm =3D vm_create_with_one_vcpu(vcpu, guest_code); sync_global_to_guest(vm, kvm_pmu_version); + sync_global_to_guest(vm, hardware_pmu_arch_events); =20 /* * Set PERF_CAPABILITIES before PMU version as KVM disallows enabling @@ -152,7 +155,7 @@ static void guest_assert_event_count(uint8_t idx, uint64_t count; =20 count =3D _rdpmc(pmc); - if (!this_pmu_has(event)) + if (!(hardware_pmu_arch_events & BIT(idx))) goto sanity_checks; =20 switch (idx) { @@ -560,7 +563,7 @@ static void test_fixed_counters(uint8_t pmu_version, ui= nt64_t perf_capabilities, =20 static void test_intel_counters(void) { - uint8_t nr_arch_events =3D kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECT= OR_LENGTH); + uint8_t nr_arch_events =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VEC= TOR_LENGTH); uint8_t nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_= COUNTERS); uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); @@ -582,18 +585,26 @@ static void test_intel_counters(void) =20 /* * Detect the existence of events that aren't supported by selftests. - * This will (obviously) fail any time the kernel adds support for a - * new event, but it's worth paying that price to keep the test fresh. + * This will (obviously) fail any time hardware adds support for a new + * event, but it's worth paying that price to keep the test fresh. */ TEST_ASSERT(nr_arch_events <=3D NR_INTEL_ARCH_EVENTS, "New architectural event(s) detected; please update this test (lengt= h =3D %u, mask =3D %x)", - nr_arch_events, kvm_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); + nr_arch_events, this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); =20 /* - * Force iterating over known arch events regardless of whether or not - * KVM/hardware supports a given event. + * Iterate over known arch events irrespective of KVM/hardware support + * to verify that KVM doesn't reject programming of events just because + * the *architectural* encoding is unsupported. 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Fri, 17 Jan 2025 15:42:10 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 17 Jan 2025 15:42:01 -0800 In-Reply-To: <20250117234204.2600624-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250117234204.2600624-1-seanjc@google.com> X-Mailer: git-send-email 2.48.0.rc2.279.g1de40edade-goog Message-ID: <20250117234204.2600624-4-seanjc@google.com> Subject: [PATCH 3/5] KVM: selftests: Remove dead code in Intel PMU counters test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the local "nr_arch_events" in the Intel PMU counters test as the test asserts that "nr_arch_events <=3D NR_INTEL_ARCH_EVENTS", and then sets nr_arch_events to the max of the two. I.e. nr_arch_events is guaranteed to be NR_INTEL_ARCH_EVENTS for the meat of the test, just use NR_INTEL_ARCH_EVENTS directly. No functional change intended. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 8159615ad492..5d6a5b9c17b3 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -563,7 +563,6 @@ static void test_fixed_counters(uint8_t pmu_version, ui= nt64_t perf_capabilities, =20 static void test_intel_counters(void) { - uint8_t nr_arch_events =3D this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VEC= TOR_LENGTH); uint8_t nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_= COUNTERS); uint8_t nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTE= RS); uint8_t pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); @@ -588,9 +587,10 @@ static void test_intel_counters(void) * This will (obviously) fail any time hardware adds support for a new * event, but it's worth paying that price to keep the test fresh. */ - TEST_ASSERT(nr_arch_events <=3D NR_INTEL_ARCH_EVENTS, + TEST_ASSERT(this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH) <= =3D NR_INTEL_ARCH_EVENTS, "New architectural event(s) detected; please update this test (lengt= h =3D %u, mask =3D %x)", - nr_arch_events, this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); + this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH), + this_cpu_property(X86_PROPERTY_PMU_EVENTS_MASK)); =20 /* * Iterate over known arch events irrespective of KVM/hardware support @@ -600,8 +600,7 @@ static void test_intel_counters(void) * count correctly, even if *enumeration* of the event is unsupported * by KVM and/or isn't exposed to the guest. */ - nr_arch_events =3D max_t(typeof(nr_arch_events), nr_arch_events, NR_INTEL= _ARCH_EVENTS); - for (i =3D 0; i < nr_arch_events; i++) { + for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) { if (this_pmu_has(intel_event_to_feature(i).gp_event)) hardware_pmu_arch_events |=3D BIT(i); } @@ -620,8 +619,8 @@ static void test_intel_counters(void) * vector length. */ if (v =3D=3D pmu_version) { - for (k =3D 1; k < (BIT(nr_arch_events) - 1); k++) - test_arch_events(v, perf_caps[i], nr_arch_events, k); + for (k =3D 1; k < (BIT(NR_INTEL_ARCH_EVENTS) - 1); k++) + test_arch_events(v, perf_caps[i], NR_INTEL_ARCH_EVENTS, k); } /* * Test single bits for all PMU version and lengths up @@ -630,11 +629,11 @@ static void test_intel_counters(void) * host length). Explicitly test a mask of '0' and all * ones i.e. all events being available and unavailable. */ - for (j =3D 0; j <=3D nr_arch_events + 1; j++) { + for (j =3D 0; j <=3D NR_INTEL_ARCH_EVENTS + 1; j++) { test_arch_events(v, perf_caps[i], j, 0); test_arch_events(v, perf_caps[i], j, 0xff); =20 - for (k =3D 0; k < nr_arch_events; k++) + for (k =3D 0; k < NR_INTEL_ARCH_EVENTS; k++) test_arch_events(v, perf_caps[i], j, BIT(k)); } =20 --=20 2.48.0.rc2.279.g1de40edade-goog From nobody Sat Feb 7 23:10:56 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EACC1DE3B5 for ; Fri, 17 Jan 2025 23:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737157335; cv=none; b=miVWZBssovKSRqslsbESvyhc0BfyCmafmxp+sbZReHXeE6CutJa5V45j0H1rOnW/9NcEvDKMO41tiPM3xkDRJAMPcFiKh+n+mURXkYMFSEhQk9Rxt/WLJcr6Pq57Jg6hX4kjiYj5fSmkqp24+JRhdJj6nSwfvI77yyw4TWQFirI= ARC-Message-Signature: i=1; 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charset="utf-8" Now that validation of event count is tied to hardware support for event, and not to guest support for an event, drop the unused "event" parameter from the various helpers. No functional change intended. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86/pmu_counters_test.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index 5d6a5b9c17b3..ea1485a08c78 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -148,9 +148,7 @@ static uint8_t guest_get_pmu_version(void) * Sanity check that in all cases, the event doesn't count when it's disab= led, * and that KVM correctly emulates the write of an arbitrary value. */ -static void guest_assert_event_count(uint8_t idx, - struct kvm_x86_pmu_feature event, - uint32_t pmc, uint32_t pmc_msr) +static void guest_assert_event_count(uint8_t idx, uint32_t pmc, uint32_t p= mc_msr) { uint64_t count; =20 @@ -223,7 +221,7 @@ do { \ ); \ } while (0) =20 -#define GUEST_TEST_EVENT(_idx, _event, _pmc, _pmc_msr, _ctrl_msr, _value, = FEP) \ +#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ do { \ wrmsr(_pmc_msr, 0); \ \ @@ -234,17 +232,16 @@ do { \ else \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \ \ - guest_assert_event_count(_idx, _event, _pmc, _pmc_msr); \ + guest_assert_event_count(_idx, _pmc, _pmc_msr); \ } while (0) =20 -static void __guest_test_arch_event(uint8_t idx, struct kvm_x86_pmu_featur= e event, - uint32_t pmc, uint32_t pmc_msr, +static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pm= c_msr, uint32_t ctrl_msr, uint64_t ctrl_msr_value) { - GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, ""); + GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, ""); =20 if (is_forced_emulation_enabled) - GUEST_TEST_EVENT(idx, event, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM= _FEP); + GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM_FEP); } =20 static void guest_test_arch_event(uint8_t idx) @@ -280,7 +277,7 @@ static void guest_test_arch_event(uint8_t idx) if (guest_has_perf_global_ctrl) wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(i)); 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Fri, 17 Jan 2025 15:42:14 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 17 Jan 2025 15:42:03 -0800 In-Reply-To: <20250117234204.2600624-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250117234204.2600624-1-seanjc@google.com> X-Mailer: git-send-email 2.48.0.rc2.279.g1de40edade-goog Message-ID: <20250117234204.2600624-6-seanjc@google.com> Subject: [PATCH 5/5] KVM: selftests: Print out the actual Top-Down Slots count on failure From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel test robot Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Print out the expected vs. actual count of the Top-Down Slots event on failure in the Intel PMU counters test. GUEST_ASSERT() only expands constants/macros, i.e. only prints the value of the expected count, which makes it difficult to debug and triage failures. Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/x86/pmu_counters_test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index ea1485a08c78..8aaaf25b6111 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -174,7 +174,9 @@ static void guest_assert_event_count(uint8_t idx, uint3= 2_t pmc, uint32_t pmc_msr GUEST_ASSERT_NE(count, 0); break; case INTEL_ARCH_TOPDOWN_SLOTS_INDEX: - GUEST_ASSERT(count >=3D NUM_INSNS_RETIRED); + __GUEST_ASSERT(count >=3D NUM_INSNS_RETIRED, + "Expected top-down slots >=3D %u, got count =3D %lu", + NUM_INSNS_RETIRED, count); break; default: break; --=20 2.48.0.rc2.279.g1de40edade-goog