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Thu, 16 Jan 2025 15:10:31 -0800 (PST) Received: from rkanwal-XPS-15-9520.uk.rivosinc.com ([2a02:c7c:75ac:6300:b3f2:3a24:1767:7db0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf322b337sm974991f8f.59.2025.01.16.15.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 15:10:31 -0800 (PST) From: Rajnesh Kanwal To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: linux-perf-users@vger.kernel.org, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, ajones@ventanamicro.com, anup@brainfault.org, acme@kernel.org, atishp@rivosinc.com, beeman@rivosinc.com, brauner@kernel.org, conor@kernel.org, heiko@sntech.de, irogers@google.com, mingo@redhat.com, james.clark@arm.com, renyu.zj@linux.alibaba.com, jolsa@kernel.org, jisheng.teoh@starfivetech.com, palmer@dabbelt.com, will@kernel.org, kaiwenxue1@gmail.com, vincent.chen@sifive.com, Rajnesh Kanwal Subject: [PATCH v2 4/7] dt-bindings: riscv: add Sxctr ISA extension description Date: Thu, 16 Jan 2025 23:09:52 +0000 Message-Id: <20250116230955.867152-5-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250116230955.867152-1-rkanwal@rivosinc.com> References: <20250116230955.867152-1-rkanwal@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the S[m|s]ctr ISA extension description. Signed-off-by: Rajnesh Kanwal --- .../devicetree/bindings/riscv/extensions.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 848354e3048f..8322503f0773 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -167,6 +167,13 @@ properties: extension allows other ISA extension to use indirect CSR access mechanism in M-mode. =20 + - const: smctr + description: | + The standard Smctr supervisor-level extension for the machine = mode + to enable recording limited branch history in a register-acces= sible + internal core storage. Smctr depend on both the implementation= of + S-mode and the Sscsrind extension. + - const: sscsrind description: | The standard Sscsrind supervisor-level extension extends the @@ -193,6 +200,13 @@ properties: and mode-based filtering as ratified at commit 01d1df0 ("Add a= bility to manually trigger workflow. (#2)") of riscv-count-overflow. =20 + - const: ssctr + description: | + The standard Ssctr supervisor-level extension enables recordin= g of + limited branch history in a register-accessible internal core + storage. Ssctr depend on both the implementation of S-mode and= the + Sscsrind extension. + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as --=20 2.34.1