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Thu, 16 Jan 2025 06:48:08 -0800 (PST) From: Nobuhiro Iwamatsu To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Masato Kiuchi , Nobuhiro Iwamatsu , Krzysztof Kozlowski Subject: [PATCH v2 1/4] dt-bindings: soc: renesas: Document Renesas RZ/V2H SoC variants Date: Thu, 16 Jan 2025 23:47:49 +0900 Message-ID: <20250116144752.1738574-2-iwamatsu@nigauri.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250116144752.1738574-1-iwamatsu@nigauri.org> References: <20250116144752.1738574-1-iwamatsu@nigauri.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SoC documentation for Renesas RZ/V2H(P) (r9a09g057h4[568]) SoC. Signed-off-by: Nobuhiro Iwamatsu Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v2: No update Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index 225c0f07ae94c8..4f2645e8140c5c 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -552,6 +552,9 @@ properties: - renesas,r9a09g057h41 # RZ/V2H - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 su= pport + - renesas,r9a09g057h45 # RZ/V2H with cryptographic extension= support + - renesas,r9a09g057h46 # RZ/V2H with Mali-G31 + cryptographi= c extension support + - renesas,r9a09g057h48 # RZ/V2HP with Mali-G31 + Mali-C55 + = cryptographic extension support - const: renesas,r9a09g057 =20 additionalProperties: true --=20 2.47.1 From nobody Sun Dec 14 08:08:29 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4431C22C9F8 for ; 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Thu, 16 Jan 2025 06:48:11 -0800 (PST) Received: from localhost ([2405:6581:5360:1800:4323:933a:5975:d650]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72dab7f06c3sm106055b3a.20.2025.01.16.06.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 06:48:11 -0800 (PST) From: Nobuhiro Iwamatsu To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Masato Kiuchi , Nobuhiro Iwamatsu , Krzysztof Kozlowski Subject: [PATCH v2 2/4] dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd. Date: Thu, 16 Jan 2025 23:47:50 +0900 Message-ID: <20250116144752.1738574-3-iwamatsu@nigauri.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250116144752.1738574-1-iwamatsu@nigauri.org> References: <20250116144752.1738574-1-iwamatsu@nigauri.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add entry for Yuridenki-Shokai Co. Ltd. (https://www.yuridenki.co.jp) Signed-off-by: Nobuhiro Iwamatsu Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v2: No update. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index da01616802c768..5e26fe32a50e7b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1727,6 +1727,8 @@ patternProperties: description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": description: Y Soft Corporation a.s. + "^yuridenki,.*": + description: Yuridenki-Shokai Co. Ltd. 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charset="utf-8" Add "yuridenki,kakip" which targets the Yuridenki-Shokai Kakip board. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v2: Fix the rule of binding for boards. kakip board uses r9a09g057h48 only. Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index 4f2645e8140c5c..a8af4fce596127 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -557,6 +557,12 @@ properties: - renesas,r9a09g057h48 # RZ/V2HP with Mali-G31 + Mali-C55 + = cryptographic extension support - const: renesas,r9a09g057 =20 + - description: Yuridenki-Shokai RZ/V2H Kakip + items: + - const: yuridenki,kakip + - const: renesas,r9a09g057h48 + - const: renesas,r9a09g057 + additionalProperties: true =20 ... --=20 2.47.1 From nobody Sun Dec 14 08:08:29 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B090A22A7FF for ; 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charset="utf-8" Add basic support for Yuridenki-Shokai Kakip board based on R9A09G057H48. This commit supports the following: - Memory - Input clocks - Pin Control - SCIF - OSTM0 - OSTM7 - SDHI0 Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Geert Uytterhoeven --- v2: Drop bootargs from chosen. Fix binding name for regulators. Fix the name style of the regulator. Use DTS coding style. arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r9a09g057h48-kakip.dts | 136 ++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 928635f2e76bbb..698f790bd42524 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_R9A09G011) +=3D r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_R9A09G047) +=3D r9a09g047e57-smarc.dtb =20 dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h44-rzv2h-evk.dtb +dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h48-kakip.dtb =20 dtb-$(CONFIG_ARCH_RCAR_GEN3) +=3D draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) +=3D salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g057h48-kakip.dts new file mode 100644 index 00000000000000..b35a6c0499ee7c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for Yuridenki-Shokai the Kakip board + * + * Copyright (C) 2024 Nobuhiro Iwamatsu + */ + +/dts-v1/; + +#include +#include +#include "r9a09g057.dtsi" + +/ { + model =3D "Yuridenki-Shokai Kakip Board based on r9a09g057h48"; + compatible =3D "yuridenki,kakip", "renesas,r9a09g057h48", "renesas,r9a09g= 057"; + + aliases { + serial0 =3D &scif; + mmc0 =3D &sdhi0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@48000000 { + device_type =3D "memory"; + /* first 128MB is reserved for secure area. */ + reg =3D <0x0 0x48000000 0x1 0xF8000000>; + }; + + reg_3p3v: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi0: regulator-vccq-sdhi0 { + compatible =3D "regulator-gpio"; + regulator-name =3D "SDHI0 VccQ"; + gpios =3D <&pinctrl RZV2H_GPIO(A, 0) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios-states =3D <0>; + states =3D <3300000 0 1800000 1>; + }; +}; + +&qextal_clk { + clock-frequency =3D <24000000>; +}; + +&pinctrl { + scif_pins: scif { + pins =3D "SCIF_RXD", "SCIF_TXD"; + }; + + sd0-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd0_pwr_en"; + }; + + sdhi0_pins: sd0 { + sd0-data { + pins =3D "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD"; + input-enable; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd0-clk { + pins =3D "SD0CLK"; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd0-mux { + pinmux =3D ; /* SD0_CD */ + }; + }; +}; + +&scif { + pinctrl-0 =3D <&scif_pins>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&ostm0 { + status =3D "okay"; +}; + +&ostm1 { + status =3D "okay"; +}; + +&ostm2 { + status =3D "okay"; +}; + +&ostm3 { + status =3D "okay"; +}; + +&ostm4 { + status =3D "okay"; +}; + +&ostm5 { + status =3D "okay"; +}; + +&ostm6 { + status =3D "okay"; +}; + +&ostm7 { + status =3D "okay"; +}; + +&sdhi0 { + pinctrl-0 =3D <&sdhi0_pins>; + pinctrl-names =3D "default"; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sdhi0>; + bus-width =3D <4>; + + status =3D "okay"; +}; --=20 2.47.1