From nobody Wed Feb 5 13:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0460713D279; Thu, 16 Jan 2025 03:25:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736997926; cv=none; b=Bhq0bM5WS9Kw/nhx+xi9lGre5/g/anFgJ5Z/aPb+PaPd9BfwtGmLolVIG+/fZyb2pN+ThrgcOSURjQkWxIRhR+sESv7SVPc1aHQiN0NGznakVBsrshG5EeYmC/rOdIMfEC5wwZ3rj/zzPT6ntM04FDHlrOGVkRaXdVqF7d3BUFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736997926; c=relaxed/simple; bh=9YYGXevSZHlst/BPZfEfbibwoduDeeUOTds+39AMyPo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H932dg55YlAtmyWkCb7xw1OLHZAumLOots4MR0fwscT+Q+CVBT6BvraElYnA9nn2QQpmRUVuKO9kcrK7WnCn7BmQXuVwf+JZwxi8hXqfqhnlehfRxlD9j97jGJPpHkwlZLvImrVc4hAhNe9I7ONk3fPy3axWH/Pv220RX2vjFmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OWX6w0XZ; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OWX6w0XZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736997925; x=1768533925; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9YYGXevSZHlst/BPZfEfbibwoduDeeUOTds+39AMyPo=; b=OWX6w0XZf0wjaEjZh67dGK0syDwG46wxinKXLE3nxTaNGVNF7CS3O6Zs 5Jdb/dP+24Uc2Lw/FzeQkQ0PWZAc9FdqrZfbdWNoPVUvTglqZVrTpwHb3 su81ZA4Z/GmQdYLaB59ADpRA75mM8LD23rO8vjeWVeacNhu8dlENwOET+ upY9dX2m3qo5ul+pW5KHVsKqTq1DqWpNnvI62j2jBaH8gBL7H2A95kCiM VayiS4G1C5ajf/89Nx1UNxE/GZlRN2v9KffWfdaKP9D5b8Bz76UF+hveq By6Ua8qvaOV+DCc5gaHyoWJCg2Rd0m+w23qqyXATupE0EMV3/Fzagk5zO Q==; X-CSE-ConnectionGUID: xUVlj1wPQZOnnJQS2kx8TQ== X-CSE-MsgGUID: LKwY4z3vSPyYYus5c1RtPg== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="37478869" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="37478869" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2025 19:25:24 -0800 X-CSE-ConnectionGUID: UZ+Enxz+Q3uMV4IIBC95Kw== X-CSE-MsgGUID: dWe5rzSyTlWc1CFGsZI1mQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="142604337" Received: from pg15swiplab1181.png.altera.com ([10.244.232.167]) by orviesa001.jf.intel.com with ESMTP; 15 Jan 2025 19:25:22 -0800 From: niravkumar.l.rabara@intel.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Niravkumar L Rabara , linux@treblig.org, Shen Lichuan , Jinjie Ruan , u.kleine-koenig@baylibre.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Subject: [PATCH v2 1/3] mtd: rawnand: cadence: support deferred prob when DMA is not ready Date: Thu, 16 Jan 2025 11:21:52 +0800 Message-Id: <20250116032154.3976447-2-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> References: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Use deferred driver probe in case the DMA driver is not probed. When ARM SMMU is enabled, all peripheral device drivers, including NAND, are probed earlier than the DMA driver. Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subs= ystem") Cc: stable@vger.kernel.org Signed-off-by: Niravkumar L Rabara --- drivers/mtd/nand/raw/cadence-nand-controller.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/n= and/raw/cadence-nand-controller.c index 8d1d710e439d..5e27f5546f1b 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -2908,7 +2908,7 @@ static int cadence_nand_init(struct cdns_nand_ctrl *c= dns_ctrl) if (!cdns_ctrl->dmac) { dev_err(cdns_ctrl->dev, "Unable to get a DMA channel\n"); - ret =3D -EBUSY; + ret =3D -EPROBE_DEFER; goto disable_irq; } } --=20 2.25.1 From nobody Wed Feb 5 13:51:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C75CA13635B; Thu, 16 Jan 2025 03:25:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736997933; cv=none; b=cy9iwJaIqMi4j33nsy5avSvSP4Bi+F3dd/Xwjm8/N2r+umeJMkBwZM6PlJaX2fGEbaWpXnfbZP6BVMNd8eMETrVfsmiHnEDT9wgK1N7orLUzEWbWV9iQrR4Vin+4NPgIbMMaijrKI4cQ6RRJ7yGaUmChKdYkrxf5GeifZinIvEg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736997933; c=relaxed/simple; bh=it0li0YYogXZ6lxr/8sOjCldpc3M/I48MQwObTe+uj0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dG3vDawN2k1yjrb1UVix0Xu8UwLoG+UrpiytuGAATiyC2ln4AqRt3+KTEJnjRZnR0LayEKpFm7xBSLeHynlfe/DueQslFVac7BBF2lBmGSCJB75PE+6eCC9XKC+TBekHQyiZJ3z4QEj5QOpiE8pcGYnc9ELXawq0Xk6xkS7SgCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PckeBSIS; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PckeBSIS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736997932; x=1768533932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=it0li0YYogXZ6lxr/8sOjCldpc3M/I48MQwObTe+uj0=; b=PckeBSISQQk7R7MDhv6BtZsIe+fkwZ33fvcOTi+NK2D+8r3PM1x94bTH ybQLXmTCOI/pUfqvCXhRey6UqLUHjIPdOJtj3g4k2t7T2He+BiTwDv8+Q UGHnrD1qv02TynQ4BU66bACzMtEUXOUzGJS+8WYcnu1AyzI7I11cJl6cQ eMqWPDysBaFyeSwLu0GaVGUcKzl9t+MAM0zT0z0LVlTz57Q9dqJ8pxpNq 3s+dlW7Zxsv76WW6ggxqb/++ocJDlGOdFZNYOgfWw7mJPN3z3FH7+eJkM t80LS3OIF0OYxeaIbnHpsvPc5UvJJ7pIgUz6MJ9YHGo+pj9T2yEHr3le7 A==; X-CSE-ConnectionGUID: 0j5TzDjyROW6IHegeKP+rA== X-CSE-MsgGUID: 83Q1FY6LT6KAwf1iLePe1w== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="37478900" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="37478900" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2025 19:25:31 -0800 X-CSE-ConnectionGUID: UNy1vifpQya6JUUjsaamGA== X-CSE-MsgGUID: 11xnMHdZS5S5S5md6mZkPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="142604356" Received: from pg15swiplab1181.png.altera.com ([10.244.232.167]) by orviesa001.jf.intel.com with ESMTP; 15 Jan 2025 19:25:28 -0800 From: niravkumar.l.rabara@intel.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Niravkumar L Rabara , linux@treblig.org, Shen Lichuan , Jinjie Ruan , u.kleine-koenig@baylibre.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Subject: [PATCH v2 2/3] mtd: rawnand: cadence: use dma_map_resource for sdma address Date: Thu, 16 Jan 2025 11:21:53 +0800 Message-Id: <20250116032154.3976447-3-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> References: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara Map the slave DMA I/O address using dma_map_resource. When ARM SMMU is enabled, using a direct physical address of SDMA results in DMA transaction failure. Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subs= ystem") Cc: stable@vger.kernel.org Signed-off-by: Niravkumar L Rabara --- .../mtd/nand/raw/cadence-nand-controller.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/n= and/raw/cadence-nand-controller.c index 5e27f5546f1b..8281151cf869 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -471,6 +471,8 @@ struct cdns_nand_ctrl { struct { void __iomem *virt; dma_addr_t dma; + dma_addr_t iova_dma; + u32 size; } io; =20 int irq; @@ -1835,11 +1837,11 @@ static int cadence_nand_slave_dma_transfer(struct c= dns_nand_ctrl *cdns_ctrl, } =20 if (dir =3D=3D DMA_FROM_DEVICE) { - src_dma =3D cdns_ctrl->io.dma; + src_dma =3D cdns_ctrl->io.iova_dma; dst_dma =3D buf_dma; } else { src_dma =3D buf_dma; - dst_dma =3D cdns_ctrl->io.dma; + dst_dma =3D cdns_ctrl->io.iova_dma; } =20 tx =3D dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len, @@ -2869,6 +2871,7 @@ cadence_nand_irq_cleanup(int irqnum, struct cdns_nand= _ctrl *cdns_ctrl) static int cadence_nand_init(struct cdns_nand_ctrl *cdns_ctrl) { dma_cap_mask_t mask; + struct dma_device *dma_dev =3D cdns_ctrl->dmac->device; int ret; =20 cdns_ctrl->cdma_desc =3D dma_alloc_coherent(cdns_ctrl->dev, @@ -2913,6 +2916,16 @@ static int cadence_nand_init(struct cdns_nand_ctrl *= cdns_ctrl) } } =20 + cdns_ctrl->io.iova_dma =3D dma_map_resource(dma_dev->dev, cdns_ctrl->io.d= ma, + cdns_ctrl->io.size, + DMA_BIDIRECTIONAL, 0); + + ret =3D dma_mapping_error(dma_dev->dev, cdns_ctrl->io.iova_dma); + if (ret) { + dev_err(cdns_ctrl->dev, "Failed to map I/O resource to DMA\n"); + goto dma_release_chnl; + } + nand_controller_init(&cdns_ctrl->controller); INIT_LIST_HEAD(&cdns_ctrl->chips); =20 @@ -2923,18 +2936,22 @@ static int cadence_nand_init(struct cdns_nand_ctrl = *cdns_ctrl) if (ret) { dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n", ret); - goto dma_release_chnl; + goto unmap_dma_resource; } =20 kfree(cdns_ctrl->buf); cdns_ctrl->buf =3D kzalloc(cdns_ctrl->buf_size, GFP_KERNEL); if (!cdns_ctrl->buf) { ret =3D -ENOMEM; - goto dma_release_chnl; + goto unmap_dma_resource; } =20 return 0; =20 +unmap_dma_resource: + dma_unmap_resource(dma_dev->dev, cdns_ctrl->io.iova_dma, + cdns_ctrl->io.size, DMA_BIDIRECTIONAL, 0); + dma_release_chnl: if (cdns_ctrl->dmac) dma_release_channel(cdns_ctrl->dmac); @@ -2956,6 +2973,8 @@ static int cadence_nand_init(struct cdns_nand_ctrl *c= dns_ctrl) static void cadence_nand_remove(struct cdns_nand_ctrl *cdns_ctrl) { cadence_nand_chips_cleanup(cdns_ctrl); + dma_unmap_resource(cdns_ctrl->dmac->device->dev, cdns_ctrl->io.iova_dma, + cdns_ctrl->io.size, DMA_BIDIRECTIONAL, 0); cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); kfree(cdns_ctrl->buf); dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), @@ -3020,7 +3039,9 @@ static int cadence_nand_dt_probe(struct platform_devi= ce *ofdev) cdns_ctrl->io.virt =3D devm_platform_get_and_ioremap_resource(ofdev, 1, &= res); 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d="scan'208";a="142604370" Received: from pg15swiplab1181.png.altera.com ([10.244.232.167]) by orviesa001.jf.intel.com with ESMTP; 15 Jan 2025 19:25:33 -0800 From: niravkumar.l.rabara@intel.com To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Niravkumar L Rabara , linux@treblig.org, Shen Lichuan , Jinjie Ruan , u.kleine-koenig@baylibre.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org Subject: [PATCH v2 3/3] mtd: rawnand: cadence: fix incorrect dev context in dma_unmap_single Date: Thu, 16 Jan 2025 11:21:54 +0800 Message-Id: <20250116032154.3976447-4-niravkumar.l.rabara@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> References: <20250116032154.3976447-1-niravkumar.l.rabara@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Niravkumar L Rabara dma_map_single is using dma_dev->dev, however dma_unmap_single is using cdns_ctrl->dev, which is incorrect. Used the correct device context dma_dev->dev for dma_unmap_single. Fixes: ec4ba01e894d ("mtd: rawnand: Add new Cadence NAND driver to MTD subs= ystem") Cc: stable@vger.kernel.org Signed-off-by: Niravkumar L Rabara --- drivers/mtd/nand/raw/cadence-nand-controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/n= and/raw/cadence-nand-controller.c index 8281151cf869..2d50eeb902ac 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -1863,12 +1863,12 @@ static int cadence_nand_slave_dma_transfer(struct c= dns_nand_ctrl *cdns_ctrl, dma_async_issue_pending(cdns_ctrl->dmac); wait_for_completion(&finished); =20 - dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir); + dma_unmap_single(dma_dev->dev, buf_dma, len, dir); =20 return 0; =20 err_unmap: - dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir); + dma_unmap_single(dma_dev->dev, buf_dma, len, dir); =20 err: dev_dbg(cdns_ctrl->dev, "Fall back to CPU I/O\n"); --=20 2.25.1