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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-3-74749c6eba33@linaro.org> References: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> In-Reply-To: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737012353; l=1739; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=eXNECQiRO+b55BrnG8VsEC3fTpX4rkFaox/olbPegR8=; b=ZpGI9rA0Yep9WbZMzmuE3wpwCyq+V72ZXvKnbh0f+XI9vex6SP5rVpcB+Qe2sTRs7UrQAVBKy 121EILuWjGBCW4075/c9hoc2vvbmgzvNIVTEpqVnBWk9jAzXMWSHNGb X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently if DSC support is requested, the driver only supports using 2 DSC blocks. We need 4 DSC in quad-pipe topology in future. So Only configure DSC engines in use, instead of the maximum number of DSC engines. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index c734d2c5790d2..6603e9c03226f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2027,7 +2027,7 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ct= l *ctl, static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, struct drm_dsc_config *dsc) { - /* coding only for 2LM, 2enc, 1 dsc config */ + int num_dsc =3D dpu_enc->num_dscs; struct dpu_encoder_phys *enc_master =3D dpu_enc->cur_master; struct dpu_hw_ctl *ctl =3D enc_master->hw_ctl; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; @@ -2039,7 +2039,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_v= irt *dpu_enc, u32 initial_lines; int i; =20 - for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) { + for (i =3D 0; i < num_dsc; i++) { hw_pp[i] =3D dpu_enc->hw_pp[i]; hw_dsc[i] =3D dpu_enc->hw_dsc[i]; =20 @@ -2068,7 +2068,7 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_v= irt *dpu_enc, enc_ip_w =3D intf_ip_w / 2; initial_lines =3D dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); =20 - for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) + for (i =3D 0; i < num_dsc; i++) dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines); } --=20 2.34.1