From nobody Sun Dec 14 21:56:08 2025 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF401ADC81 for ; Thu, 16 Jan 2025 07:27:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737012473; cv=none; b=SU8tGGXS6fVRmbt7kOszxXVEuNwGlE/jf3xchE6NxwbzGmpIEgxThf+gfoENPCq6dIuEbPWlDsFQfxZI+UTM9t9kxJz3JyQaI50zFk2LQWrgxnIoaTuZMdi3qsnKCnGNGCY0B8S5c9b+lC1wexPIfiXzzuDiMR+K30Ien4lZv3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737012473; c=relaxed/simple; bh=RbKPuq803+NiCMGe/UJ/U7W3A07kesdKTJCDbtqd0sE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UGEAEkEt2jPt39uvrId3t1uf/23UWUHLqdn7mPaCAh51POTkHwLLUso/VMcpZNFLIT6qaQnAZGtkFS0KdmMjWSTbN/IeaLOXoXGdzIbeeU5LjVHYyvVbxBl/dAwkvX2ygJ5aEkYsiv30BvUJ4QGxrvfQCEB1wnVwVirC+bvWxJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Fg9+Yopr; arc=none smtp.client-ip=209.85.214.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Fg9+Yopr" Received: by mail-pl1-f171.google.com with SMTP id d9443c01a7336-21619108a6bso8369415ad.3 for ; Wed, 15 Jan 2025 23:27:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1737012471; x=1737617271; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=e3p4IrXJLa2akZc/exUIig8oznH8M83r0nH6KiRhlZU=; b=Fg9+YoprvI279xoLApJAI8hfMqgpYt1+Zj4VCwJI+XgbnZjuIWDrqRAT0Fhd0TdU/Z 3jUsHEg53oCPTKZRqV3geYQz6/Uis6yAX97uYxXEx9AtUfa6mZ5F+icmDc2u44Lp61sb 03aEqeCagRQfTEvc0fS5ElM2J+h8st11rB6rjPvu5dO9jF1mvy2Gcfah88UYhx5gZ/KT RD27McBDgvw67sldxdNswBR49CCgslfIE+MOnNxc8Lnqy77DxeJ7NQ/ROZrsC9zzbYTC E7iVXlJszityHoR4kgFf8QES7BS9CqwGpyQuK3xnl90M9PwjTdUUwDSg4qCB4tLW3PG9 70Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1737012471; x=1737617271; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e3p4IrXJLa2akZc/exUIig8oznH8M83r0nH6KiRhlZU=; b=H6Gh3qprZ+wOhaeODUdBAcLwfd4yByeFrOgSr7O18LpGcwFHWFmR8ZujT2j4frzOHA vwuafH+1LSauzCm0ufk1c6G7f1FRboymNKnQ+NGT3k93Tg+jnc6R9gxRDrC2Tf7l18+r g+Vn9gzGw1Df+fj7kybD7qXmKGbnjSuz073t6E+E9ytup43EzCpNjNQcg3Va4g7zxUtc SOt+xVYYr/cKgQOBp4sj/r9yRfUDaW3icLfwuJkPJeLBU129NaxogjsP+4gtVqkmVPSR 39zXRogWefoXzrqYoQSetebVM+/8j4l6bqEhmUB7OictfH7ckK+J8D5O/jw/iuSMp4vJ nvFA== X-Forwarded-Encrypted: i=1; AJvYcCWZUl+ccwuM0zkJ2lehu6QCMt1cJpNxfxt67eZ+moPqm8+hVWjLUGgM6oefdrytZunyCsUfQuAg8n49NjU=@vger.kernel.org X-Gm-Message-State: AOJu0YyVJFwg9RDkUfulnepsR1zbulzNIBUoBhE1H+AowJEms/9vV3Rd ioB6J2AhJQ02UnbWWRK6uI7+Ce4Jmrq1rLq1trChrYdAhRlCU9/f2EVgs/+T5Fw= X-Gm-Gg: ASbGncvISLK0O5Cy9nqhzlWXkQIwbhIpHRah3Akq8FalQFujHnlFG7xF7FYmKykPIxN +FMwB3MzSLBFO0xlEPPZEY8YW0Zy8uvotHLCFNpyuM8O9zN/ZJaB3oBwjzDwMMlzhFJx16KhRhi Y+wbPFw4j7SZxN+Vn55Ev33/4eWQfSbZsLveqUL06KY+Yvdl90PleOTEHhbSgobc6AVLqoTv4H5 UTkbsgM1cqysOFUjMmFYFQvwqxQpfUncNYTl7gjfYKrWWY9mvcrDw== X-Google-Smtp-Source: AGHT+IH6sMEL6GX1kbpB8tlkmwGkWmBcolv5ZrUWSyKJAZnVbbsPEjoI8z6Hwtt366GLlL4hyvvDjg== X-Received: by 2002:a05:6a00:399a:b0:725:f1ca:fd8a with SMTP id d2e1a72fcca58-72d21fb1dfcmr52232905b3a.19.1737012471334; Wed, 15 Jan 2025 23:27:51 -0800 (PST) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72d4059485bsm10164583b3a.83.2025.01.15.23.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 23:27:51 -0800 (PST) From: Jun Nie Date: Thu, 16 Jan 2025 15:26:05 +0800 Subject: [PATCH v4 16/16] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-16-74749c6eba33@linaro.org> References: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> In-Reply-To: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737012353; l=5963; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=RbKPuq803+NiCMGe/UJ/U7W3A07kesdKTJCDbtqd0sE=; b=hEdfNz5hHuGh4b0RzMcBCXUrqAGiJZ5UBCDEi/2MsEYrRR4ciTLPVA9sh0uZF7TTKrAk9Uh5Y uomWzZumYCzBR0tMPVdXJsFb5TtgG/9NcElr3WNO1k0JX5qRP94alHw X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are enabled. 4 pipes are preferred for dual DSI case for it is power optimal for DSC. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 ++++++++++++++++++--= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a900220deeb35..5e96c309fabb8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index b14bab2754635..38820d05edb8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 1f3054792a228..fdb7bfcb4119c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -54,7 +54,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -664,15 +664,20 @@ static struct msm_display_topology dpu_encoder_get_to= pology( =20 /* Datapath topology selection * - * Dual display + * Dual display without DSC * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * Dual display with DSC + * 2 LM, 2 INTF ( Split display using 2 interfaces) + * 4 LM, 2 INTF ( Split display using 2 interfaces) + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * * Add dspps to the reservation requirements if ctm is requested */ + if (intf_count =3D=3D 2) topology.num_lm =3D 2; else if (!dpu_kms->catalog->caps->has_3d_merge) @@ -691,10 +696,20 @@ static struct msm_display_topology dpu_encoder_get_to= pology( * 2 DSC encoders, 2 layer mixers and 1 interface * this is power optimal and can drive up to (including) 4k * screens + * But for dual display case, we prefer 4 layer mixers. Because + * the resolution is always high in the case and 4 DSCs are more + * power optimal. */ - topology.num_dsc =3D 2; - topology.num_lm =3D 2; - topology.num_intf =3D 1; + + if (intf_count =3D=3D 2) { + topology.num_dsc =3D dpu_kms->catalog->dsc_count >=3D 4 ? 4 : 2; + topology.num_lm =3D topology.num_dsc; + topology.num_intf =3D 2; + } else { + topology.num_dsc =3D 2; + topology.num_lm =3D 2; + topology.num_intf =3D 1; + } } =20 return topology; @@ -2194,8 +2209,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 63f09857025c2..a9e122243dce9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers !=3D 1) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a2038..77a7a5375d545 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,7 +24,7 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 -#define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 64e220987be56..804858e69e7da 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -35,8 +35,8 @@ #endif =20 #define STAGES_PER_PLANE 2 -#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 +#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif --=20 2.34.1