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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-12-74749c6eba33@linaro.org> References: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> In-Reply-To: <20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1737012353; l=4704; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=riXvJCYz3ZHmPNnxEFMshsGfh9DVde6M2D9iSPytzY0=; b=N90+eokB1/pHDBh9fjgX2d92pIVhyzJtSySJRwUrRkbmzYWATDHJLeNTJaYbgHelleGAuUAfc mBJojSGj0IADfqFey7Oaqj8g0qdjqTM9yBukm8HkEVL1UuEcn8CZEUK X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, only 2 pipes are used at most for a plane. A stage structure describes the configuration for a mixer pair. So only one stage is needed for current usage cases. The quad-pipe case will be added in future and 2 stages are used in the case. So extend the stage to an array with array size STAGES_PER_PLANE and blend pipes per mixer pair with configuration in the stage structure. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 42 +++++++++++++++++--------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + 2 files changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 81474823e6799..5ae640da53fbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -401,7 +401,6 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, struct dpu_hw_stage_cfg *stage_cfg ) { - uint32_t lm_idx; enum dpu_sspp sspp_idx; struct drm_plane_state *state; =20 @@ -426,8 +425,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, stage_cfg->multirect_index[stage][stage_idx] =3D pipe->multirect_index; =20 /* blend config update */ - for (lm_idx =3D 0; lm_idx < num_mixers; lm_idx++) - mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl= , sspp_idx); + mixer->lm_ctl->ops.update_pending_flush_sspp(mixer->lm_ctl, sspp_idx); } =20 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, @@ -442,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; =20 - uint32_t lm_idx, i; + uint32_t lm_idx, stage, i, pipe_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(fetch_active, SSPP_MAX); =20 @@ -463,15 +461,20 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_PLANE; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair with config in stage structure */ + for (stage =3D 0; stage < STAGES_PER_PLANE; stage++) { + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe_idx =3D i + stage * PIPES_PER_STAGE; + if (!pstate->pipe[pipe_idx].sspp) + continue; + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + &mixer[pipe_idx], cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[stage]); + } } =20 /* blend config update */ @@ -503,7 +506,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer =3D cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE]; int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -516,9 +519,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } =20 /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); =20 - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg); =20 for (i =3D 0; i < cstate->num_mixers; i++) { ctl =3D mixer[i].lm_ctl; @@ -535,8 +538,13 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crt= c) mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * There are 4 mixers at most. The first 2 are for the left half, and + * the later 2 are for the right half. + */ ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / PIPES_PER_STAGE]); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 5f010d36672cc..64e220987be56 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 +#define STAGES_PER_PLANE 2 #define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES --=20 2.34.1