From nobody Sun Feb 8 21:42:07 2026 Received: from exchange.fintech.ru (exchange.fintech.ru [195.54.195.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 467D219005D for ; Wed, 15 Jan 2025 17:12:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.54.195.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736961136; cv=none; b=CyBvR3irX9BEx7QNk+pVIOoCJLtKuggdA61qsORbCRDNuArOjwfhtzEE9DhQdAAHff1yi2TaKxtt4yDcXAbg1jXHhq0ooUb6MFJQePCJ4gVDUrtAR3b4ufXcOQ5PkQrVnzH8Gopy+6Hh4TSaz49QTsvkrNIDd0coE/+fUi8Qb3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736961136; c=relaxed/simple; bh=FfVyu0aQVxq6NlAoGtk8Pt2mPCqyNY/2awemk5iBRas=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=PBejYVvI+lN3WTmjSSFtL3VnxFMjfu/AhXQWiu7A74wf5ugeL59cjU/sScwyZ65MWcaU4c0lwLNWEyavjD5sDhHSCQRZJuFyrGhh7UOnlfjajEy3eRI+C3jU9Va0xvF+dKUQCSjgXev6ROojGhrm18iJSReW+GWyj/M1FMSxAvY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fintech.ru; spf=pass smtp.mailfrom=fintech.ru; arc=none smtp.client-ip=195.54.195.159 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=fintech.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fintech.ru Received: from Ex16-01.fintech.ru (10.0.10.18) by exchange.fintech.ru (195.54.195.159) with Microsoft SMTP Server (TLS) id 14.3.498.0; Wed, 15 Jan 2025 20:12:11 +0300 Received: from localhost (10.0.253.138) by Ex16-01.fintech.ru (10.0.10.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Wed, 15 Jan 2025 20:12:11 +0300 From: Nikita Zhandarovich To: Lee Jones CC: Nikita Zhandarovich , , Subject: [PATCH] mfd: sm501: switch to BIT() to mitigate integer overflows Date: Wed, 15 Jan 2025 09:12:06 -0800 Message-ID: <20250115171206.20308-1-n.zhandarovich@fintech.ru> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: Ex16-02.fintech.ru (10.0.10.19) To Ex16-01.fintech.ru (10.0.10.18) Content-Type: text/plain; charset="utf-8" If offset end up being high enough, right hand expression in functions like sm501_gpio_set() shifted left for that number of bits, may not fit in int type. Just in case, fix that by using BIT() both as an option safe from overflow issues and to make this step look similar to other gpio drivers. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: f61be273d369 ("sm501: add gpiolib support") Signed-off-by: Nikita Zhandarovich --- drivers/mfd/sm501.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 0469e85d72cf..7ee293b09f62 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -920,7 +920,7 @@ static void sm501_gpio_set(struct gpio_chip *chip, unsi= gned offset, int value) { struct sm501_gpio_chip *smchip =3D gpiochip_get_data(chip); struct sm501_gpio *smgpio =3D smchip->ourgpio; - unsigned long bit =3D 1 << offset; + unsigned long bit =3D BIT(offset); void __iomem *regs =3D smchip->regbase; unsigned long save; unsigned long val; @@ -946,7 +946,7 @@ static int sm501_gpio_input(struct gpio_chip *chip, uns= igned offset) struct sm501_gpio_chip *smchip =3D gpiochip_get_data(chip); struct sm501_gpio *smgpio =3D smchip->ourgpio; void __iomem *regs =3D smchip->regbase; - unsigned long bit =3D 1 << offset; + unsigned long bit =3D BIT(offset); unsigned long save; unsigned long ddr; =20 @@ -971,7 +971,7 @@ static int sm501_gpio_output(struct gpio_chip *chip, { struct sm501_gpio_chip *smchip =3D gpiochip_get_data(chip); struct sm501_gpio *smgpio =3D smchip->ourgpio; - unsigned long bit =3D 1 << offset; + unsigned long bit =3D BIT(offset); void __iomem *regs =3D smchip->regbase; unsigned long save; unsigned long val;