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([145.224.90.10]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499bbasm24853825e9.3.2025.01.15.05.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:43:13 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, broonie@kernel.org, maz@kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Mark Rutland , Oliver Upton , Anshuman Khandual , James Morse , linux-kernel@vger.kernel.org Subject: [PATCH 1/5] arm64/sysreg: Fix unbalanced closing block Date: Wed, 15 Jan 2025 13:42:53 +0000 Message-Id: <20250115134259.1864060-2-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115134259.1864060-1-james.clark@linaro.org> References: <20250115134259.1864060-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is a sysreg block so close it with one. This doesn't make a difference to the output because the script only matches on the beginning of the word to close blocks which is correct by coincidence here. Signed-off-by: James Clark --- arch/arm64/tools/sysreg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 762ee084b37c..bbe7df69da9c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2074,7 +2074,7 @@ EndEnum Res0 4:2 Field 1 ExTRE Field 0 E0TRE -EndSysregFields +EndSysreg =20 Sysreg SMPRI_EL1 3 0 1 2 4 Res0 63:4 --=20 2.34.1 From nobody Sun Dec 14 21:40:44 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28E8F243854 for ; Wed, 15 Jan 2025 13:43:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736948599; cv=none; b=MJlILbO2L07lhnIo3V9RlH3N+3kAbeb+d2AGC8czHyOZ6FrAHzlrr+t+Y/5/dx8JO+jZTeNA6Zgcl4kMu7ctfSGNVPpsik8YL8LDYYKs4Hy6Vzm+vledxYTWJ3J/y3zL7LKkcxrGhJG/+sVO+UC+ZkyNfufOZwDbiL7B+W1uiRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736948599; c=relaxed/simple; bh=FF2EoXoefL4siXVWOsmJnsiqNK8nWNKS+yBe+obt2N4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZPUHrqyj+RnbQWQCE20tKBCTYn91Mu/x1LvkBKUyWvynj7bOUkKc6MPOWLvNUg6Vj6aDoRzGVzCwXp2HUELZ9PsemgwkWFrWAfZhRiFNeQRmeHyJiGleOCW9Ofcxtumi8OoFx14jmGwF5ntXoZeGnVgSJbHtUFcnVNWzUBxuJ50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=xmoHmzNL; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xmoHmzNL" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3863494591bso3534986f8f.1 for ; Wed, 15 Jan 2025 05:43:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736948596; x=1737553396; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FL7ZkhQdK78qVjJ8hh9m+jIEQAe9pT1DEJ5hOyp5o9I=; b=xmoHmzNLj9YKn7KlBwxwPX7UlU/3NkUOUHW01Snrg/5EKh6x6BEmgFc1jDignOTZEi Qtj05sYxwTLBlMNZLh7Ka19+WDNpjOxvN84Ic5E/a8A/aevquCE4DZWbEza7Xrnb7sFZ XUw1999YVEQViE7/WCtfA/csMWuAFcZDZV6JJ69+Tx2WHLjNOP1mPXIpTG+MwsrGeA21 PBZzgdjTgDUWiojSxYf1f0iIbiPexuF0alvHShNIhwwHY35MkXczi9CIxOeXjE5gQbSB 7lhi5KIR/jg/BWWRSQfTy5Wgkju2dImA7IvKoyuE+fHQue/oyZZ0d9hwiGZXEZJaHTjF Ityw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736948596; x=1737553396; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FL7ZkhQdK78qVjJ8hh9m+jIEQAe9pT1DEJ5hOyp5o9I=; b=tjceqxQMSM+aykTRZjuXuBtgUjQ0FBMa7zS9ZLjCnOmVf20DWAOTgBCsehtvYJY59Y ESMr2+H7YyIO9WsUwam6Syb0VsI1ZPKXKvozx0BPhsDm6DaOjEgZps3VuQ2Idyux6UTC vE9s8Wbamu9MaZczlVjE3tRHesmBiL18p5WxKS3Uho55GgzGYg10Fitz0mz0aZkE9bG1 eFAcgZ81qObD94CS2TnaF0H299I1ZRZHIGKqBopdqCNYXdryo8UUMTPuib6R2kByHJat VD40qvFTY0dBUHsBrdTnISRIRULL3I8/PuGqd+IRHJDFnvApYrKB+2vfrE62+Kp1PVlZ OxHg== X-Forwarded-Encrypted: i=1; AJvYcCVxOcAnCl0X+qco8v7PMnn5v17N3CQmkva5T1zCw0FBOC+OoHMwv3GgCY6wBcJXhORfZbmjfPwmDj4UfQk=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4G8TqQGTqeRjsXQoM7EZU1c7nBzZARDezXz4u6IkqYLQNQqhj 9EhTxhe4/XBPBoLJHLx88ZK3c2x2Z5IOXcZxwr21MTH6Nt6g3xtXd8OOnYhmLVo= X-Gm-Gg: ASbGncvH9aOwEy8DA/RBgMok1eqM2KQmbYpVwMFMxdy38PTe7xkmkjFJUeYuyvDTc6M mEm7yAqPvRF+Okigt4HwQHg0+Lms/SrOKjb/1Pb5jVDo5IA1JTRCI2/QmnuR0hbQkwb5VY9OmgD faBdbHbSSnsrJlStpT1hzRI58E7OGPUt39HJ/t/V/9khWTZcD3a9c8i+m1IZc1yK0MW689Dcw5v Jcp4Pm/5KsUuflN0pislRMPmUAJi8rAmIPdd88HSgLYtia43L8p4hU= X-Google-Smtp-Source: AGHT+IHirEWQcVqlGkFPsz3lXJkoAgAhrYtf95Ok2YyQSwvsam/EPZ1NxQT2nmM6wK31QGxnvLzt+g== X-Received: by 2002:a05:6000:1f89:b0:38a:9ffb:fe2f with SMTP id ffacd0b85a97d-38a9ffc0071mr14458706f8f.0.1736948596597; Wed, 15 Jan 2025 05:43:16 -0800 (PST) Received: from pop-os.. ([145.224.90.10]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499bbasm24853825e9.3.2025.01.15.05.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:43:16 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, broonie@kernel.org, maz@kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Mark Rutland , Oliver Upton , Anshuman Khandual , James Morse , linux-kernel@vger.kernel.org Subject: [PATCH 2/5] arm64/sysreg: Enforce whole line match for closing blocks Date: Wed, 15 Jan 2025 13:42:54 +0000 Message-Id: <20250115134259.1864060-3-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115134259.1864060-1-james.clark@linaro.org> References: <20250115134259.1864060-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Match on the whole line to prevent matching on prefixes like "Endsysreg" vs "EndsysregFields". This could potentially make the script go wrong in weird ways so make it fall through to the fatal unhandled statement catcher if it doesn't fully match the current block. Signed-off-by: James Clark Reviewed-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index 1a2afc9fdd42..7c7412adf90e 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -127,7 +127,7 @@ END { next } =20 -/^EndSysregFields/ && block_current() =3D=3D "SysregFields" { +/^EndSysregFields$/ && block_current() =3D=3D "SysregFields" { if (next_bit > 0) fatal("Unspecified bits in " reg) =20 @@ -177,7 +177,7 @@ END { next } =20 -/^EndSysreg/ && block_current() =3D=3D "Sysreg" { +/^EndSysreg$/ && block_current() =3D=3D "Sysreg" { if (next_bit > 0) fatal("Unspecified bits in " reg) =20 @@ -310,7 +310,7 @@ END { next } =20 -/^EndEnum/ && block_current() =3D=3D "Enum" { +/^EndEnum$/ && block_current() =3D=3D "Enum" { =20 field =3D null msb =3D null --=20 2.34.1 From nobody Sun Dec 14 21:40:44 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76159243867 for ; Wed, 15 Jan 2025 13:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736948603; cv=none; b=n/nsHk6EUY5Tiz8jqwcHsK3HQVCEl7BJpywuA0TdHeqhC6W7niVQCqplds9nKq817cZQ99d+T7V+6po2Z9HAw3vqZsfbGxTDcvI4zNXuBg6gnN0cKA5u6Qth/9PYQnVnvbQq6PTuW/laEyqITl3SV5DYutqgSRw1FrmDgAYJ9Ig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736948603; c=relaxed/simple; bh=+kRVZqyEqiJek7zqLyxeSd2TeztXMiK8BtEGo5XjW1w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sgU5/3PdoVJyiTOCUwDwDlSwgHQn6ZfYemMFGvkQMeYQuayT17mspigZVYEtAIz/+spOXZcwEentoRlyvVFf9aTZwuTcu8I9jpxHOg7IZxEQd6trlruZY6FKdLhZ2OMloFUaKOiZJ+4AcZuX2jUY9KeKJ3F9owFNzGyvuBINyOo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=bSwcaYq4; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bSwcaYq4" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso47864875e9.3 for ; Wed, 15 Jan 2025 05:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736948600; x=1737553400; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KeZuvH3UGnQUtqtWabBejUBG0pdX8SFSDZ3OStfizlM=; b=bSwcaYq4cpkck0Vvk1q2mJfVaFZyvDkNpfAtXh6QgQ9QRaPf3q1n9rgNBClEe0KptP MJmF5jK+Q1K+cDkODsiB4JZm0CHoCR0P0gKI9e22FWvbPAQs1jo9fCwwjXFzvUqAm5m4 ByR0XYIsYRpRDcbMr1u3HiFisYwJUPuo87Y+X3mArhF+z3QsLn+dTrQ/azZvTuUgw/ND 3xFShfEdGJMS0YAyJA8GJLpdVXEoXTuDArfa1vGFQw6AseDyWd6VDDbfHTnQAHr9TlkI +0uQEn0hnCY6NyOPEUc5ICwBYdszEU1B9uMJSusscZ0ZLCF2j7y/wCgzLYhFHhOkND+K UZ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736948600; x=1737553400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KeZuvH3UGnQUtqtWabBejUBG0pdX8SFSDZ3OStfizlM=; b=TqszkYbKHPBVkmJGtc7/gIA8cZMaURhtaxytoOEqySnrXb8p745rdR4Iwz4xMU+p5F RBq8Fvuh1Qs2roOCUYbGtLZVLc5nedADAoDC3HDI2lAS8Yv8yihP55P+TxI89mEWsvcy Oozz/lVeNxl26KkHGyjMtETp8fQrI9RAF80cP66DhMfOPHeiIYwh7q3l3QGXrRwG423I OmkFpT7yB302d/lBDs4FDz0SrjFFhN8CYVfnE7DpOdXCqXoAbg2zLv19ZShyTsR9QVoY f0e60aIwGXstBhUzqAiDQlY8MiHjJ2IWFLum8dhrcWNANe0T2g5sr593RsfJVP6Cf4V1 tq8Q== X-Forwarded-Encrypted: i=1; AJvYcCVmnWbxzy/kLA2pKqkigqEji2fXEKiibvk5wQ7UkYJt02cWHUWvg2y9cK5NS8xMXp6KzexikC7UZCUd7SE=@vger.kernel.org X-Gm-Message-State: AOJu0Yzy+25y3b0FCsZEVSxuGdddLp7vBwJk+khJiCN3kD+QS3NuAMkq 6EfV+EIkgdAA93XaHqQjGN6QUyflJeAx7D/jKIwZObuXjYvQ+0dopFPyV4njoZw= X-Gm-Gg: ASbGncvA0Atf6pOvTb/EbJdQg1JGfKxmMM+vVkcEE/bAIqBhXnsxs60e0cMX0DLIYiV gBUO70ODVG8do1nLKPF7czdL6WNM9vWtMWVhUk1F7oWa6xbovkCTQM+67hrsdD0PyCTSR8vclON rMWjr4RmLWk8vrx8rtgYZk6a0EWzMaLsk3mtcloMPCRrvG9bIuxfvSknQ3mG2VhCX2lUAwTPBYT /aorya6084ijBTPWtDF20pqi+hYypZaIX+ZI987KC6+vQiJjpagLkM= X-Google-Smtp-Source: AGHT+IF6/6miVqA8lxPXwEMJFgSltM5n1uymfk4FgX+ZbGSSTlwfp9RcgUI/CSyzjF1w9ekENozQyg== X-Received: by 2002:a05:600c:1384:b0:436:1c04:aa8e with SMTP id 5b1f17b1804b1-436e26bdac1mr316746855e9.16.1736948599790; Wed, 15 Jan 2025 05:43:19 -0800 (PST) Received: from pop-os.. ([145.224.90.10]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499bbasm24853825e9.3.2025.01.15.05.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:43:19 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, broonie@kernel.org, maz@kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Mark Rutland , Oliver Upton , Anshuman Khandual , James Morse , linux-kernel@vger.kernel.org Subject: [PATCH 3/5] arm64/sysreg: Enforce whole word for opening blocks Date: Wed, 15 Jan 2025 13:42:55 +0000 Message-Id: <20250115134259.1864060-4-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115134259.1864060-1-james.clark@linaro.org> References: <20250115134259.1864060-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similarly to the previous change, opening blocks can also match on words with common prefixes. Fix it by ensuring the whole word matches. This doesn't do much more than catch trailing typos. Signed-off-by: James Clark --- arch/arm64/tools/gen-sysreg.awk | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index 7c7412adf90e..7f578216dc68 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -111,11 +111,10 @@ END { /^$/ { next } /^[\t ]*#/ { next } =20 -/^SysregFields/ && block_current() =3D=3D "Root" { +$1 =3D=3D "SysregFields" && block_current() =3D=3D "Root" { block_push("SysregFields") =20 expect_fields(2) - reg =3D $2 =20 res0 =3D "UL(0)" @@ -145,7 +144,7 @@ END { next } =20 -/^Sysreg/ && block_current() =3D=3D "Root" { +$1 =3D=3D "Sysreg" && block_current() =3D=3D "Root" { block_push("Sysreg") =20 expect_fields(7) @@ -206,7 +205,7 @@ END { =20 # Currently this is effectivey a comment, in future we may want to emit # defines for the fields. -(/^Fields/ || /^Mapping/) && block_current() =3D=3D "Sysreg" { +($1 =3D=3D "Fields" || $1 =3D=3D "Mapping") && block_current() =3D=3D "Sys= reg" { expect_fields(2) =20 if (next_bit !=3D 63) @@ -224,7 +223,7 @@ END { } =20 =20 -/^Res0/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { +$1 =3D=3D "Res0" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { expect_fields(2) parse_bitdef(reg, "RES0", $2) field =3D "RES0_" msb "_" lsb @@ -234,7 +233,7 @@ END { next } =20 -/^Res1/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { +$1 =3D=3D "Res1" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { expect_fields(2) parse_bitdef(reg, "RES1", $2) field =3D "RES1_" msb "_" lsb @@ -244,7 +243,7 @@ END { next } =20 -/^Unkn/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { +$1 =3D=3D "Unkn" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { expect_fields(2) parse_bitdef(reg, "UNKN", $2) field =3D "UNKN_" msb "_" lsb @@ -254,7 +253,7 @@ END { next } =20 -/^Field/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sy= sregFields") { +$1 =3D=3D "Field" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { expect_fields(3) field =3D $3 parse_bitdef(reg, field, $2) @@ -265,14 +264,14 @@ END { next } =20 -/^Raz/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sysr= egFields") { +$1 =3D=3D "Raz" && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { expect_fields(2) parse_bitdef(reg, field, $2) =20 next } =20 -/^SignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { +$1 =3D=3D "SignedEnum" && (block_current() =3D=3D "Sysreg" || block_curren= t() =3D=3D "SysregFields") { block_push("Enum") =20 expect_fields(3) @@ -285,7 +284,7 @@ END { next } =20 -/^UnsignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { +$1 =3D=3D "UnsignedEnum" && (block_current() =3D=3D "Sysreg" || block_curr= ent() =3D=3D "SysregFields") { block_push("Enum") =20 expect_fields(3) @@ -298,7 +297,7 @@ END { next } =20 -/^Enum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { +$1 =3D=3D "Enum" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { block_push("Enum") =20 expect_fields(3) --=20 2.34.1 From nobody Sun Dec 14 21:40:44 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3817924387D for ; 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([145.224.90.10]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499bbasm24853825e9.3.2025.01.15.05.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:43:23 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, broonie@kernel.org, maz@kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Mark Rutland , Oliver Upton , Anshuman Khandual , James Morse , linux-kernel@vger.kernel.org Subject: [PATCH 4/5] arm64/sysreg: Sort sysreg by encoding Date: Wed, 15 Jan 2025 13:42:56 +0000 Message-Id: <20250115134259.1864060-5-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115134259.1864060-1-james.clark@linaro.org> References: <20250115134259.1864060-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's mostly been sorted by sysreg encoding, but not 100%. Sort it so new entries can be added without wondering where to put them. The following python script was used to sort, keeping the top level SysregFields and comments next to their current Sysreg entries by splitting on "EndSysreg": # cat arch/arm64/tools/sysreg | python3 sort.py > sorted-sysreg import sys, re def key(block): reg =3D r"\w+\s+(\d+)\s+(\d+)\s+(\d+)\s+(\d+)\s+(\d+)" match =3D re.search(reg, block) sort_val =3D ''.join(f"{int(n):02d}" for n in match.groups()) return (sort_val, block) sysreg =3D sys.stdin.read().split("\nEndSysreg\n")[:-1] sysreg =3D sorted(sysreg, key=3Dkey) print("\nEndSysreg\n".join(sysreg) + "\nEndSysreg") Tested by diffing sorted outputs: $ diff <(sort arch/arm64/include/generated/asm/sysreg-defs.h) \ <(sort before-sysreg-defs.h) -s Files /dev/fd/63 and /dev/fd/62 are identical Signed-off-by: James Clark --- arch/arm64/tools/sysreg | 1006 +++++++++++++++++++-------------------- 1 file changed, 503 insertions(+), 503 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index bbe7df69da9c..fe1c58367ceb 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -661,71 +661,71 @@ UnsignedEnum 3:0 SEVL EndEnum EndSysreg =20 -Sysreg ID_ISAR6_EL1 3 0 0 2 7 -Res0 63:28 -UnsignedEnum 27:24 I8MM +Sysreg ID_MMFR4_EL1 3 0 0 2 6 +Res0 63:32 +UnsignedEnum 31:28 EVT 0b0000 NI - 0b0001 IMP + 0b0001 NO_TLBIS + 0b0010 TLBIS EndEnum -UnsignedEnum 23:20 BF16 +UnsignedEnum 27:24 CCIDX 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 19:16 SPECRES +UnsignedEnum 23:20 LSM 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 15:12 SB +UnsignedEnum 19:16 HPDS + 0b0000 NI + 0b0001 AA32HPD + 0b0010 HPDS2 +EndEnum +UnsignedEnum 15:12 CnP 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 11:8 FHM +UnsignedEnum 11:8 XNX 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 7:4 DP +UnsignedEnum 7:4 AC2 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 3:0 JSCVT +UnsignedEnum 3:0 SpecSEI 0b0000 NI 0b0001 IMP EndEnum EndSysreg =20 -Sysreg ID_MMFR4_EL1 3 0 0 2 6 -Res0 63:32 -UnsignedEnum 31:28 EVT - 0b0000 NI - 0b0001 NO_TLBIS - 0b0010 TLBIS -EndEnum -UnsignedEnum 27:24 CCIDX +Sysreg ID_ISAR6_EL1 3 0 0 2 7 +Res0 63:28 +UnsignedEnum 27:24 I8MM 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 23:20 LSM +UnsignedEnum 23:20 BF16 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 19:16 HPDS +UnsignedEnum 19:16 SPECRES 0b0000 NI - 0b0001 AA32HPD - 0b0010 HPDS2 + 0b0001 IMP EndEnum -UnsignedEnum 15:12 CnP +UnsignedEnum 15:12 SB 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 11:8 XNX +UnsignedEnum 11:8 FHM 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 7:4 AC2 +UnsignedEnum 7:4 DP 0b0000 NI 0b0001 IMP EndEnum -UnsignedEnum 3:0 SpecSEI +UnsignedEnum 3:0 JSCVT 0b0000 NI 0b0001 IMP EndEnum @@ -2064,6 +2064,16 @@ Field 17:16 ZEN Res0 15:0 EndSysreg =20 +SysregFields ZCR_ELx +Res0 63:9 +Raz 8:4 +Field 3:0 LEN +EndSysregFields + +Sysreg ZCR_EL1 3 0 1 2 0 +Fields ZCR_ELx +EndSysreg + Sysreg TRFCR_EL1 3 0 1 2 1 Res0 63:7 UnsignedEnum 6:5 TS @@ -2081,16 +2091,6 @@ Res0 63:4 Field 3:0 PRIORITY EndSysreg =20 -SysregFields ZCR_ELx -Res0 63:9 -Raz 8:4 -Field 3:0 LEN -EndSysregFields - -Sysreg ZCR_EL1 3 0 1 2 0 -Fields ZCR_ELx -EndSysreg - SysregFields SMCR_ELx Res0 63:32 Field 31 FA64 @@ -2104,6 +2104,36 @@ Sysreg SMCR_EL1 3 0 1 2 6 Fields SMCR_ELx EndSysreg =20 +SysregFields TTBRx_EL1 +Field 63:48 ASID +Field 47:1 BADDR +Field 0 CnP +EndSysregFields + +Sysreg TTBR0_EL1 3 0 2 0 0 +Fields TTBRx_EL1 +EndSysreg + +Sysreg TTBR1_EL1 3 0 2 0 1 +Fields TTBRx_EL1 +EndSysreg + +Sysreg TCR2_EL1 3 0 2 0 3 +Res0 63:16 +Field 15 DisCH1 +Field 14 DisCH0 +Res0 13:12 +Field 11 HAFT +Field 10 PTTWI +Res0 9:6 +Field 5 D128 +Field 4 AIE +Field 3 POE +Field 2 E0POE +Field 1 PIE +Field 0 PnCH +EndSysreg + SysregFields GCSCR_ELx Res0 63:10 Field 9 STREn @@ -2149,31 +2179,6 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg =20 -Sysreg PMICNTR_EL0 3 3 9 4 0 -Field 63:0 ICNT -EndSysreg - -Sysreg PMICFILTR_EL0 3 3 9 6 0 -Res0 63:59 -Field 58 SYNC -Field 57:56 VS -Res0 55:32 -Field 31 P -Field 30 U -Field 29 NSK -Field 28 NSU -Field 27 NSH -Field 26 M -Res0 25 -Field 24 SH -Field 23 T -Field 22 RLK -Field 21 RLU -Field 20 RLH -Res0 19:16 -Field 15:0 evtCount -EndSysreg - Sysreg PMSCR_EL1 3 0 9 9 0 Res0 63:8 Field 7:6 PCT @@ -2298,72 +2303,283 @@ Field 4 P Field 3:0 ALIGN EndSysreg =20 -Sysreg PMUACR_EL1 3 0 9 14 4 -Res0 63:33 -Field 32 F0 -Field 31 C -Field 30:0 P +Sysreg TRBLIMITR_EL1 3 0 9 11 0 +Field 63:12 LIMIT +Res0 11:7 +Field 6 XE +Field 5 nVM +Enum 4:3 TM + 0b00 STOP + 0b01 IRQ + 0b11 IGNR +EndEnum +Enum 2:1 FM + 0b00 FILL + 0b01 WRAP + 0b11 CBUF +EndEnum +Field 0 E EndSysreg =20 -Sysreg PMSELR_EL0 3 3 9 12 5 -Res0 63:5 -Field 4:0 SEL +Sysreg TRBPTR_EL1 3 0 9 11 1 +Field 63:0 PTR EndSysreg =20 -SysregFields CONTEXTIDR_ELx -Res0 63:32 -Field 31:0 PROCID -EndSysregFields - -Sysreg CONTEXTIDR_EL1 3 0 13 0 1 -Fields CONTEXTIDR_ELx +Sysreg TRBBASER_EL1 3 0 9 11 2 +Field 63:12 BASE +Res0 11:0 EndSysreg =20 -Sysreg RCWSMASK_EL1 3 0 13 0 3 -Field 63:0 RCWSMASK +Sysreg TRBSR_EL1 3 0 9 11 3 +Res0 63:56 +Field 55:32 MSS2 +Field 31:26 EC +Res0 25:24 +Field 23 DAT +Field 22 IRQ +Field 21 TRG +Field 20 WRAP +Res0 19 +Field 18 EA +Field 17 S +Res0 16 +Field 15:0 MSS EndSysreg =20 -Sysreg TPIDR_EL1 3 0 13 0 4 -Field 63:0 ThreadID +Sysreg TRBMAR_EL1 3 0 9 11 4 +Res0 63:12 +Enum 11:10 PAS + 0b00 SECURE + 0b01 NON_SECURE + 0b10 ROOT + 0b11 REALM +EndEnum +Enum 9:8 SH + 0b00 NON_SHAREABLE + 0b10 OUTER_SHAREABLE + 0b11 INNER_SHAREABLE +EndEnum +Field 7:0 Attr EndSysreg =20 -Sysreg RCWMASK_EL1 3 0 13 0 6 -Field 63:0 RCWMASK +Sysreg TRBTRG_EL1 3 0 9 11 6 +Res0 63:32 +Field 31:0 TRG EndSysreg =20 -Sysreg SCXTNUM_EL1 3 0 13 0 7 -Field 63:0 SoftwareContextNumber +Sysreg TRBIDR_EL1 3 0 9 11 7 +Res0 63:12 +Enum 11:8 EA + 0b0000 NON_DESC + 0b0001 IGNORE + 0b0010 SERROR +EndEnum +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 Align EndSysreg =20 -# The bit layout for CCSIDR_EL1 depends on whether FEAT_CCIDX is implement= ed. -# The following is for case when FEAT_CCIDX is not implemented. -Sysreg CCSIDR_EL1 3 1 0 0 0 -Res0 63:32 -Unkn 31:28 -Field 27:13 NumSets -Field 12:3 Associativity -Field 2:0 LineSize +Sysreg PMUACR_EL1 3 0 9 14 4 +Res0 63:33 +Field 32 F0 +Field 31 C +Field 30:0 P EndSysreg =20 -Sysreg CLIDR_EL1 3 1 0 0 1 -Res0 63:47 -Field 46:33 Ttypen -Field 32:30 ICB -Field 29:27 LoUU -Field 26:24 LoC -Field 23:21 LoUIS -Field 20:18 Ctype7 -Field 17:15 Ctype6 -Field 14:12 Ctype5 -Field 11:9 Ctype4 -Field 8:6 Ctype3 -Field 5:3 Ctype2 -Field 2:0 Ctype1 -EndSysreg +SysregFields MAIR2_ELx +Field 63:56 Attr7 +Field 55:48 Attr6 +Field 47:40 Attr5 +Field 39:32 Attr4 +Field 31:24 Attr3 +Field 23:16 Attr2 +Field 15:8 Attr1 +Field 7:0 Attr0 +EndSysregFields =20 -Sysreg CCSIDR2_EL1 3 1 0 0 2 -Res0 63:24 -Field 23:0 NumSets +Sysreg MAIR2_EL1 3 0 10 2 1 +Fields MAIR2_ELx +EndSysreg + +SysregFields PIRx_ELx +Field 63:60 Perm15 +Field 59:56 Perm14 +Field 55:52 Perm13 +Field 51:48 Perm12 +Field 47:44 Perm11 +Field 43:40 Perm10 +Field 39:36 Perm9 +Field 35:32 Perm8 +Field 31:28 Perm7 +Field 27:24 Perm6 +Field 23:20 Perm5 +Field 19:16 Perm4 +Field 15:12 Perm3 +Field 11:8 Perm2 +Field 7:4 Perm1 +Field 3:0 Perm0 +EndSysregFields + +Sysreg PIRE0_EL1 3 0 10 2 2 +Fields PIRx_ELx +EndSysreg + +Sysreg PIR_EL1 3 0 10 2 3 +Fields PIRx_ELx +EndSysreg + +Sysreg POR_EL1 3 0 10 2 4 +Fields PIRx_ELx +EndSysreg + +Sysreg S2POR_EL1 3 0 10 2 5 +Fields PIRx_ELx +EndSysreg + +Sysreg AMAIR2_EL1 3 0 10 3 1 +Field 63:0 ImpDef +EndSysreg + +Sysreg LORSA_EL1 3 0 10 4 0 +Res0 63:52 +Field 51:16 SA +Res0 15:1 +Field 0 Valid +EndSysreg + +Sysreg LOREA_EL1 3 0 10 4 1 +Res0 63:52 +Field 51:48 EA_51_48 +Field 47:16 EA_47_16 +Res0 15:0 +EndSysreg + +Sysreg LORN_EL1 3 0 10 4 2 +Res0 63:8 +Field 7:0 Num +EndSysreg + +Sysreg LORC_EL1 3 0 10 4 3 +Res0 63:10 +Field 9:2 DS +Res0 1 +Field 0 EN +EndSysreg + +Sysreg MPAMIDR_EL1 3 0 10 4 4 +Res0 63:62 +Field 61 HAS_SDEFLT +Field 60 HAS_FORCE_NS +Field 59 SP4 +Field 58 HAS_TIDR +Field 57 HAS_ALTSP +Res0 56:40 +Field 39:32 PMG_MAX +Res0 31:21 +Field 20:18 VPMR_MAX +Field 17 HAS_HCR +Res0 16 +Field 15:0 PARTID_MAX +EndSysreg + +Sysreg LORID_EL1 3 0 10 4 7 +Res0 63:24 +Field 23:16 LD +Res0 15:8 +Field 7:0 LR +EndSysreg + +Sysreg MPAM1_EL1 3 0 10 5 0 +Field 63 MPAMEN +Res0 62:61 +Field 60 FORCED_NS +Res0 59:55 +Field 54 ALTSP_FRCD +Res0 53:48 +Field 47:40 PMG_D +Field 39:32 PMG_I +Field 31:16 PARTID_D +Field 15:0 PARTID_I +EndSysreg + +Sysreg MPAM0_EL1 3 0 10 5 1 +Res0 63:48 +Field 47:40 PMG_D +Field 39:32 PMG_I +Field 31:16 PARTID_D +Field 15:0 PARTID_I +EndSysreg + +Sysreg ISR_EL1 3 0 12 1 0 +Res0 63:11 +Field 10 IS +Field 9 FS +Field 8 A +Field 7 I +Field 6 F +Res0 5:0 +EndSysreg + +Sysreg ICC_NMIAR1_EL1 3 0 12 9 5 +Res0 63:24 +Field 23:0 INTID +EndSysreg + +SysregFields CONTEXTIDR_ELx +Res0 63:32 +Field 31:0 PROCID +EndSysregFields + +Sysreg CONTEXTIDR_EL1 3 0 13 0 1 +Fields CONTEXTIDR_ELx +EndSysreg + +Sysreg RCWSMASK_EL1 3 0 13 0 3 +Field 63:0 RCWSMASK +EndSysreg + +Sysreg TPIDR_EL1 3 0 13 0 4 +Field 63:0 ThreadID +EndSysreg + +Sysreg RCWMASK_EL1 3 0 13 0 6 +Field 63:0 RCWMASK +EndSysreg + +Sysreg SCXTNUM_EL1 3 0 13 0 7 +Field 63:0 SoftwareContextNumber +EndSysreg + +# The bit layout for CCSIDR_EL1 depends on whether FEAT_CCIDX is implement= ed. +# The following is for case when FEAT_CCIDX is not implemented. +Sysreg CCSIDR_EL1 3 1 0 0 0 +Res0 63:32 +Unkn 31:28 +Field 27:13 NumSets +Field 12:3 Associativity +Field 2:0 LineSize +EndSysreg + +Sysreg CLIDR_EL1 3 1 0 0 1 +Res0 63:47 +Field 46:33 Ttypen +Field 32:30 ICB +Field 29:27 LoUU +Field 26:24 LoC +Field 23:21 LoUIS +Field 20:18 Ctype7 +Field 17:15 Ctype6 +Field 14:12 Ctype5 +Field 11:9 Ctype4 +Field 8:6 Ctype3 +Field 5:3 Ctype2 +Field 2:0 Ctype1 +EndSysreg + +Sysreg CCSIDR2_EL1 3 1 0 0 2 +Res0 63:24 +Field 23:0 NumSets EndSysreg =20 Sysreg GMID_EL1 3 1 0 0 4 @@ -2448,6 +2664,40 @@ UnsignedEnum 2:0 F8S1 EndEnum EndSysreg =20 +Sysreg PMICNTR_EL0 3 3 9 4 0 +Field 63:0 ICNT +EndSysreg + +Sysreg PMICFILTR_EL0 3 3 9 6 0 +Res0 63:59 +Field 58 SYNC +Field 57:56 VS +Res0 55:32 +Field 31 P +Field 30 U +Field 29 NSK +Field 28 NSU +Field 27 NSH +Field 26 M +Res0 25 +Field 24 SH +Field 23 T +Field 22 RLK +Field 21 RLU +Field 20 RLH +Res0 19:16 +Field 15:0 evtCount +EndSysreg + +Sysreg PMSELR_EL0 3 3 9 12 5 +Res0 63:5 +Field 4:0 SEL +EndSysreg + +Sysreg POR_EL0 3 3 10 2 4 +Fields PIRx_ELx +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 @@ -2625,6 +2875,10 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg ZCR_EL2 3 4 1 2 0 +Fields ZCR_ELx +EndSysreg + Sysreg TRFCR_EL2 3 4 1 2 1 Res0 63:7 UnsignedEnum 6:5 TS @@ -2640,18 +2894,114 @@ Field 1 E2TRE Field 0 E0HTRE EndSysreg =20 +Sysreg HCRX_EL2 3 4 1 2 2 +Res0 63:25 +Field 24 PACMEn +Field 23 EnFPM +Field 22 GCSEn +Field 21 EnIDCP128 +Field 20 EnSDERR +Field 19 TMEA +Field 18 EnSNERR +Field 17 D128En +Field 16 PTTWI +Field 15 SCTLR2En +Field 14 TCR2En +Res0 13:12 +Field 11 MSCEn +Field 10 MCE2 +Field 9 CMOW +Field 8 VFNMI +Field 7 VINMI +Field 6 TALLINT +Field 5 SMPME +Field 4 FGTnXS +Field 3 FnXS +Field 2 EnASR +Field 1 EnALS +Field 0 EnAS0 +EndSysreg =20 -Sysreg HDFGRTR_EL2 3 4 3 1 4 -Field 63 PMBIDR_EL1 -Field 62 nPMSNEVFR_EL1 -Field 61 nBRBDATA -Field 60 nBRBCTL -Field 59 nBRBIDR -Field 58 PMCEIDn_EL0 -Field 57 PMUSERENR_EL0 -Field 56 TRBTRG_EL1 -Field 55 TRBSR_EL1 -Field 54 TRBPTR_EL1 +Sysreg SMPRIMAP_EL2 3 4 1 2 5 +Field 63:60 P15 +Field 59:56 P14 +Field 55:52 P13 +Field 51:48 P12 +Field 47:44 P11 +Field 43:40 P10 +Field 39:36 F9 +Field 35:32 P8 +Field 31:28 P7 +Field 27:24 P6 +Field 23:20 P5 +Field 19:16 P4 +Field 15:12 P3 +Field 11:8 P2 +Field 7:4 P1 +Field 3:0 P0 +EndSysreg + +Sysreg SMCR_EL2 3 4 1 2 6 +Fields SMCR_ELx +EndSysreg + +Sysreg TCR2_EL2 3 4 2 0 3 +Res0 63:16 +Field 15 DisCH1 +Field 14 DisCH0 +Field 13 AMEC1 +Field 12 AMEC0 +Field 11 HAFT +Field 10 PTTWI +Res0 9:6 +Field 5 D128 +Field 4 AIE +Field 3 POE +Field 2 E0POE +Field 1 PIE +Field 0 PnCH +EndSysreg + +Sysreg GCSCR_EL2 3 4 2 5 0 +Fields GCSCR_ELx +EndSysreg + +Sysreg GCSPR_EL2 3 4 2 5 1 +Fields GCSPR_ELx +EndSysreg + +Sysreg DACR32_EL2 3 4 3 0 0 +Res0 63:32 +Field 31:30 D15 +Field 29:28 D14 +Field 27:26 D13 +Field 25:24 D12 +Field 23:22 D11 +Field 21:20 D10 +Field 19:18 D9 +Field 17:16 D8 +Field 15:14 D7 +Field 13:12 D6 +Field 11:10 D5 +Field 9:8 D4 +Field 7:6 D3 +Field 5:4 D2 +Field 3:2 D1 +Field 1:0 D0 +EndSysreg + + +Sysreg HDFGRTR_EL2 3 4 3 1 4 +Field 63 PMBIDR_EL1 +Field 62 nPMSNEVFR_EL1 +Field 61 nBRBDATA +Field 60 nBRBCTL +Field 59 nBRBIDR +Field 58 PMCEIDn_EL0 +Field 57 PMUSERENR_EL0 +Field 56 TRBTRG_EL1 +Field 55 TRBSR_EL1 +Field 54 TRBPTR_EL1 Field 53 TRBMAR_EL1 Field 52 TRBLIMITR_EL1 Field 51 TRBIDR_EL1 @@ -2813,89 +3163,6 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg =20 -Sysreg ZCR_EL2 3 4 1 2 0 -Fields ZCR_ELx -EndSysreg - -Sysreg HCRX_EL2 3 4 1 2 2 -Res0 63:25 -Field 24 PACMEn -Field 23 EnFPM -Field 22 GCSEn -Field 21 EnIDCP128 -Field 20 EnSDERR -Field 19 TMEA -Field 18 EnSNERR -Field 17 D128En -Field 16 PTTWI -Field 15 SCTLR2En -Field 14 TCR2En -Res0 13:12 -Field 11 MSCEn -Field 10 MCE2 -Field 9 CMOW -Field 8 VFNMI -Field 7 VINMI -Field 6 TALLINT -Field 5 SMPME -Field 4 FGTnXS -Field 3 FnXS -Field 2 EnASR -Field 1 EnALS -Field 0 EnAS0 -EndSysreg - -Sysreg SMPRIMAP_EL2 3 4 1 2 5 -Field 63:60 P15 -Field 59:56 P14 -Field 55:52 P13 -Field 51:48 P12 -Field 47:44 P11 -Field 43:40 P10 -Field 39:36 F9 -Field 35:32 P8 -Field 31:28 P7 -Field 27:24 P6 -Field 23:20 P5 -Field 19:16 P4 -Field 15:12 P3 -Field 11:8 P2 -Field 7:4 P1 -Field 3:0 P0 -EndSysreg - -Sysreg SMCR_EL2 3 4 1 2 6 -Fields SMCR_ELx -EndSysreg - -Sysreg GCSCR_EL2 3 4 2 5 0 -Fields GCSCR_ELx -EndSysreg - -Sysreg GCSPR_EL2 3 4 2 5 1 -Fields GCSPR_ELx -EndSysreg - -Sysreg DACR32_EL2 3 4 3 0 0 -Res0 63:32 -Field 31:30 D15 -Field 29:28 D14 -Field 27:26 D13 -Field 25:24 D12 -Field 23:22 D11 -Field 21:20 D10 -Field 19:18 D9 -Field 17:16 D8 -Field 15:14 D7 -Field 13:12 D6 -Field 11:10 D5 -Field 9:8 D4 -Field 7:6 D3 -Field 5:4 D2 -Field 3:2 D1 -Field 1:0 D0 -EndSysreg - Sysreg FAR_EL2 3 4 6 0 0 Field 63:0 ADDR EndSysreg @@ -2915,6 +3182,30 @@ Field 1 E2SPE Field 0 E0HSPE EndSysreg =20 +Sysreg MAIR2_EL2 3 4 10 1 1 +Fields MAIR2_ELx +EndSysreg + +Sysreg PIRE0_EL2 3 4 10 2 2 +Fields PIRx_ELx +EndSysreg + +Sysreg PIR_EL2 3 4 10 2 3 +Fields PIRx_ELx +EndSysreg + +Sysreg POR_EL2 3 4 10 2 4 +Fields PIRx_ELx +EndSysreg + +Sysreg S2PIR_EL2 3 4 10 2 5 +Fields PIRx_ELx +EndSysreg + +Sysreg AMAIR2_EL2 3 4 10 3 1 +Field 63:0 ImpDef +EndSysreg + Sysreg MPAMHCR_EL2 3 4 10 4 0 Res0 63:32 Field 31 TRAP_MPAMIDR_EL1 @@ -3059,6 +3350,10 @@ Sysreg SMCR_EL12 3 5 1 2 6 Mapping SMCR_EL1 EndSysreg =20 +Sysreg TCR2_EL12 3 5 2 0 3 +Mapping TCR2_EL1 +EndSysreg + Sysreg GCSCR_EL12 3 5 2 5 0 Mapping GCSCR_EL1 EndSysreg @@ -3071,317 +3366,22 @@ Sysreg FAR_EL12 3 5 6 0 0 Field 63:0 ADDR EndSysreg =20 -Sysreg MPAM1_EL12 3 5 10 5 0 -Fields MPAM1_ELx -EndSysreg - -Sysreg CONTEXTIDR_EL12 3 5 13 0 1 -Mapping CONTEXTIDR_EL1 -EndSysreg - -SysregFields TTBRx_EL1 -Field 63:48 ASID -Field 47:1 BADDR -Field 0 CnP -EndSysregFields - -Sysreg TTBR0_EL1 3 0 2 0 0 -Fields TTBRx_EL1 -EndSysreg - -Sysreg TTBR1_EL1 3 0 2 0 1 -Fields TTBRx_EL1 -EndSysreg - -Sysreg TCR2_EL1 3 0 2 0 3 -Res0 63:16 -Field 15 DisCH1 -Field 14 DisCH0 -Res0 13:12 -Field 11 HAFT -Field 10 PTTWI -Res0 9:6 -Field 5 D128 -Field 4 AIE -Field 3 POE -Field 2 E0POE -Field 1 PIE -Field 0 PnCH -EndSysreg - -Sysreg TCR2_EL12 3 5 2 0 3 -Mapping TCR2_EL1 -EndSysreg - -Sysreg TCR2_EL2 3 4 2 0 3 -Res0 63:16 -Field 15 DisCH1 -Field 14 DisCH0 -Field 13 AMEC1 -Field 12 AMEC0 -Field 11 HAFT -Field 10 PTTWI -Res0 9:6 -Field 5 D128 -Field 4 AIE -Field 3 POE -Field 2 E0POE -Field 1 PIE -Field 0 PnCH -EndSysreg - -SysregFields MAIR2_ELx -Field 63:56 Attr7 -Field 55:48 Attr6 -Field 47:40 Attr5 -Field 39:32 Attr4 -Field 31:24 Attr3 -Field 23:16 Attr2 -Field 15:8 Attr1 -Field 7:0 Attr0 -EndSysregFields - -Sysreg MAIR2_EL1 3 0 10 2 1 -Fields MAIR2_ELx -EndSysreg - -Sysreg MAIR2_EL2 3 4 10 1 1 -Fields MAIR2_ELx -EndSysreg - -Sysreg AMAIR2_EL1 3 0 10 3 1 -Field 63:0 ImpDef -EndSysreg - -Sysreg AMAIR2_EL2 3 4 10 3 1 -Field 63:0 ImpDef -EndSysreg - -SysregFields PIRx_ELx -Field 63:60 Perm15 -Field 59:56 Perm14 -Field 55:52 Perm13 -Field 51:48 Perm12 -Field 47:44 Perm11 -Field 43:40 Perm10 -Field 39:36 Perm9 -Field 35:32 Perm8 -Field 31:28 Perm7 -Field 27:24 Perm6 -Field 23:20 Perm5 -Field 19:16 Perm4 -Field 15:12 Perm3 -Field 11:8 Perm2 -Field 7:4 Perm1 -Field 3:0 Perm0 -EndSysregFields - -Sysreg PIRE0_EL1 3 0 10 2 2 -Fields PIRx_ELx -EndSysreg - Sysreg PIRE0_EL12 3 5 10 2 2 Mapping PIRE0_EL1 EndSysreg =20 -Sysreg PIRE0_EL2 3 4 10 2 2 -Fields PIRx_ELx -EndSysreg - -Sysreg PIR_EL1 3 0 10 2 3 -Fields PIRx_ELx -EndSysreg - Sysreg PIR_EL12 3 5 10 2 3 Mapping PIR_EL1 EndSysreg =20 -Sysreg PIR_EL2 3 4 10 2 3 -Fields PIRx_ELx -EndSysreg - -Sysreg POR_EL0 3 3 10 2 4 -Fields PIRx_ELx -EndSysreg - -Sysreg POR_EL1 3 0 10 2 4 -Fields PIRx_ELx -EndSysreg - -Sysreg POR_EL2 3 4 10 2 4 -Fields PIRx_ELx -EndSysreg - Sysreg POR_EL12 3 5 10 2 4 Mapping POR_EL1 EndSysreg =20 -Sysreg S2POR_EL1 3 0 10 2 5 -Fields PIRx_ELx -EndSysreg - -Sysreg S2PIR_EL2 3 4 10 2 5 -Fields PIRx_ELx -EndSysreg - -Sysreg LORSA_EL1 3 0 10 4 0 -Res0 63:52 -Field 51:16 SA -Res0 15:1 -Field 0 Valid -EndSysreg - -Sysreg LOREA_EL1 3 0 10 4 1 -Res0 63:52 -Field 51:48 EA_51_48 -Field 47:16 EA_47_16 -Res0 15:0 -EndSysreg - -Sysreg LORN_EL1 3 0 10 4 2 -Res0 63:8 -Field 7:0 Num -EndSysreg - -Sysreg LORC_EL1 3 0 10 4 3 -Res0 63:10 -Field 9:2 DS -Res0 1 -Field 0 EN -EndSysreg - -Sysreg MPAMIDR_EL1 3 0 10 4 4 -Res0 63:62 -Field 61 HAS_SDEFLT -Field 60 HAS_FORCE_NS -Field 59 SP4 -Field 58 HAS_TIDR -Field 57 HAS_ALTSP -Res0 56:40 -Field 39:32 PMG_MAX -Res0 31:21 -Field 20:18 VPMR_MAX -Field 17 HAS_HCR -Res0 16 -Field 15:0 PARTID_MAX -EndSysreg - -Sysreg LORID_EL1 3 0 10 4 7 -Res0 63:24 -Field 23:16 LD -Res0 15:8 -Field 7:0 LR -EndSysreg - -Sysreg MPAM1_EL1 3 0 10 5 0 -Field 63 MPAMEN -Res0 62:61 -Field 60 FORCED_NS -Res0 59:55 -Field 54 ALTSP_FRCD -Res0 53:48 -Field 47:40 PMG_D -Field 39:32 PMG_I -Field 31:16 PARTID_D -Field 15:0 PARTID_I -EndSysreg - -Sysreg MPAM0_EL1 3 0 10 5 1 -Res0 63:48 -Field 47:40 PMG_D -Field 39:32 PMG_I -Field 31:16 PARTID_D -Field 15:0 PARTID_I -EndSysreg - -Sysreg ISR_EL1 3 0 12 1 0 -Res0 63:11 -Field 10 IS -Field 9 FS -Field 8 A -Field 7 I -Field 6 F -Res0 5:0 -EndSysreg - -Sysreg ICC_NMIAR1_EL1 3 0 12 9 5 -Res0 63:24 -Field 23:0 INTID -EndSysreg - -Sysreg TRBLIMITR_EL1 3 0 9 11 0 -Field 63:12 LIMIT -Res0 11:7 -Field 6 XE -Field 5 nVM -Enum 4:3 TM - 0b00 STOP - 0b01 IRQ - 0b11 IGNR -EndEnum -Enum 2:1 FM - 0b00 FILL - 0b01 WRAP - 0b11 CBUF -EndEnum -Field 0 E -EndSysreg - -Sysreg TRBPTR_EL1 3 0 9 11 1 -Field 63:0 PTR -EndSysreg - -Sysreg TRBBASER_EL1 3 0 9 11 2 -Field 63:12 BASE -Res0 11:0 -EndSysreg - -Sysreg TRBSR_EL1 3 0 9 11 3 -Res0 63:56 -Field 55:32 MSS2 -Field 31:26 EC -Res0 25:24 -Field 23 DAT -Field 22 IRQ -Field 21 TRG -Field 20 WRAP -Res0 19 -Field 18 EA -Field 17 S -Res0 16 -Field 15:0 MSS -EndSysreg - -Sysreg TRBMAR_EL1 3 0 9 11 4 -Res0 63:12 -Enum 11:10 PAS - 0b00 SECURE - 0b01 NON_SECURE - 0b10 ROOT - 0b11 REALM -EndEnum -Enum 9:8 SH - 0b00 NON_SHAREABLE - 0b10 OUTER_SHAREABLE - 0b11 INNER_SHAREABLE -EndEnum -Field 7:0 Attr -EndSysreg - -Sysreg TRBTRG_EL1 3 0 9 11 6 -Res0 63:32 -Field 31:0 TRG +Sysreg MPAM1_EL12 3 5 10 5 0 +Fields MPAM1_ELx EndSysreg =20 -Sysreg TRBIDR_EL1 3 0 9 11 7 -Res0 63:12 -Enum 11:8 EA - 0b0000 NON_DESC - 0b0001 IGNORE - 0b0010 SERROR -EndEnum -Res0 7:6 -Field 5 F -Field 4 P -Field 3:0 Align +Sysreg CONTEXTIDR_EL12 3 5 13 0 1 +Mapping CONTEXTIDR_EL1 EndSysreg --=20 2.34.1 From nobody Sun Dec 14 21:40:44 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A64924387C for ; Wed, 15 Jan 2025 13:43:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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([145.224.90.10]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7499bbasm24853825e9.3.2025.01.15.05.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:43:26 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, robh@kernel.org, broonie@kernel.org, maz@kernel.org Cc: James Clark , Catalin Marinas , Will Deacon , Mark Rutland , Oliver Upton , Anshuman Khandual , James Morse , linux-kernel@vger.kernel.org Subject: [PATCH 5/5] arm64/sysreg: Enforce sorting Date: Wed, 15 Jan 2025 13:42:57 +0000 Message-Id: <20250115134259.1864060-6-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250115134259.1864060-1-james.clark@linaro.org> References: <20250115134259.1864060-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make an unsorted sysreg file a build error so it stays sorted. Signed-off-by: James Clark Reviewed-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index 7f578216dc68..00a8391f373d 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -98,6 +98,7 @@ BEGIN { =20 __current_block_depth =3D 0 __current_block[__current_block_depth] =3D "Root" + __last_sysreg_sort_val =3D 0 } =20 END { @@ -156,6 +157,12 @@ $1 =3D=3D "Sysreg" && block_current() =3D=3D "Root" { crm =3D $6 op2 =3D $7 =20 + sort_val =3D sprintf("%02d", $3) sprintf("%02d", $4) sprintf("%02d", $5) \ + sprintf("%02d", $6) sprintf("%02d", $7) + if (sort_val < __last_sysreg_sort_val) + fatal($2 ": Sysregs should be sorted by encoding") + __last_sysreg_sort_val =3D sort_val + res0 =3D "UL(0)" res1 =3D "UL(0)" unkn =3D "UL(0)" --=20 2.34.1