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X-CSE-ConnectionGUID: uUIOS/pbQnKKbt5ehMoa8A== X-CSE-MsgGUID: 97qeQKJLQzCT07+dLNTyJA== X-IronPort-AV: E=Sophos;i="6.12,316,1728975600"; d="scan'208";a="36185959" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 15 Jan 2025 02:01:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 15 Jan 2025 02:00:38 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 15 Jan 2025 02:00:34 -0700 From: Divya Koppera To: , , , , , , , , , , , , Subject: [PATCH net-next v3 1/3] net: phy: microchip_rds_ptp: Header file library changes for PEROUT Date: Wed, 15 Jan 2025 14:36:32 +0530 Message-ID: <20250115090634.12941-2-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250115090634.12941-1-divya.koppera@microchip.com> References: <20250115090634.12941-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This ptp header file library changes will cover PEROUT macros that are required to generate periodic output from pin out Signed-off-by: Divya Koppera --- v2 -> v3 - Removed redundant macros after modifying code to use nearby pulsewidth value of user input. v1 -> v2 - Removed redundant Macros - Given proper naming to event and pin --- drivers/net/phy/microchip_rds_ptp.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/phy/microchip_rds_ptp.h b/drivers/net/phy/microchi= p_rds_ptp.h index e95c065728b5..25af68337b94 100644 --- a/drivers/net/phy/microchip_rds_ptp.h +++ b/drivers/net/phy/microchip_rds_ptp.h @@ -130,6 +130,23 @@ #define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1 #define MCHP_RDS_PTP_TSU_HARDRESET BIT(0) =20 +#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15 +#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16 +#define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17 +#define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18 + +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19 +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b +#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c + +#define MCHP_RDS_PTP_GEN_CFG 0x01 +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8) + +#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4) +#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0) +#define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1) + /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles in 250MHz. * The value is calculated as following: (1/1000000)/((2^-32)/4) @@ -138,6 +155,10 @@ #define MCHP_RDS_PTP_FIFO_SIZE 8 #define MCHP_RDS_PTP_MAX_ADJ 31249999 =20 +#define MCHP_RDS_PTP_BUFFER_TIME 2 +#define MCHP_RDS_PTP_N_PIN 4 +#define MCHP_RDS_PTP_N_PEROUT 1 + #define BASE_CLK(p) ((p)->clk_base_addr) #define BASE_PORT(p) ((p)->port_base_addr) #define PTP_MMD(p) ((p)->mmd) @@ -176,6 +197,9 @@ struct mchp_rds_ptp_clock { /* Lock for phc */ struct mutex ptp_lock; u8 mmd; + int mchp_rds_ptp_event; + int event_pin; + struct ptp_pin_desc *pin_config; }; =20 struct mchp_rds_ptp_rx_ts { --=20 2.17.1