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Tue, 14 Jan 2025 19:41:46 -0800 (PST) Received: from HOME-PC ([223.185.133.12]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f72c04b157sm325868a91.0.2025.01.14.19.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 19:41:46 -0800 (PST) From: Dheeraj Reddy Jonnalagadda To: anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, piotr.kwapulinski@intel.com Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, michal.swiatkowski@linux.intel.com, intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Dheeraj Reddy Jonnalagadda Subject: [PATCH v2 net-next] ixgbe: Fix endian handling for ACI descriptor registers Date: Wed, 15 Jan 2025 09:11:17 +0530 Message-Id: <20250115034117.172999-1-dheeraj.linuxdev@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ixgbe driver was missing proper endian conversion for ACI descriptor register operations. Add the necessary conversions when reading and writing to the registers. Fixes: 46761fd52a88 ("ixgbe: Add support for E610 FW Admin Command Interfac= e") Closes: https://scan7.scan.coverity.com/#/project-view/52337/11354?selected= Issue=3D1602757 Signed-off-by: Dheeraj Reddy Jonnalagadda Reviewed-by: Michal Swiatkowski Reviewed-by: Piotr Kwapulinski --- Changelog v2: - Updated the patch to include suggested fix - Updated the commit message to describe the issue drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c b/drivers/net/et= hernet/intel/ixgbe/ixgbe_e610.c index 683c668672d6..3b9017e72d0e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c @@ -113,7 +113,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *= hw, =20 /* Descriptor is written to specific registers */ for (i =3D 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) - IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), raw_desc[i]); + IXGBE_WRITE_REG(hw, IXGBE_PF_HIDA(i), cpu_to_le32(raw_desc[i])); =20 /* SW has to set PF_HICR.C bit and clear PF_HICR.SV and * PF_HICR_EV @@ -145,7 +145,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *= hw, if ((hicr & IXGBE_PF_HICR_SV)) { for (i =3D 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { raw_desc[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIDA(i)); - raw_desc[i] =3D raw_desc[i]; + raw_desc[i] =3D le32_to_cpu(raw_desc[i]); } } =20 @@ -153,7 +153,7 @@ static int ixgbe_aci_send_cmd_execute(struct ixgbe_hw *= hw, if ((hicr & IXGBE_PF_HICR_EV) && !(hicr & IXGBE_PF_HICR_C)) { for (i =3D 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) { raw_desc[i] =3D IXGBE_READ_REG(hw, IXGBE_PF_HIDA_2(i)); - raw_desc[i] =3D raw_desc[i]; + raw_desc[i] =3D le32_to_cpu(raw_desc[i]); } } =20 --=20 2.34.1