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Wed, 15 Jan 2025 05:44:06 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:00 +0100 Subject: [PATCH 08/10] arm64: dts: qcom: sm8650: add OPP table support to PCIe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-8-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3609; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=UxJJ2vmOkJivP1vF3mBeCHCgN3ZON8eherWl/ihv3Kw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnh7ue+EB/n83NOVH+e5MD+a2GTuI7GXMZK8MiWxwA kbzviRuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4e7ngAKCRB33NvayMhJ0d6jD/ 4nD4cfnrIs8lSeDJ+79d33odNmnWw3qHlq1crroZk18Gzountj3F/un4s5f/7IBKBQi3+ynTEAAqV4 xxfh6CrtVjKgFALegOsUcRBG29bA80qMWGJNvYd928k50l55Mn1u8p08RaBo9cDYLTPYzU8SZLF9DP 8mk6Z8V7miAzBOP2TpcBo/qvU5s4yLdK5nRHbVYYosGD1gvFMF7zaKsscS/R2y5Ovw9KHXMkjjwYrR koceQ38YLQndaH4g70Mn7PnD/lNFCgbXXWhmbxSCONYGFg59P6BdNswlOGvZxhpSjc++XjfLr9NiZY g6cHp6mO1LpMlk1vRn6/fCG4grJHXuFLLk/ESe7xec4YIMSBUCSY91JD/NJFzgbfrOJLQLxy2Z0kKB ERcMdunb/wnjHDQ2U3GDT2s5fsW6TfuCyi0hafTl17UFHK6vfR2O2Te/GLrOD8iPAzcdEWsPuIwGdO wR7OxzJCWlaqz7piyJz7p1Mr3iwxTVQGFGGLsgQfRF4RmCxNjylGyiEIGdrlI14RkdJW9cPceV4nco Ri+X6ehQqr1hAo3tPX+rEwVZsVzRAaMx5Al+3HUWLAS5IH2PjbxBzi7fAs9NA+TIksCc5S7fQv7u20 crac3QDCnFueaMVnKgwN0pnHSjE+kK25PyRD/VaO+/O7GFavDvoQoIogktHg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe bus interconnect path can be scaled depending on the PCIe link established, add the OPP table with all the possible link speeds and the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 89 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 5982fd4d66d903d638f0eeaaac221f3007abf68b..737d1901ca10fe0a49ae4685d03= 63be74cc0668d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2308,6 +2308,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 + operating-points-v2 =3D <&pcie0_opp_table>; + iommu-map =3D <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; =20 @@ -2338,6 +2340,45 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 status =3D "disabled"; =20 + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + }; + pcieport0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; @@ -2447,6 +2488,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 power-domains =3D <&gcc PCIE_1_GDSC>; =20 + operating-points-v2 =3D <&pcie1_opp_table>; + iommu-map =3D <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; =20 @@ -2477,6 +2520,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 status =3D "disabled"; =20 + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + }; + }; + pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; --=20 2.34.1