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Wed, 15 Jan 2025 05:44:00 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:53 +0100 Subject: [PATCH 01/10] arm64: dts: qcom: sm8550: use ICC tag for all interconnect phandles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-1-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=39955; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=GgqFZVDWjmc89HhqNy2vz4FGoGqqhoGyszp08y7l280=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnh7ubWZkZLYwB/4bkoRejnQqzqB6fxZnhJ6xM+965 Zn6denGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4e7mwAKCRB33NvayMhJ0SJkEA DKb3VIwgDKO1n4GSbLbEAGS8yF6yvw4vVbPgiQB5l5Iq98TtHJOJBn9iAozTl8vWg8ppzNYWxacpjo yscKTBdCBKqL8vorD8fEBiiZsqCjo8VbpNGTk87k+cxwVXjxFlwMjQ78k7NR6Ov2M+wpQGyVgkNe8d smh18iV4FIaLXLoLZadz2rA3t9Q+Q2kvlL5o14FvLqfO9uVENijtq6sEDVLJT8Tu/2YYYiMenGopMa /stxWhC/4NOhDbj4ESMNDhbfd7KYWs8g+pOLldc2dyu/Rwt5t0V3oPA+5XUxEO9tyKOYiUDVIc26X4 aoBAKlip1yoY1GSYFRRqZnBWQDn3djOK8GkGreQDOB4s4Sb337W/j4LRG1cnFLmQnYY74EnP/y65vh uqwESXH5fVPOQbKqe3rXvkTcLr33/KPnGhc3MLIVUvhmvanfGxg2LRKhPLJvMv85zZAi0CE6yooiHj nWsnvFU6Hok36W+Y8ghEdWZDhIzq55kAHcQREA/WcJYzQEglmSEo6mNnr4kYr/tbpIX4NeFO5sYsl/ R3NVXnd9UPUJDJzztn9QQvDqKUuCrxF5Q885UMdTU4W2woWkPUQjRhHjRK8sSS1s/ljBl9cpVthrN0 lm/mqKK7MbF9E/oh7iw7qWrTAPcae9xlTSgHKkS45RBTZSnVLyleY/yDOxsg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Use the proper QCOM_ICC_TAG_ define instead of passing 0 in all interconnect paths phandle third argument. Use QCOM_ICC_TAG_ALWAYS which is the fallback mask if 0 is used as third phandle argument. Signed-off-by: Neil Armstrong Acked-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 387 +++++++++++++++++++++++--------= ---- 1 file changed, 258 insertions(+), 129 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index eac8de4005d82f246bc50f64f09515631d895c99..cc754684bf05b99d39e3987312a= 200b479e8de2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -331,7 +331,8 @@ firmware { scm: scm { compatible =3D "qcom,scm-sm8550", "qcom,scm"; qcom,dload-mode =3D <&tcsr 0x19000>; - interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; }; =20 @@ -850,9 +851,12 @@ i2c8: i2c@880000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; @@ -868,9 +872,12 @@ spi8: spi@880000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; @@ -890,9 +897,12 @@ i2c9: i2c@884000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; @@ -908,9 +918,12 @@ spi9: spi@884000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; @@ -930,9 +943,12 @@ i2c10: i2c@888000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; @@ -948,9 +964,12 @@ spi10: spi@888000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; @@ -970,9 +989,12 @@ i2c11: i2c@88c000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; @@ -988,9 +1010,12 @@ spi11: spi@88c000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; @@ -1010,9 +1035,12 @@ i2c12: i2c@890000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; @@ -1028,9 +1056,12 @@ spi12: spi@890000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; @@ -1050,9 +1081,12 @@ i2c13: i2c@894000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; @@ -1068,9 +1102,12 @@ spi13: spi@894000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; @@ -1088,8 +1125,10 @@ uart14: serial@898000 { pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_uart14_default>, <&qup_uart14_cts_rts>; interrupts =3D ; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1104,9 +1143,12 @@ i2c15: i2c@89c000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; @@ -1122,9 +1164,12 @@ spi15: spi@89c000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; @@ -1156,8 +1201,10 @@ i2c_hub_0: i2c@980000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1173,8 +1220,10 @@ i2c_hub_1: i2c@984000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1190,8 +1239,10 @@ i2c_hub_2: i2c@988000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1207,8 +1258,10 @@ i2c_hub_3: i2c@98c000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1224,8 +1277,10 @@ i2c_hub_4: i2c@990000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1241,8 +1296,10 @@ i2c_hub_5: i2c@994000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1258,8 +1315,10 @@ i2c_hub_6: i2c@998000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1275,8 +1334,10 @@ i2c_hub_7: i2c@99c000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1292,8 +1353,10 @@ i2c_hub_8: i2c@9a0000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1309,8 +1372,10 @@ i2c_hub_9: i2c@9a4000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1347,7 +1412,8 @@ qupv3_id_0: geniqup@ac0000 { clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus =3D <&apps_smmu 0xa3 0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CO= RE_1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core"; dma-coherent; #address-cells =3D <2>; @@ -1364,9 +1430,12 @@ i2c0: i2c@a80000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; @@ -1382,9 +1451,12 @@ spi0: spi@a80000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; @@ -1404,9 +1476,12 @@ i2c1: i2c@a84000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; @@ -1422,9 +1497,12 @@ spi1: spi@a84000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; @@ -1444,9 +1522,12 @@ i2c2: i2c@a88000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; @@ -1462,9 +1543,12 @@ spi2: spi@a88000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; @@ -1484,9 +1568,12 @@ i2c3: i2c@a8c000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; @@ -1502,9 +1589,12 @@ spi3: spi@a8c000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; @@ -1524,9 +1614,12 @@ i2c4: i2c@a90000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; @@ -1542,9 +1635,12 @@ spi4: spi@a90000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; @@ -1562,9 +1658,12 @@ i2c5: i2c@a94000 { pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c5_data_clk>; interrupts =3D ; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; @@ -1582,9 +1681,12 @@ spi5: spi@a94000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; @@ -1602,9 +1704,12 @@ i2c6: i2c@a98000 { pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c6_data_clk>; interrupts =3D ; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; @@ -1622,9 +1727,12 @@ spi6: spi@a98000 { interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; @@ -1643,8 +1751,10 @@ uart7: serial@a9c000 { pinctrl-0 =3D <&qup_uart7_default>; interrupts =3D ; interconnect-names =3D "qup-core", "qup-config"; - interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; status =3D "disabled"; }; }; @@ -1768,8 +1878,10 @@ pcie0: pcie@1c00000 { "ddrss_sf_tbu", "noc_aggr"; =20 - interconnects =3D <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 msi-map =3D <0x0 &gic_its 0x1400 0x1>, @@ -1891,8 +2003,10 @@ pcie1: pcie@1c08000 { assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates =3D <19200000>; =20 - interconnects =3D <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; + interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 msi-map =3D <0x0 &gic_its 0x1480 0x1>, @@ -1969,7 +2083,8 @@ crypto: crypto@1dfa000 { dma-names =3D "rx", "tx"; iommus =3D <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; - interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "memory"; }; =20 @@ -2013,8 +2128,10 @@ ufs_mem_hc: ufshc@1d84000 { dma-coherent; =20 operating-points-v2 =3D <&ufs_opp_table>; - interconnects =3D <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; =20 interconnect-names =3D "ufs-ddr", "cpu-ufs"; clock-names =3D "core_clk", @@ -2314,8 +2431,10 @@ ipa: ipa@3f40000 { clocks =3D <&rpmhcc RPMH_IPA_CLK>; clock-names =3D "core"; =20 - interconnects =3D <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnects =3D <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "memory", "config"; =20 @@ -2349,7 +2468,8 @@ remoteproc_mpss: remoteproc@4080000 { <&rpmhpd RPMHPD_MSS>; power-domain-names =3D "cx", "mss"; =20 - interconnects =3D <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; =20 memory-region =3D <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; =20 @@ -2390,7 +2510,8 @@ remoteproc_adsp: remoteproc@6800000 { <&rpmhpd RPMHPD_LMX>; power-domain-names =3D "lcx", "lmx"; =20 - interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_= EBI1 0>; + interconnects =3D <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWA= YS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; =20 memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; =20 @@ -2848,8 +2969,10 @@ sdhc_2: mmc@8804000 { power-domains =3D <&rpmhpd RPMHPD_CX>; operating-points-v2 =3D <&sdhc2_opp_table>; =20 - interconnects =3D <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; bus-width =3D <4>; dma-coherent; @@ -3020,7 +3143,8 @@ mdss: display-subsystem@ae00000 { =20 power-domains =3D <&dispcc MDSS_GDSC>; =20 - interconnects =3D <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "mdp0-mem"; =20 iommus =3D <&apps_smmu 0x1c00 0x2>; @@ -3493,8 +3617,10 @@ usb_1: usb@a6f8800 { =20 resets =3D <&gcc GCC_USB30_PRIM_BCR>; =20 - interconnects =3D <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "usb-ddr", "apps-usb"; =20 status =3D "disabled"; @@ -4617,7 +4743,8 @@ pmu@24091000 { compatible =3D "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg =3D <0 0x24091000 0 0x1000>; interrupts =3D ; - interconnects =3D <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; =20 operating-points-v2 =3D <&llcc_bwmon_opp_table>; =20 @@ -4666,7 +4793,8 @@ pmu@240b6400 { compatible =3D "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x240b6400 0 0x600>; interrupts =3D ; - interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; =20 operating-points-v2 =3D <&cpu_bwmon_opp_table>; =20 @@ -4750,7 +4878,8 @@ remoteproc_cdsp: remoteproc@32300000 { <&rpmhpd RPMHPD_NSP>; power-domain-names =3D "cx", "mxc", "nsp"; =20 - interconnects =3D <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; =20 memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 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Wed, 15 Jan 2025 05:44:01 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:54 +0100 Subject: [PATCH 02/10] arm64: dts: qcom: sm8550: set CPU interconnect paths as ACTIVE_ONLY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-2-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=27171; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ZI7GQbjgxuGWsEsoRi1Z27Tkxrt9xFBzVoFkKCeDx78=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnh7ubAbsEzXbLR+2LpYMf+o42Dh0J0NUkmyz+ppCu pkrkPb6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4e7mwAKCRB33NvayMhJ0R+hEA DKu8Adg5P5vnAE60mEh5pkWRg4rC271seb/amXEPMaU9yR1KCoVtv92cONGQ6+54fMLRnAjxOirET7 yK1hbyXAQNbvRfIpVo1hoiu1aqXPMhePq642v5+D3sDRPomB0lAj3ccrDMxlb6ZzMBa1AI2JSuK8wY /F53eOD5kjA08kCRfKoYHD91ZshAlABu9f21ZXnCxbJ9XMbqRWeWyvbSspQQHj9rUPYa6WbaoGJO9a XyFmRYygt87dvb5HMCGQOz0l/p0EbYV7eTHyWoLg/pT2+V2rRp5CbygWrFJrVX/xaz9Mmgj2ulTfZS 5DehSemsxGpwdF8hn1n+lDcMIKXQhzw/F2nKXdDfJP+CnVK/Ws+yOezfjwMqByExc0gUgb9XBwjvd5 ZA2dGrbzBAZqTxBPXSl2swLZeOyfJV7oyacgJ1oHBHblVdkLKACI2J+GsktM8QAFEimObZPthlI7Vx 1c9xaVDn8lBsLmDr1uoq8LM/yIuPyrnBiXdFu3dvhsNzlKN6Qx9KJr+90xrlHixl3M5AF/96Ops0AI qQ8UyEp2h/cVNc+YwKt9/hUucB4/xJ9wOGDPtuBB1QAM+H8qm7xpLWcX8scxa2J06j3FRkqCQieM7i p13MzzcBN27htJDafoCUgUe2AvhK4HvQF6iulIOVMXEQaEpshV3scgZg14ig== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if the CPU is online, leaving the firmware disabling the path when the CPUs goes in suspend-idle. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 184 +++++++++++++++++--------------= ---- 1 file changed, 92 insertions(+), 92 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index cc754684bf05b99d39e3987312a200b479e8de2c..a04a405a3f78f34fddf14a26a69= 96148cf60c85f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -853,8 +853,8 @@ i2c8: i2c@880000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -874,8 +874,8 @@ spi8: spi@880000 { pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -899,8 +899,8 @@ i2c9: i2c@884000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -920,8 +920,8 @@ spi9: spi@884000 { pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -945,8 +945,8 @@ i2c10: i2c@888000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -966,8 +966,8 @@ spi10: spi@888000 { pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -991,8 +991,8 @@ i2c11: i2c@88c000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1012,8 +1012,8 @@ spi11: spi@88c000 { pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1037,8 +1037,8 @@ i2c12: i2c@890000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1058,8 +1058,8 @@ spi12: spi@890000 { pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1083,8 +1083,8 @@ i2c13: i2c@894000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1104,8 +1104,8 @@ spi13: spi@894000 { pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1127,8 +1127,8 @@ uart14: serial@898000 { interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1145,8 +1145,8 @@ i2c15: i2c@89c000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1166,8 +1166,8 @@ spi15: spi@89c000 { pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1203,8 +1203,8 @@ i2c_hub_0: i2c@980000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1222,8 +1222,8 @@ i2c_hub_1: i2c@984000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1241,8 +1241,8 @@ i2c_hub_2: i2c@988000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1260,8 +1260,8 @@ i2c_hub_3: i2c@98c000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1279,8 +1279,8 @@ i2c_hub_4: i2c@990000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1298,8 +1298,8 @@ i2c_hub_5: i2c@994000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1317,8 +1317,8 @@ i2c_hub_6: i2c@998000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1336,8 +1336,8 @@ i2c_hub_7: i2c@99c000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1355,8 +1355,8 @@ i2c_hub_8: i2c@9a0000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1374,8 +1374,8 @@ i2c_hub_9: i2c@9a4000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; status =3D "disabled"; }; @@ -1432,8 +1432,8 @@ i2c0: i2c@a80000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1453,8 +1453,8 @@ spi0: spi@a80000 { pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1478,8 +1478,8 @@ i2c1: i2c@a84000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1499,8 +1499,8 @@ spi1: spi@a84000 { pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1524,8 +1524,8 @@ i2c2: i2c@a88000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1545,8 +1545,8 @@ spi2: spi@a88000 { pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1570,8 +1570,8 @@ i2c3: i2c@a8c000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1591,8 +1591,8 @@ spi3: spi@a8c000 { pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1616,8 +1616,8 @@ i2c4: i2c@a90000 { #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1637,8 +1637,8 @@ spi4: spi@a90000 { pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1660,8 +1660,8 @@ i2c5: i2c@a94000 { interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1683,8 +1683,8 @@ spi5: spi@a94000 { pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1706,8 +1706,8 @@ i2c6: i2c@a98000 { interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1729,8 +1729,8 @@ spi6: spi@a98000 { pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; @@ -1753,8 +1753,8 @@ uart7: serial@a9c000 { interconnect-names =3D "qup-core", "qup-config"; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; status =3D "disabled"; }; }; @@ -1880,8 +1880,8 @@ pcie0: pcie@1c00000 { =20 interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 msi-map =3D <0x0 &gic_its 0x1400 0x1>, @@ -2005,8 +2005,8 @@ pcie1: pcie@1c08000 { =20 interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 msi-map =3D <0x0 &gic_its 0x1480 0x1>, @@ -2130,8 +2130,8 @@ ufs_mem_hc: ufshc@1d84000 { operating-points-v2 =3D <&ufs_opp_table>; interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; =20 interconnect-names =3D "ufs-ddr", "cpu-ufs"; clock-names =3D "core_clk", @@ -2433,8 +2433,8 @@ ipa: ipa@3f40000 { =20 interconnects =3D <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "memory", "config"; =20 @@ -2971,8 +2971,8 @@ sdhc_2: mmc@8804000 { =20 interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 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Wed, 15 Jan 2025 05:44:02 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7540ae7sm23454655e9.33.2025.01.15.05.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:44:02 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:55 +0100 Subject: [PATCH 03/10] arm64: dts: qcom: sm8550: add OPP table support to PCIe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-3-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe bus interconnect path can be scaled depending on the PCIe link established, add the OPP table with all the possible link speeds and the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index a04a405a3f78f34fddf14a26a6996148cf60c85f..4b3c51fad9f19a1ec1e5d563a18= fec9633a4e4ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1897,8 +1897,49 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie0_phy>; phy-names =3D "pciephy"; =20 + operating-points-v2 =3D <&pcie0_opp_table>; + status =3D "disabled"; =20 + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + }; + pcieport0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; @@ -2023,8 +2064,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie1_phy>; phy-names =3D "pciephy"; =20 + operating-points-v2 =3D <&pcie1_opp_table>; + status =3D "disabled"; =20 + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; 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Wed, 15 Jan 2025 05:44:03 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7540ae7sm23454655e9.33.2025.01.15.05.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:44:03 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:56 +0100 Subject: [PATCH 04/10] arm64: dts: qcom: sm8550: add QUP serial engines OPP tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-4-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The QUP Serial Engines requires different power domain level depending on their working frequency, add the required OPP table with the level associated with all possible frequencies. For the "I2C Hub" serial engines, sinse they only support a single Operating Point, only add a single power domain level property. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 122 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 4b3c51fad9f19a1ec1e5d563a18fec9633a4e4ae..d02d80d731b9a8746655af6da23= 6307760a8f662 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -348,6 +348,48 @@ mc_virt: interconnect-1 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_125mhz: opp-table-qup125mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + memory@a0000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -861,6 +903,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -882,6 +926,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -907,6 +953,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -928,6 +976,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -953,6 +1003,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -974,6 +1026,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -999,6 +1053,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -1020,6 +1076,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1045,6 +1103,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -1066,6 +1126,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1091,6 +1153,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -1112,6 +1176,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1130,6 +1196,8 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_125mhz>; status =3D "disabled"; }; =20 @@ -1153,6 +1221,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -1174,6 +1244,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1206,6 +1278,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1225,6 +1299,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1244,6 +1320,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1263,6 +1341,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1282,6 +1362,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1301,6 +1383,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1320,6 +1404,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1339,6 +1425,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1358,6 +1446,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; =20 @@ -1377,6 +1467,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; status =3D "disabled"; }; }; @@ -1440,6 +1532,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -1461,6 +1555,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1486,6 +1582,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; status =3D "disabled"; }; =20 @@ -1507,6 +1605,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1532,6 +1632,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -1553,6 +1655,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1578,6 +1682,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -1599,6 +1705,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1624,6 +1732,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; status =3D "disabled"; }; =20 @@ -1645,6 +1755,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1668,6 +1780,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1691,6 +1805,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -1714,6 +1830,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", "rx"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; #address-cells =3D <1>; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Use the proper QCOM_ICC_TAG_ define instead of passing 0 in the IPA interconnect paths phandle third argument Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..0658982a748ef4d9df0fe12ecc6= 8c4c23e3c2566 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2889,8 +2889,10 @@ ipa: ipa@3f40000 { clocks =3D <&rpmhcc RPMH_IPA_CLK>; clock-names =3D "core"; =20 - interconnects =3D <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnects =3D <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; 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Wed, 15 Jan 2025 05:44:04 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:58 +0100 Subject: [PATCH 06/10] arm64: dts: qcom: sm8650: set CPU interconnect paths as ACTIVE_ONLY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-6-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=24175; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=8GGzqyDgRXvGMsBLV5U6mpTGxtZYhoYGyXW1VL17GOc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnh7ud721QAErqoBqpS2UeVPHKRsRUcmsNvTTbhRt9 wvi8Ry6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4e7nQAKCRB33NvayMhJ0cUlEA C/wF9RP+yz1rzErq4y/rtA/BgBtRnZeCczNqW/HTyCVwhBlvYfHvRaZ78pnGwUQ4goiB7nuyJNGeIF pcSq9Lyl9vfdOe+Cpzha2UdoAHeII8SLzXKBjdhswgQvdINvu7DWdOjUCyf5Z17PbrXxLQNR7iUJg8 SLVCAkVI6VL1SoFRsMzKD7AfwZAZ8+ft+5VLTgpN7akIuxurbRWmBL8ESKmavaNcrbw6PlxRKKmQSy qbveMMAQUFywSrJBijF6bqluPPkRc23zsa2P0m/jLhLWAJ5ub4+osIpzAi7vWrmJRsX4UrmcdHfK0z n4g0y/8vppnaNlKSJsf3/z7oafLjZos98/dvoog8kez530wm2HaMjFp/VvImHcY77or4C/iO6ZdiYU Wk4madYRfzsQZMNE9hjykNNmVFuWnfJUPnWsvDewW9JiAZynV/icbfMo9zAsrvh6lX2impCv3VMvi0 1j3ziazpvp7//s4y15hYXGkzHD4xYnCx/iHGAKSnnBJdGMuFkZ6ebWx9p2nSUmINWEP90yI5CtlGe3 jpe6VABWWFApgMSUKNmE9oqcuoq4NHYakUqvT4Ic51vMFQBJU71DJhX46e5EWh8hp4mo2nJzxS9yoj /zexZmdAlrRpjboZwDiahaQBuEG23t7CrFfrjDow9EStH5U/JFJdVjzc2Odw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if the CPU is online, leaving the firmware disabling the path when the CPUs goes in suspend-idle. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++++++++++--------------= ---- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 0658982a748ef4d9df0fe12ecc68c4c23e3c2566..a72087d5255899fba03ac90a3f0= 241ee3905504e 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -881,8 +881,8 @@ i2c8: i2c@880000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -914,8 +914,8 @@ spi8: spi@880000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -947,8 +947,8 @@ i2c9: i2c@884000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -980,8 +980,8 @@ spi9: spi@884000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1013,8 +1013,8 @@ i2c10: i2c@888000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1046,8 +1046,8 @@ spi10: spi@888000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1079,8 +1079,8 @@ i2c11: i2c@88c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1112,8 +1112,8 @@ spi11: spi@88c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1145,8 +1145,8 @@ i2c12: i2c@890000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1178,8 +1178,8 @@ spi12: spi@890000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1211,8 +1211,8 @@ i2c13: i2c@894000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1244,8 +1244,8 @@ spi13: spi@894000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1277,8 +1277,8 @@ uart14: serial@898000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1299,8 +1299,8 @@ uart15: serial@89c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1337,8 +1337,8 @@ i2c_hub_0: i2c@980000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1364,8 +1364,8 @@ i2c_hub_1: i2c@984000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1391,8 +1391,8 @@ i2c_hub_2: i2c@988000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1418,8 +1418,8 @@ i2c_hub_3: i2c@98c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1445,8 +1445,8 @@ i2c_hub_4: i2c@990000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1472,8 +1472,8 @@ i2c_hub_5: i2c@994000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1499,8 +1499,8 @@ i2c_hub_6: i2c@998000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1526,8 +1526,8 @@ i2c_hub_7: i2c@99c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1553,8 +1553,8 @@ i2c_hub_8: i2c@9a0000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1580,8 +1580,8 @@ i2c_hub_9: i2c@9a4000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "qup-core", "qup-config"; =20 @@ -1656,8 +1656,8 @@ i2c0: i2c@a80000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1689,8 +1689,8 @@ spi0: spi@a80000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1722,8 +1722,8 @@ i2c1: i2c@a84000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1755,8 +1755,8 @@ spi1: spi@a84000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1788,8 +1788,8 @@ i2c2: i2c@a88000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1821,8 +1821,8 @@ spi2: spi@a88000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1854,8 +1854,8 @@ i2c3: i2c@a8c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1887,8 +1887,8 @@ spi3: spi@a8c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1920,8 +1920,8 @@ i2c4: i2c@a90000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1953,8 +1953,8 @@ spi4: spi@a90000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -1986,8 +1986,8 @@ i2c5: i2c@a94000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2019,8 +2019,8 @@ spi5: spi@a94000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2052,8 +2052,8 @@ i2c6: i2c@a98000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2085,8 +2085,8 @@ spi6: spi@a98000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2118,8 +2118,8 @@ i2c7: i2c@a9c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2151,8 +2151,8 @@ spi7: spi@a9c000 { =20 interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names =3D "qup-core", @@ -2301,8 +2301,8 @@ pcie0: pcie@1c00000 { =20 interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 @@ -2440,8 +2440,8 @@ pcie1: pcie@1c08000 { =20 interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "pcie-mem", "cpu-pcie"; =20 @@ -2609,8 +2609,8 @@ ufs_mem_hc: ufshc@1d84000 { =20 interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "ufs-ddr", "cpu-ufs"; =20 @@ -2891,8 +2891,8 @@ ipa: ipa@3f40000 { =20 interconnects =3D <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "memory", "config"; =20 @@ -3474,8 +3474,8 @@ sdhc_2: mmc@8804000 { =20 interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; =20 --=20 2.34.1 From nobody Sun Dec 14 21:43:45 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D366A2442E5 for ; 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Wed, 15 Jan 2025 05:44:06 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7540ae7sm23454655e9.33.2025.01.15.05.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:44:05 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:59 +0100 Subject: [PATCH 07/10] arm64: dts: qcom: sm8650: add USB interconnect paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-7-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the interconnect paths for the USB controller. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index a72087d5255899fba03ac90a3f0241ee3905504e..5982fd4d66d903d638f0eeaaac2= 21f3007abf68b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4148,6 +4148,13 @@ usb_1: usb@a6f8800 { =20 resets =3D <&gcc GCC_USB30_PRIM_BCR>; =20 + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + power-domains =3D <&gcc USB30_PRIM_GDSC>; required-opps =3D <&rpmhpd_opp_nom>; =20 --=20 2.34.1 From nobody Sun Dec 14 21:43:45 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DADC4242244 for ; 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Wed, 15 Jan 2025 05:44:06 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-437c7540ae7sm23454655e9.33.2025.01.15.05.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 05:44:06 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:00 +0100 Subject: [PATCH 08/10] arm64: dts: qcom: sm8650: add OPP table support to PCIe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-8-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe bus interconnect path can be scaled depending on the PCIe link established, add the OPP table with all the possible link speeds and the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 89 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 5982fd4d66d903d638f0eeaaac221f3007abf68b..737d1901ca10fe0a49ae4685d03= 63be74cc0668d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2308,6 +2308,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 + operating-points-v2 =3D <&pcie0_opp_table>; + iommu-map =3D <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; =20 @@ -2338,6 +2340,45 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 status =3D "disabled"; =20 + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + }; + pcieport0: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; @@ -2447,6 +2488,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 power-domains =3D <&gcc PCIE_1_GDSC>; =20 + operating-points-v2 =3D <&pcie1_opp_table>; + iommu-map =3D <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; =20 @@ -2477,6 +2520,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 status =3D "disabled"; =20 + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz =3D /bits/ 64 <32000000>; + required-opps =3D <&rpmhpd_opp_nom>; + opp-peak-kBps =3D <3938000 1>; + }; + }; + pcie@0 { device_type =3D "pci"; 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Wed, 15 Jan 2025 05:44:07 -0800 (PST) From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:01 +0100 Subject: [PATCH 09/10] arm64: dts: qcom: sm8650: add QUP serial engines OPP tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-9-eaa8b10e2af7@linaro.org> References: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> In-Reply-To: <20250115-topic-sm8x50-upstream-dt-icc-update-v1-0-eaa8b10e2af7@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15660; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=OKPEX6F08gGO+sg+Hn4Zg0EioH1BaTQhpuoQgCo1/fI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnh7uewyVfACvk7kUBkRivpF6UEfyRHEp824Rvyv4R 74pVfjCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ4e7ngAKCRB33NvayMhJ0XZEEA C87HnZ6EIqwVn16w2yGdgiRLBXGgERrziZ5UFrI1RjlsLtYjOxYXeF0TKIXiViQGm/HPJKxfx7piZk vaef34XaE9EJnMOQ0kFJ9v3RcvvKTVWSjt/PUUqtuJiON7NibXdmtOKvM426ZMV59Jgti7MLlDtIsN +QkEdvEJW58QFz1WKw7+aUMWFPPbxqBCNJv5C6ZaHK+Wj1h9olaVkFSVhh4GPFhRfystgmXRfKnDWa uAofPmycv97YtTtC7lKaF4TmeK/+VMfSkDphtKWZigjtq8H3kOO67HqmzTINNEAc6NBX8ZsJS58BOi KYyLJruGth8NQc4JtISNYrF9d/2mN+v35SmyPbM0k73rAQp0WEaB7WTpuub+fKJJTmTnOkjdSx2nOf +WQmouCuiblxNfwVBkCFCcoURUZZ7sR5xY79FrCbJ3FgRWyviQjUiDU/KV8TmTCAsbCCZln2mgkZ3A FSRTScAUT+jdJvDscaDeZ35vvl6oRO/Puvv48lsJ2XzHaNMZ51gznEfG88s1QyNOzMpIfJpGsKp3x3 tEH2Lv2pj0PoBX3FJvpy2Uy3XgETGfwhNH7eGefa0GToC1cZoFNP93jyxqDmsMldYeq9oCmUY5qLi2 IujDDXmrTFs/xCEuhh9zO3fpa0x0y289kr0MAVKjD8iXcelCvElcM0+rtAHA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The QUP Serial Engines requires different power domain level depending on their working frequency, add the required OPP table with the level associated with all possible frequencies. For the "I2C Hub" serial engines, sinse they only support a single Operating Point, only add a single power domain level property. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 216 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 216 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 737d1901ca10fe0a49ae4685d0363be74cc0668d..82be3f9051705507767023d7e19= 5489852223ce3 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -420,6 +420,62 @@ mc_virt: interconnect-1 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_128mhz: opp-table-qup128mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-128000000 { + opp-hz =3D /bits/ 64 <128000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_240mhz: opp-table-qup240mhz { + compatible =3D "operating-points-v2"; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + memory@a0000000 { device_type =3D "memory"; /* We expect the bootloader to fill in the size */ @@ -889,6 +945,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -922,6 +982,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -955,6 +1019,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -988,6 +1056,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1021,6 +1093,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1054,6 +1130,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1087,6 +1167,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1120,6 +1204,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1153,6 +1241,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1186,6 +1278,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1219,6 +1315,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1252,6 +1352,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1282,6 +1386,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_128mhz>; + pinctrl-0 =3D <&qup_uart14_default>, <&qup_uart14_cts_rts>; pinctrl-names =3D "default"; =20 @@ -1304,6 +1412,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + pinctrl-0 =3D <&qup_uart15_default>; pinctrl-names =3D "default"; =20 @@ -1342,6 +1454,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c0_data_clk>; pinctrl-names =3D "default"; =20 @@ -1369,6 +1485,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c1_data_clk>; pinctrl-names =3D "default"; =20 @@ -1396,6 +1516,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c2_data_clk>; pinctrl-names =3D "default"; =20 @@ -1423,6 +1547,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c3_data_clk>; pinctrl-names =3D "default"; =20 @@ -1450,6 +1578,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c4_data_clk>; pinctrl-names =3D "default"; =20 @@ -1477,6 +1609,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c5_data_clk>; pinctrl-names =3D "default"; =20 @@ -1504,6 +1640,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c6_data_clk>; pinctrl-names =3D "default"; =20 @@ -1531,6 +1671,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c7_data_clk>; pinctrl-names =3D "default"; =20 @@ -1558,6 +1702,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c8_data_clk>; pinctrl-names =3D "default"; =20 @@ -1585,6 +1733,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + pinctrl-0 =3D <&hub_i2c9_data_clk>; pinctrl-names =3D "default"; =20 @@ -1664,6 +1816,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1697,6 +1853,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1730,6 +1890,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1763,6 +1927,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1796,6 +1964,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_240mhz>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1829,6 +2001,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_240mhz>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1862,6 +2038,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1895,6 +2075,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1928,6 +2112,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1961,6 +2149,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1994,6 +2186,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2027,6 +2223,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2060,6 +2260,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2093,6 +2297,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Swich to an OPP table for the UFS frequency scaling instead of the deprecated freq-table-hz property. The Operating Point table will also provide the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 50 ++++++++++++++++++++++++++++++--= ---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 82be3f9051705507767023d7e195489852223ce3..483ae63e6032823e8cc13e8aeb6= db70e3948f02d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2900,14 +2900,6 @@ ufs_mem_hc: ufshc@1d84000 { "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; - freq-table-hz =3D <100000000 403000000>, - <0 0>, - <0 0>, - <100000000 403000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; =20 resets =3D <&gcc GCC_UFS_PHY_BCR>; reset-names =3D "rst"; @@ -2922,6 +2914,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains =3D <&gcc UFS_PHY_GDSC>; required-opps =3D <&rpmhpd_opp_nom>; =20 + operating-points-v2 =3D <&ufs_opp_table>; + iommus =3D <&apps_smmu 0x60 0>; =20 lanes-per-direction =3D <2>; @@ -2933,6 +2927,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, #reset-cells =3D <1>; =20 status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz =3D /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; }; =20 ice: crypto@1d88000 { --=20 2.34.1