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Tue, 14 Jan 2025 15:25:24 -0500 (EST) From: Celeste Liu Date: Wed, 15 Jan 2025 04:24:58 +0800 Subject: [PATCH v5 1/2] riscv/ptrace: add new regset to access original a0 register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250115-riscv-new-regset-v5-1-d0e6ec031a23@coelacanthus.name> References: <20250115-riscv-new-regset-v5-0-d0e6ec031a23@coelacanthus.name> In-Reply-To: <20250115-riscv-new-regset-v5-0-d0e6ec031a23@coelacanthus.name> To: Oleg Nesterov , Paul Walmsley , Palmer Dabbelt , Eric Biederman , Kees Cook , Shuah Khan , Albert Ou Cc: Alexandre Ghiti , "Dmitry V. Levin" , Andrea Bolognani , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , Thomas Gleixner , Ron Economos , Charlie Jenkins , Andrew Jones , Quan Zhou , Felix Yan , Ruizhe Pan , Guo Ren , Yao Zi , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, Celeste Liu , stable@vger.kernel.org, =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3197; i=uwu@coelacanthus.name; h=from:subject:message-id; bh=Bd0I0lIMKMC4KxEOjUIKWSGVerkNEic9IL2ALFZ+R48=; b=owJ4nJvAy8zAJeafov85RWVtBeNptSSG9LYTahxei2+ZK7gL31/p1LKEL+S0u9TWg2pWopNOn ch+9jLbmr2jlIVBjItBVkyRJa+E5SfnpbPdezu2d8HMYWUCGcLAxSkAE1nRz8jQulbWYqJDmdS9 yH0Xd0ZtaImSZtoiOvOPRm3rh46tD2JXMjJMt7t61ztq0xrZnQ+9mjfNvhsjKVJToZO/aUXVeeO /8z/yAADK3kiB X-Developer-Key: i=uwu@coelacanthus.name; a=openpgp; fpr=892EBC7DC392DFF9C9C03F1D15F4180E73787863 The orig_a0 is missing in struct user_regs_struct of riscv, and there is no way to add it without breaking UAPI. (See Link tag below) Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to access original a0 register from userspace via ptrace API. Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API") Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmai= l.com/ Cc: stable@vger.kernel.org Reviewed-by: Bj=C3=B6rn T=C3=B6pel Signed-off-by: Celeste Liu --- arch/riscv/kernel/ptrace.c | 32 ++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 33 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index ea67e9fb7a583683b922fe2c017ea61f3bc848db..ef9ab74c8575a5c440155973b1c= 625c06a867c97 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -31,6 +31,7 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif + REGSET_ORIG_A0, }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -184,6 +185,29 @@ static int tagged_addr_ctrl_set(struct task_struct *ta= rget, } #endif =20 +static int riscv_orig_a0_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + return membuf_store(&to, task_pt_regs(target)->orig_a0); +} + +static int riscv_orig_a0_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + unsigned long orig_a0 =3D task_pt_regs(target)->orig_a0; + int ret; + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1); + if (ret) + return ret; + + task_pt_regs(target)->orig_a0 =3D orig_a0; + return 0; +} + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -224,6 +248,14 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D tagged_addr_ctrl_set, }, #endif + [REGSET_ORIG_A0] =3D { + .core_note_type =3D NT_RISCV_ORIG_A0, + .n =3D 1, + .size =3D sizeof(elf_greg_t), + .align =3D sizeof(elf_greg_t), + .regset_get =3D riscv_orig_a0_get, + .set =3D riscv_orig_a0_set, + }, }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9= fa2142e676c14 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -452,6 +452,7 @@ typedef struct elf64_shdr { #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (= prctl()) */ +#define NT_RISCV_ORIG_A0 0x903 /* RISC-V original a0 register */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --=20 2.48.0