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Mon, 13 Jan 2025 18:20:19 -0800 (PST) From: Yunhui Cui To: ajones@ventanamicro.com, alexghiti@rivosinc.com, andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, cleger@rivosinc.com, conor.dooley@microchip.com, conor@kernel.org, corbet@lwn.net, cuiyunhui@bytedance.com, evan@rivosinc.com, jesse@rivosinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel.holland@sifive.com, shuah@kernel.org Subject: [PATCH v4 1/3] RISC-V: Enable cbo.clean/flush in usermode Date: Tue, 14 Jan 2025 10:19:34 +0800 Message-Id: <20250114021936.17234-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250114021936.17234-1-cuiyunhui@bytedance.com> References: <20250114021936.17234-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enabling cbo.clean and cbo.flush in user mode makes it more convenient to manage the cache state and achieve better performance. Reviewed-by: Andrew Jones Signed-off-by: Yunhui Cui --- arch/riscv/kernel/cpufeature.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..60d180b98f52 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) =20 static bool any_cpu_has_zicboz; +static bool any_cpu_has_zicbom; =20 unsigned long elf_hwcap __read_mostly; =20 @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_i= sa_ext_data *data, pr_err("Zicbom disabled as cbom-block-size present, but is not a power-o= f-2\n"); return -EINVAL; } + + any_cpu_has_zicbom =3D true; return 0; } =20 @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void) current->thread.envcfg |=3D ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n"); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM)) + current->thread.envcfg |=3D ENVCFG_CBCFE; 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Mon, 13 Jan 2025 18:20:26 -0800 (PST) From: Yunhui Cui To: ajones@ventanamicro.com, alexghiti@rivosinc.com, andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, cleger@rivosinc.com, conor.dooley@microchip.com, conor@kernel.org, corbet@lwn.net, cuiyunhui@bytedance.com, evan@rivosinc.com, jesse@rivosinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel.holland@sifive.com, shuah@kernel.org Subject: [PATCH v4 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size Date: Tue, 14 Jan 2025 10:19:35 +0800 Message-Id: <20250114021936.17234-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250114021936.17234-1-cuiyunhui@bytedance.com> References: <20250114021936.17234-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expose Zicbom through hwprobe and also provide a key to extract its respective block size. Signed-off-by: Yunhui Cui --- Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 955fbcd19ce9..0ea7754b2049 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -242,6 +242,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported= , as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar val= ues to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. @@ -281,6 +284,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value descr= ibing the performance of misaligned vector accesses on the selected set of proc= essors. =20 +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicbom block in bytes. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of= misaligned vector accesses is unknown. =20 diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 1ce1df6d0ff3..89379f9a2e6e 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 10 +#define RISCV_HWPROBE_MAX_KEY 11 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 3af142b99f77..b15c0bd83ef2 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -73,6 +73,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) +#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -94,6 +95,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW 2 #define RISCV_HWPROBE_MISALIGNED_VECTOR_FAST 3 #define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4 +#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 11 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index cb93adfffc48..04150e62f998 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -106,6 +106,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCA); 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Mon, 13 Jan 2025 18:20:35 -0800 (PST) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.227]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f217b38sm58948065ad.145.2025.01.13.18.20.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 18:20:35 -0800 (PST) From: Yunhui Cui To: ajones@ventanamicro.com, alexghiti@rivosinc.com, andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, cleger@rivosinc.com, conor.dooley@microchip.com, conor@kernel.org, corbet@lwn.net, cuiyunhui@bytedance.com, evan@rivosinc.com, jesse@rivosinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel.holland@sifive.com, shuah@kernel.org Subject: [PATCH v4 3/3] RISC-V: selftests: Add TEST_ZICBOM into CBO tests Date: Tue, 14 Jan 2025 10:19:36 +0800 Message-Id: <20250114021936.17234-4-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250114021936.17234-1-cuiyunhui@bytedance.com> References: <20250114021936.17234-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add test for Zicbom and its block size into CBO tests, when Zicbom is present, test that cbo.clean/flush may be issued and works. As the software can't verify the clean/flush functions, we just judged that cbo.clean/flush isn't executed illegally. Signed-off-by: Yunhui Cui Reviewed-by: Andrew Jones Reviewed-by: Samuel Holland --- tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 1 file changed, 55 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/se= lftests/riscv/hwprobe/cbo.c index a40541bb7c7d..dec510291ab8 100644 --- a/tools/testing/selftests/riscv/hwprobe/cbo.c +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c @@ -50,6 +50,14 @@ static void cbo_clean(char *base) { cbo_insn(base, 1); } static void cbo_flush(char *base) { cbo_insn(base, 2); } static void cbo_zero(char *base) { cbo_insn(base, 4); } =20 +static void test_no_cbo_inval(void *arg) +{ + ksft_print_msg("Testing cbo.inval instruction remain privileged\n"); + illegal_insn =3D false; + cbo_inval(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.inval\n"); +} + static void test_no_zicbom(void *arg) { ksft_print_msg("Testing Zicbom instructions remain privileged\n"); @@ -61,10 +69,6 @@ static void test_no_zicbom(void *arg) illegal_insn =3D false; cbo_flush(&mem[0]); ksft_test_result(illegal_insn, "No cbo.flush\n"); - - illegal_insn =3D false; - cbo_inval(&mem[0]); - ksft_test_result(illegal_insn, "No cbo.inval\n"); } =20 static void test_no_zicboz(void *arg) @@ -81,6 +85,30 @@ static bool is_power_of_2(__u64 n) return n !=3D 0 && (n & (n - 1)) =3D=3D 0; } =20 +static void test_zicbom(void *arg) +{ + struct riscv_hwprobe pair =3D { + .key =3D RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE, + }; + cpu_set_t *cpus =3D (cpu_set_t *)arg; + __u64 block_size; + long rc; + + rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)cpus, = 0); + block_size =3D pair.value; + ksft_test_result(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_ZICBOM_= BLOCK_SIZE && + is_power_of_2(block_size), "Zicbom block size\n"); + ksft_print_msg("Zicbom block size: %llu\n", block_size); + + illegal_insn =3D false; + cbo_clean(&mem[block_size]); + ksft_test_result(!illegal_insn, "cbo.clean\n"); + + illegal_insn =3D false; + cbo_flush(&mem[block_size]); + ksft_test_result(!illegal_insn, "cbo.flush\n"); +} + static void test_zicboz(void *arg) { struct riscv_hwprobe pair =3D { @@ -129,7 +157,7 @@ static void test_zicboz(void *arg) ksft_test_result_pass("cbo.zero check\n"); } =20 -static void check_no_zicboz_cpus(cpu_set_t *cpus) +static void check_no_zicbo_cpus(cpu_set_t *cpus, __u64 cbo) { struct riscv_hwprobe pair =3D { .key =3D RISCV_HWPROBE_KEY_IMA_EXT_0, @@ -137,6 +165,7 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) cpu_set_t one_cpu; int i =3D 0, c =3D 0; long rc; + char *cbostr; =20 while (i++ < CPU_COUNT(cpus)) { while (!CPU_ISSET(c, cpus)) @@ -148,10 +177,13 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) rc =3D riscv_hwprobe(&pair, 1, sizeof(cpu_set_t), (unsigned long *)&one_= cpu, 0); assert(rc =3D=3D 0 && pair.key =3D=3D RISCV_HWPROBE_KEY_IMA_EXT_0); =20 - if (pair.value & RISCV_HWPROBE_EXT_ZICBOZ) - ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n" - "Use taskset to select a set of harts where Zicboz\n" - "presence (present or not) is consistent for each hart\n"); + cbostr =3D cbo =3D=3D RISCV_HWPROBE_EXT_ZICBOZ ? "Zicboz" : "Zicbom"; + + if (pair.value & cbo) + ksft_exit_fail_msg("%s is only present on a subset of harts.\n" + "Use taskset to select a set of harts where %s\n" + "presence (present or not) is consistent for each hart\n", + cbostr, cbostr); ++c; } } @@ -159,7 +191,9 @@ static void check_no_zicboz_cpus(cpu_set_t *cpus) enum { TEST_ZICBOZ, TEST_NO_ZICBOZ, + TEST_ZICBOM, TEST_NO_ZICBOM, + TEST_NO_ZICBOINVAL, }; =20 static struct test_info { @@ -169,7 +203,9 @@ static struct test_info { } tests[] =3D { [TEST_ZICBOZ] =3D { .nr_tests =3D 3, test_zicboz }, [TEST_NO_ZICBOZ] =3D { .nr_tests =3D 1, test_no_zicboz }, - [TEST_NO_ZICBOM] =3D { .nr_tests =3D 3, test_no_zicbom }, + [TEST_ZICBOM] =3D { .nr_tests =3D 3, test_zicbom }, + [TEST_NO_ZICBOM] =3D { .nr_tests =3D 2, test_no_zicbom }, + [TEST_NO_ZICBOINVAL] =3D { .nr_tests =3D 1, test_no_cbo_inval }, }; =20 int main(int argc, char **argv) @@ -189,6 +225,7 @@ int main(int argc, char **argv) assert(rc =3D=3D 0); tests[TEST_NO_ZICBOZ].enabled =3D true; tests[TEST_NO_ZICBOM].enabled =3D true; + tests[TEST_NO_ZICBOINVAL].enabled =3D true; } =20 rc =3D sched_getaffinity(0, sizeof(cpu_set_t), &cpus); @@ -206,7 +243,14 @@ int main(int argc, char **argv) tests[TEST_ZICBOZ].enabled =3D true; tests[TEST_NO_ZICBOZ].enabled =3D false; } else { - check_no_zicboz_cpus(&cpus); + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOZ); + } + + if (pair.value & RISCV_HWPROBE_EXT_ZICBOM) { + tests[TEST_ZICBOM].enabled =3D true; + tests[TEST_NO_ZICBOM].enabled =3D false; + } else { + check_no_zicbo_cpus(&cpus, RISCV_HWPROBE_EXT_ZICBOM); } =20 for (i =3D 0; i < ARRAY_SIZE(tests); ++i) --=20 2.39.2