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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1064 +++++++++++++++++= ++++ 2 files changed, 1065 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 839432153cc7a..a2fd3a32e351e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -281,6 +281,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk.dtb =20 imx8mm-kontron-dl-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64= /boot/dts/freescale/imx95-15x15-evk.dts new file mode 100644 index 0000000000000..eebfd64141403 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -0,0 +1,1064 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx95.dtsi" + +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 +#define BRD_SM_CTRL_BT_WAKE 0x8002 +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 +#define BRD_SM_CTRL_BUTTON 0x8004 + +/ { + compatible =3D "fsl,imx95-15x15-evk", "fsl,imx95"; + model =3D "NXP i.MX95 15X15 board"; + + aliases { + ethernet0 =3D &enetc_port0; + ethernet1 =3D &enetc_port1; + serial0 =3D &lpuart1; + }; + + bt_sco_codec: bt-sco-codec { + compatible =3D "linux,bt-sco"; + #sound-dai-cells =3D <1>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + stdout-path =3D &lpuart1; + }; + + fan0: pwm-fan { + compatible =3D "pwm-fan"; + #cooling-cells =3D <2>; + cooling-levels =3D <64 128 192 255>; + pwms =3D <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "audio-pwr"; + gpio =3D <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "audio-switch1"; + gpio =3D <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can2-stby"; + gpio =3D <&pcal6524 14 GPIO_ACTIVE_LOW>; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "M.2-power"; + gpio =3D <&pcal6524 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + off-on-delay-us =3D <12000>; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VDD_SD2_3V3"; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "WLAN_EN"; + vin-supply =3D <®_m2_pwr>; + gpio =3D <&pcal6524 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us =3D <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "USB_VBUS"; + gpio =3D <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vcc_12v: regulator-vcc-12v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <12000000>; + regulator-min-microvolt =3D <12000000>; + regulator-name =3D "VCC_12V"; + gpio =3D <&pcal6524 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7F000000>; + reusable; + size =3D <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg =3D <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg =3D <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg =3D <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg =3D <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg =3D <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: vpu_boot@a0000000 { + reg =3D <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-bt-sco { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master =3D <&btcpu>; + simple-audio-card,format =3D "dsp_a"; + simple-audio-card,frame-master =3D <&btcpu>; + simple-audio-card,name =3D "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai =3D <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num =3D <2>; + dai-tdm-slot-width =3D <16>; + sound-dai =3D <&sai1>; + }; + }; + + sound-micfil { + compatible =3D "fsl,imx-audio-card"; + model =3D "micfil-audio"; + + pri-dai-link { + format =3D "i2s"; + link-name =3D "micfil hifi"; + + cpu { + sound-dai =3D <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible =3D "fsl,imx-audio-wm8962"; + audio-codec =3D <&wm8962>; + audio-cpu =3D <&sai3>; + audio-routing =3D "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", + "IN3R", "AMIC", "IN1R", "AMIC"; + hp-det-gpio =3D <&gpio2 21 GPIO_ACTIVE_HIGH>; + model =3D "wm8962-audio"; + pinctrl-0 =3D <&pinctrl_hp>; + pinctrl-names =3D "default"; + }; + + sound-xcvr { + compatible =3D "fsl,imx-audio-card"; + model =3D "imx-audio-xcvr"; + + pri-dai-link { + link-name =3D "XCVR PCM"; + + cpu { + sound-dai =3D <&xcvr>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-0 =3D <&pinctrl_usdhc3_pwrseq>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg =3D <0x0 0x80000000 0 0x80000000>; + device_type =3D "memory"; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&enetc_port0 { + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc0>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&enetc_port1 { + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-0 =3D <&pinctrl_flexcan2>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_can2_stby>; + status =3D "okay"; +}; + +&i3c2 { + pinctrl-0 =3D <&pinctrl_i3c2>; + pinctrl-names =3D "default"; + i2c-scl-hz =3D <400000>; + status =3D "okay"; + + pca9570: gpio@24 { + compatible =3D "nxp,pca9570"; + reg =3D <0x24 0 (I2C_FILTER)>; + + #gpio-cells =3D <2>; + gpio-controller; + gpio-line-names =3D "OUT1", "OUT2", "OUT3", "OUT4"; + }; +}; + +&lpi2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c2>; + pinctrl-names =3D "default"; + status =3D "okay"; + + wm8962: codec@1a { + compatible =3D "wlf,wm8962"; + reg =3D <0x1a>; + clocks =3D <&scmi_clk IMX95_CLK_SAI3>; + AVDD-supply =3D <®_audio_pwr>; + CPVDD-supply =3D <®_audio_pwr>; + DBVDD-supply =3D <®_audio_pwr>; + DCVDD-supply =3D <®_audio_pwr>; + gpio-cfg =3D < + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + >; + MICVDD-supply =3D <®_audio_pwr>; + PLLVDD-supply =3D <®_audio_pwr>; + SPKVDD1-supply =3D <®_audio_pwr>; + SPKVDD2-supply =3D <®_audio_pwr>; + }; + + pcal6524: gpio@22 { + compatible =3D "nxp,pcal6524"; + reg =3D <0x22>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio5>; + pinctrl-0 =3D <&pinctrl_pcal6524>; + pinctrl-names =3D "default"; + }; +}; + +&lpi2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pca9632: led-controller@62 { + compatible =3D "nxp,pca9632"; + reg =3D <0x62>; + #address-cells =3D <1>; + #size-cells =3D <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_BACKLIGHT; + function-enumerator =3D <0>; + }; + + led_backlight1: led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_BACKLIGHT; + function-enumerator =3D <1>; + }; + }; +}; + +&lpi2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c4>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpi2c6 { + clock-frequency =3D <100000>; + pinctrl-0 =3D <&pinctrl_lpi2c6>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpuart1 { + pinctrl-0 =3D <&pinctrl_uart1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpuart5 { + pinctrl-0 =3D <&pinctrl_uart5>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIO= PLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, <393216000>, <361267= 200>, <49152000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_pdm>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mu7 { + status =3D "okay"; +}; + +&netc_blk_ctrl { + status =3D "okay"; +}; + +&netc_emdio { + pinctrl-0 =3D <&pinctrl_emdio>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethphy0: ethernet-phy@1 { + reg =3D <1>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&pcal6524 4 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + + ethphy1: ethernet-phy@2 { + reg =3D <2>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&pcal6524 5 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; +}; + +&netc_timer { + status =3D "okay"; +}; + +&netcmix_blk_ctrl { + status =3D "okay"; +}; + +&pcie0 { + pinctrl-0 =3D <&pinctrl_pcie0>; + pinctrl-names =3D "default"; + reset-gpio =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie-supply =3D <®_m2_pwr>; + status =3D "okay"; +}; + +&netc_bus0 { + msi-map =3D <0x00 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; +}; + +&sai1 { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIO= PLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, <393216000>, <361267= 200>, <12288000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_sai1>; + pinctrl-names =3D "default"; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&sai3 { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIO= PLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, <393216000>, <361267= 200>, <12288000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_sai3>; + pinctrl-names =3D "default"; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins =3D < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins =3D < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins =3D < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x31e + >; + }; + + pinctrl_i3c2: i3c2grp { + fsl,pins =3D < + IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40000186 + IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40000186 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_mipi_dsi_csi: mipidsigrp { + fsl,pins =3D < + IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins =3D < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins =3D < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins =3D < + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins =3D < + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO22__SPDIF_IN 0x3fe + IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x3fe + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins =3D < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO08__TPM6_CH0 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins =3D < + IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids =3D , + , + , + , + ; +}; + +&thermal_zones { + a55-thermal { + cooling-maps { + map1 { + cooling-device =3D <&fan0 0 1>; + trip =3D <&atrip2>; + }; + + map2 { + cooling-device =3D <&fan0 1 2>; + trip =3D <&atrip3>; + }; + + map3 { + cooling-device =3D <&fan0 2 3>; + trip =3D <&atrip4>; + }; + }; + + trips { + atrip2: trip2 { + hysteresis =3D <2000>; + temperature =3D <55000>; + type =3D "active"; + }; + + atrip3: trip3 { + hysteresis =3D <2000>; + temperature =3D <65000>; + type =3D "active"; + }; + + atrip4: trip4 { + hysteresis =3D <2000>; + temperature =3D <75000>; + type =3D "active"; + }; + }; + }; + + pf09-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf09_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device =3D <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip =3D <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5301_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5302_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; +}; + +&tpm3 { + pinctrl-0 =3D <&pinctrl_tpm3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&tpm6 { + pinctrl-0 =3D <&pinctrl_tpm6>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usdhc1 { + bus-width =3D <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc1>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step =3D <1>; + status =3D "okay"; +}; + +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc2_vmmc>; + fsl,cd-gpio-wakeup-disable; + fsl,tuning-step =3D <1>; + status =3D "okay"; +}; + +&usdhc3 { + bus-width =3D <4>; + keep-power-in-suspend; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc3>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc3_vmmc>; + wakeup-source; + status =3D "okay"; +}; + +&wdog3 { + status =3D "okay"; +}; + +&xcvr { + clocks =3D <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&dummy>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names =3D "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates =3D <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>, <0>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_spdif>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.34.1