From nobody Tue Mar 4 22:19:54 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C2F4227BBA for ; Tue, 14 Jan 2025 22:58:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736895533; cv=none; b=HNyxELZlHqLItfsipQUPMpe7vqp/V/5p8IJJ+1uCmyeOFrT1CJ+dGH2Aznr84Z2pf+l6AfW11jF/NZYvld1sBsK6RL1MFnAM300YrhH5LdRM0otjzSMTpaqXELGVDjj27pmcucs5qh2l0FmxZxlqUlhFlH9GGlqb2uOG0stx2s0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736895533; c=relaxed/simple; bh=KX+c6OZLcoeS98RkAUKLotKTlJrHqY7en1pLAwLRhK8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lhqAZkwoReDTdKN/EeAiiN9tFE8kZshHJQEUsmWjtfSUmOL9OjIpyYshCdaSJDT059CSHRR4Rlww7XP2BMwmNSgNTxQX9K5NfqPtnfqljDLJBbb+2BecwZ5qx9MgZfooYNj94LiozTH7DmMqyPi03imhyAGs/QVNa8xbIBlbGQI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=mRpHszRX; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="mRpHszRX" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-2164b662090so105213975ad.1 for ; Tue, 14 Jan 2025 14:58:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1736895530; x=1737500330; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qntZYbhhaPOyc0opQ/xzbCXT2UPDrjgDrjtXnzGv1Lc=; b=mRpHszRX6ik/dBvFnqOgfexdZuIsP3u9Y4NIjN1p5e8ujRPU59C/lNHIgHqxrP+eA+ jIU9a7ITmY46zrhBLYlYqhYKWYD/pjktFnLHFjpx3GGDK+vuLsAvOIUdyUIQNQtmKDqb IiAZDKi6gZiemqdf+cOk8DB8Fyl53wov3wkzwECVnIJPsrSfllEdV0XIKeLNcO52B/hn T/gV1o6ElybcHx9U1KWDpbPkUoxLora92bCoC3mfalgFqGCx0UFLbIETkmtjF7KO7+UF bG9084XOX1dAJwElF/ZBhg5guNP5em/sgu5tnnhGRaAS41ldsh6zD3v3DdkLX9d4C8KG SWYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736895530; x=1737500330; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qntZYbhhaPOyc0opQ/xzbCXT2UPDrjgDrjtXnzGv1Lc=; b=NW2r4JUyC9UzJVjOznPZr78tiZ5ONWwo60fHEolkc5wxMBhDZiCTGsde6YtF4KS9LL hPzOyAEpMssZSqqOUt65cLbonIONA1am3TluOPbWjwXx2QSpeCQ7/ZKp/C2pe5LeRzQy IZMeH0lNCQEH7j1/kYOYiJQZ9syrSHxYS9vvrZOBhhEgEgjduY2cM/I8p6wYsk48LipS jLmg3NezQwoVO5ozXB8AKZapVY1SicNkAkzxHbEE2HwHcSu9IYS3r7XBZgbRbwim1gKm JIjHKklrnzCW5UG9P4VTFdoAt1bRSq2IeRaw8PdhI8SzKgyIh9ieO17/eCAaUnPJvEbR FW9Q== X-Forwarded-Encrypted: i=1; AJvYcCVvFHbzEw2Gb2v9DRDk3JCES2yiVTQzlXqBkZtbbqO46k8l71b4qAtXmBpsUeHLsYVic8/gAtH5MPFUsDk=@vger.kernel.org X-Gm-Message-State: AOJu0Yy+Q4sOB3wHg8pP6KVM8muBPk4sWJiGK7FemAPJHY2q9g0lI3j+ bpx8HWwLfW9OCz8jrnFs+ymjeOKlIyazImvYcWKC47v0AAMAnINWJDii1iNTnd0= X-Gm-Gg: ASbGncuRfZPwkCYzjlG12jS3kaNe+rwKBTSbKoAa+l2gXLrsAhW5ofVBGp92ew6yo5f Yf5lU6WgMT5UlaJ+zLzfX2c/Z8qB1Xl+Gir0z1y//kcsol5rfaQ6qC/YhWIGl8oW4yZa2mbvUVz TrMcwJiz4f91uUC9nwzeCUsqccRQ+Oiwhdp3a9/91dWMgzGzWe/gxT5FLen6qjw7b9Asa6WTE85 Llwb82gy44JTFJv30gc6nk6QB5LiA/V0Qxbmf6O507KYXupWrcpD+movePeGS+D5vrYuA== X-Google-Smtp-Source: AGHT+IGvBxZa4fPYf8i5v/l3b33jLbUOvTwVMUDT5oDU8+c/I1Eb7QvrJXcdFBnuK94wX8xRhTTgmw== X-Received: by 2002:a17:902:ecc5:b0:216:45eb:5e4d with SMTP id d9443c01a7336-21a83f4b29dmr369677175ad.6.1736895529901; Tue, 14 Jan 2025 14:58:49 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f10df7asm71746105ad.47.2025.01.14.14.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2025 14:58:49 -0800 (PST) From: Atish Patra Date: Tue, 14 Jan 2025 14:57:43 -0800 Subject: [PATCH v2 18/21] RISC-V: perf: Add Qemu virt machine events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250114-counter_delegation-v2-18-8ba74cdb851b@rivosinc.com> References: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> In-Reply-To: <20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Signed-off-by: Atish Patra --- arch/riscv/include/asm/vendorid_list.h | 4 ++++ drivers/perf/riscv_pmu_dev.c | 36 ++++++++++++++++++++++++++++++= ++++ 2 files changed, 40 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index 2f2bb0c84f9a..ef22b03552bc 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,4 +9,8 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 +#define QEMU_VIRT_VENDOR_ID 0x000 +#define QEMU_VIRT_IMPL_ID 0x000 +#define QEMU_VIRT_ARCH_ID 0x000 + #endif diff --git a/drivers/perf/riscv_pmu_dev.c b/drivers/perf/riscv_pmu_dev.c index 8c5598253af0..d28d60abaaf2 100644 --- a/drivers/perf/riscv_pmu_dev.c +++ b/drivers/perf/riscv_pmu_dev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -384,7 +385,42 @@ struct riscv_vendor_pmu_events { .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map,= \ .attrs_events =3D _attrs }, =20 +/* QEMU virt PMU events */ +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_M= AX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D {0x01, 0xFFFFFFF8}, + [PERF_COUNT_HW_INSTRUCTIONS] =3D {0x02, 0xFFFFFFF8} +}; + +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_H= W_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10019, 0xFFFFFFF8}, + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] =3D {0x1001B, 0xFFFFFFF8}, + + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10021, 0xFFFFFFF8}, +}; + +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFF= F8); +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFF= FFF8); +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFF= F8); + +static struct attribute *qemu_virt_event_group[] =3D { + RVPMU_EVENT_ATTR_PTR(cycles), + RVPMU_EVENT_ATTR_PTR(instructions), + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + NULL, +}; + static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT= _IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) }; =20 const struct riscv_pmu_event *current_pmu_hw_event_map; --=20 2.34.1