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[93.34.91.161]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436e9dd1de9sm156091075e9.15.2025.01.13.15.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 15:10:57 -0800 (PST) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com Cc: Christian Marangi Subject: [PATCH v6 1/4] clk: en7523: Rework clock handling for different clock numbers Date: Tue, 14 Jan 2025 00:10:02 +0100 Message-ID: <20250113231030.6735-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250113231030.6735-1-ansuelsmth@gmail.com> References: <20250113231030.6735-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Airoha EN7581 SoC have additional clock compared to EN7523 but current driver permits to only support up to EN7523 clock numbers. To handle this, rework the clock handling and permit to declare the clocks number in match_data and alloca clk_data based on the compatible match_data. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 495c0d607c7d..3a4b7ed40af4 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -75,6 +75,7 @@ struct en_rst_data { }; =20 struct en_clk_soc_data { + u32 num_clocks; const struct clk_ops pcie_ops; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); @@ -504,8 +505,6 @@ static void en7523_register_clocks(struct device *dev, = struct clk_hw_onecell_dat u32 rate; int i; =20 - clk_data->num =3D EN7523_NUM_CLOCKS; - for (i =3D 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc =3D &en7523_base_clks[i]; u32 reg =3D desc->div_reg ? desc->div_reg : desc->base_reg; @@ -587,8 +586,6 @@ static void en7581_register_clocks(struct device *dev, = struct clk_hw_onecell_dat =20 hw =3D en7523_register_pcie_clk(dev, base); clk_data->hws[EN7523_CLK_PCIE] =3D hw; - - clk_data->num =3D EN7523_NUM_CLOCKS; } =20 static int en7523_reset_update(struct reset_controller_dev *rcdev, @@ -702,13 +699,15 @@ static int en7523_clk_probe(struct platform_device *p= dev) struct clk_hw_onecell_data *clk_data; int r; =20 + soc_data =3D device_get_match_data(&pdev->dev); + clk_data =3D devm_kzalloc(&pdev->dev, - struct_size(clk_data, hws, EN7523_NUM_CLOCKS), + struct_size(clk_data, hws, soc_data->num_clocks), GFP_KERNEL); if (!clk_data) return -ENOMEM; =20 - soc_data =3D device_get_match_data(&pdev->dev); + clk_data->num =3D soc_data->num_clocks; r =3D soc_data->hw_init(pdev, clk_data); if (r) return r; @@ -717,6 +716,7 @@ static int en7523_clk_probe(struct platform_device *pde= v) } =20 static const struct en_clk_soc_data en7523_data =3D { + .num_clocks =3D ARRAY_SIZE(en7523_base_clks) + 1, .pcie_ops =3D { .is_enabled =3D en7523_pci_is_enabled, .prepare =3D en7523_pci_prepare, @@ -726,6 +726,8 @@ static const struct en_clk_soc_data en7523_data =3D { }; =20 static const struct en_clk_soc_data en7581_data =3D { + /* We increment num_clocks by 1 to account for additional PCIe clock */ + .num_clocks =3D ARRAY_SIZE(en7581_base_clks) + 1, .pcie_ops =3D { .is_enabled =3D en7581_pci_is_enabled, .enable =3D en7581_pci_enable, --=20 2.45.2