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Mon, 13 Jan 2025 07:09:46 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 1/5] irqchip/riscv-intc: Balance priority and fairness during irq handling Date: Mon, 13 Jan 2025 23:09:29 +0800 Message-Id: <20250113150933.65121-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both csr cause and csr topi record the pending bit with the highest priority. If interrupts with high priority arrive frequently within a certain period of time, the interrupts with low priority won't get a chance to be handled. For example, if external interrupts and software interrupts arrive very frequently, the timer interrupts will never be handled. Then buddy watchdog on a buddy CPU will report a hardlockup on the current CPU while current CPU actually can receive irq. This commit solves this problem by handling all pending irqs in a round. During each round, this commit handles pending irqs by their priority. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-intc.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index f653c13de62b..bc2ec26aa9e9 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,40 @@ static unsigned int riscv_intc_nr_irqs __ro_after_init = =3D BITS_PER_LONG; static unsigned int riscv_intc_custom_base __ro_after_init =3D BITS_PER_LO= NG; static unsigned int riscv_intc_custom_nr_irqs __ro_after_init; =20 +static unsigned int riscv_prio_irqs[] =3D { +#ifdef CONFIG_RISCV_M_MODE + IRQ_M_EXT, IRQ_M_SOFT, IRQ_M_TIMER, +#endif + IRQ_S_EXT, IRQ_S_SOFT, IRQ_S_TIMER, IRQ_S_GEXT, + IRQ_VS_EXT, IRQ_VS_SOFT, IRQ_VS_TIMER, + IRQ_PMU_OVF, +}; + static void riscv_intc_irq(struct pt_regs *regs) { - unsigned long cause =3D regs->cause & ~CAUSE_IRQ_FLAG; - - if (generic_handle_domain_irq(intc_domain, cause)) - pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause); 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Mon, 13 Jan 2025 07:09:50 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:09:50 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 2/5] irqchip/riscv-imsic: Add a threshold to ext irq handling times Date: Mon, 13 Jan 2025 23:09:30 +0800 Message-Id: <20250113150933.65121-3-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V's external irq has higher priority than software irq, timer irq and pmu overflow irq. In existing implementation of IMSIC driver, If external irqs keep arriving within a certain period of time, no other interrupt will get a chance to be handled. This commit solves this problem by introducing a threshold to the number of times imsic interrupts can be processed in each round. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-early.c | 31 ++++++++++++++----------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index c5c2e6929a2f..63097f2bbadf 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -20,6 +20,8 @@ =20 #include "irq-riscv-imsic-state.h" =20 +#define IMSIC_HANDLE_THRESHOLD 20 + static int imsic_parent_irq; =20 #ifdef CONFIG_SMP @@ -76,6 +78,7 @@ static void imsic_handle_irq(struct irq_desc *desc) int err, cpu =3D smp_processor_id(); struct imsic_vector *vec; unsigned long local_id; + unsigned int handled =3D 0; =20 chained_irq_enter(chip, desc); =20 @@ -85,21 +88,23 @@ static void imsic_handle_irq(struct irq_desc *desc) if (local_id =3D=3D IMSIC_IPI_ID) { if (IS_ENABLED(CONFIG_SMP)) ipi_mux_process(); - continue; - } - - if (unlikely(!imsic->base_domain)) - continue; - - vec =3D imsic_vector_from_local_id(cpu, local_id); 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charset="utf-8" During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as IMSIC issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-early.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-= riscv-imsic-early.c index 63097f2bbadf..c6317cb557fb 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -29,6 +29,12 @@ static void imsic_ipi_send(unsigned int cpu) { struct imsic_local_config *local =3D per_cpu_ptr(imsic->global.local, cpu= ); =20 + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel_relaxed(IMSIC_IPI_ID, local->msi_va); } =20 --=20 2.20.1 From nobody Thu Dec 18 09:59:19 2025 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0C6E233539 for ; Mon, 13 Jan 2025 15:09:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 13 Jan 2025 07:09:58 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:09:58 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 4/5] irqchip/timer-clint: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:32 +0800 Message-Id: <20250113150933.65121-5-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as CLINT issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/clocksource/timer-clint.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-= clint.c index 0bdd9d7ec545..8d73b45f9966 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -48,6 +48,12 @@ EXPORT_SYMBOL(clint_time_val); #ifdef CONFIG_SMP static void clint_send_ipi(unsigned int cpu) { + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); } =20 --=20 2.20.1 From nobody Thu Dec 18 09:59:19 2025 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C341223354B for ; Mon, 13 Jan 2025 15:10:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.42 ARC-Seal: i=1; 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Mon, 13 Jan 2025 07:10:03 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:10:02 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 5/5] irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:33 +0800 Message-Id: <20250113150933.65121-6-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as ACLINT SSWI issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/irqchip/irq-thead-c900-aclint-sswi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip= /irq-thead-c900-aclint-sswi.c index b0e366ade427..7246a008a0f0 100644 --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c @@ -31,6 +31,12 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); =20 static void thead_aclint_sswi_ipi_send(unsigned int cpu) { + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); } =20 --=20 2.20.1