From nobody Thu Dec 18 20:41:36 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 457B61FBBDB; Mon, 13 Jan 2025 14:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736779967; cv=none; b=AGckBCM6Rsnf4g/xnRZgbzI8cI7MpyTYPUvhv5BjMl062v2F+La5ybFWuxZzfO8LRsrHuvS8Ev9i57I0c3UMsbtDYd0hb9qxLJ3Iz3MiMzgN6kKkLuEiCihPIeDVMmlaeTmuz8bdrl6s303wWNqY+IQ7SqbnY2/mSYd4qQHBQBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736779967; c=relaxed/simple; bh=mTyo19wid9FYefXlygiKggLItgPYMiXGJtMBBZA5C2U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BG2BbYVpupcVoAy6f/3TT4BS5ymZpfXDxkOWoctJd0eoYGoFRp7I/uJ16kHoRuc0RXnXH0nR5c3/jc7+uZWx2FbG0iE3C4Lot/iziMuF0FYJADZt2y8A5LFG8UHNoMT+tkDlLxu9Qfv8VZCGT3GjyQwSpf8xtdTHN2UXkfbGvKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nG+39xsG; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nG+39xsG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1736779963; bh=mTyo19wid9FYefXlygiKggLItgPYMiXGJtMBBZA5C2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nG+39xsG/M/xNyhz5JlWViveXrF2MeM4clecRMFBOnCKNFhDg/gg2nBSnzLPUDca1 A+l4xBS0qlPgYcR6alnChp3yDoE2SaXgsV1Bxd6vvpPdsE6UTN2yhSZ0q3iHEHc+QR w47Af7KoCn/2y+mw8MMZAGDhB4D0P9YuxeLHPV5L1v9iN7vYhlFiwmoGQy8T2czoxh P1MAniFvqr/QumKEmOu37eqkpkWvc4xH0ZHLnNLpnCsIh4CWyj1P8U6uIrGTiJ6SB7 6MrEaJoXB/Gqf9IbpNocDKimFO0stE4Le5F7aZQIU/uQH07htJLCW0e1Z1UU7rSLUx WpOZ1TPKuuH6Q== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3E91B17E0F70; Mon, 13 Jan 2025 15:52:42 +0100 (CET) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ck.hu@mediatek.com, jitao.shi@mediatek.com, jie.qiu@mediatek.com, junzhi.zhao@mediatek.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, dmitry.baryshkov@linaro.org, lewis.liao@mediatek.com, ives.chenjh@mediatek.com, tommyyl.chen@mediatek.com, jason-jh.lin@mediatek.com Subject: [PATCH v5 04/34] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function Date: Mon, 13 Jan 2025 15:52:02 +0100 Message-ID: <20250113145232.227674-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250113145232.227674-1-angelogioacchino.delregno@collabora.com> References: <20250113145232.227674-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for the DPI IP found in MT8195 and in MT8188 used for HDMI, move the code flow for calculation and setting of the DPI pixel clock to a separate function called mtk_dpi_set_pixel_clk(). This was done because, on those platforms, the DPI instance that is used for HDMI will get its pixel clock from the HDMI clock, hence it is not necessary, nor desirable, to calculate or set the pixel clock in DPI. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 41fdc193891a..59c2e4f32a61 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -537,26 +537,17 @@ static unsigned int mtk_dpi_calculate_factor(struct m= tk_dpi *dpi, int mode_clk) return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; } =20 -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, - struct drm_display_mode *mode) +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *v= m, int mode_clk) { - struct mtk_dpi_polarities dpi_pol; - struct mtk_dpi_sync_param hsync; - struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_leven =3D { 0 }; - struct mtk_dpi_sync_param vsync_rodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_reven =3D { 0 }; - struct videomode vm =3D { 0 }; unsigned long pll_rate; unsigned int factor; =20 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ factor =3D mtk_dpi_calculate_factor(dpi, mode_clk); - drm_display_mode_to_videomode(mode, &vm); - pll_rate =3D vm.pixelclock * factor; + pll_rate =3D vm->pixelclock * factor; =20 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); =20 clk_set_rate(dpi->tvd_clk, pll_rate); pll_rate =3D clk_get_rate(dpi->tvd_clk); @@ -566,20 +557,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, * pixels for each iteration: divide the clock by this number and * adjust the display porches accordingly. */ - vm.pixelclock =3D pll_rate / factor; - vm.pixelclock /=3D dpi->conf->pixels_per_iter; + vm->pixelclock =3D pll_rate / factor; + vm->pixelclock /=3D dpi->conf->pixels_per_iter; =20 if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); else - clk_set_rate(dpi->pixel_clk, vm.pixelclock); + clk_set_rate(dpi->pixel_clk, vm->pixelclock); =20 - - vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); + vm->pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); +} + +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, + struct drm_display_mode *mode) +{ + struct mtk_dpi_polarities dpi_pol; + struct mtk_dpi_sync_param hsync; + struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; + struct mtk_dpi_sync_param vsync_leven =3D { 0 }; + struct mtk_dpi_sync_param vsync_rodd =3D { 0 }; + struct mtk_dpi_sync_param vsync_reven =3D { 0 }; + struct videomode vm =3D { 0 }; + + drm_display_mode_to_videomode(mode, &vm); + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); =20 dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; --=20 2.47.0