From nobody Sat Feb 7 05:49:09 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCA01148FF2 for ; Sun, 12 Jan 2025 07:49:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736668165; cv=none; b=hsIs84zthSLYFgGAgv4JFLuwN2Af8tm5lpeLOj7CB3IL7uk6RgLMnXCMTf9uhtjfrx6F22A07X27+Db4HljiWzS7hLF/gFe4Enup+yP6veVSsVSJ5O5lezZZIq7FWmh3y61IfgTTxv5+sRTiGsTpdDpks3dTLEPSJl1trUskVNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736668165; c=relaxed/simple; bh=cNi9vhf9bGsIwHgm7dOKJB7hausRE69NcKHC5yezuYw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=MHtmiOJ6lVFEs2NVHCoGUa9LcyxSDRtsAknE+KR4SHqOpODkXCLsnMOMySmymm3DubcqvL4YxuYiE2KSszbu61WAwcMoqaYjxryvPaFq9cqlBsKrlldPCCVFuS6KdNuWoH8/xE65jNatiWr3LPDBGJmFaXVqwZQ+fiMPW8TAW5w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AIB/v9P4; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AIB/v9P4" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-2161eb95317so56415735ad.1 for ; Sat, 11 Jan 2025 23:49:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1736668163; x=1737272963; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=gcU6OrSCKgDwFj8OIVqMhgOivSwgFqlZg2dJEdDSXwc=; b=AIB/v9P4ZxEJPmQDxfeIRlH1VE5CiMHW2GFubBPmSdjDcXv7gTsofI5dmoXIVz82hT Tw10/FooFgxdY1Q+b/+8d3ytNdZesuMUjOgVpG6P/O+vV1K6Fsi8DWQ8GWax1q3Fj6de YNMX2tUSzUYJCPfkzRJO1OLYV7tLGleNcxZPTRVPx7wzw4aQwqUbUK4yUnkbMuZWCxCn hsoZmLAZpVM4E+EnAY1xhH2fCl/sRnpkra5WxigNiAoZis0xagSzsI1Q4guIIcko6uga cirUkbq/3CKnKtgFDUDE3MfdbG1EJylXstPDJKFesOm7jtEn0i+TZZgxYyZr9ry5gR3h /ILA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736668163; x=1737272963; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gcU6OrSCKgDwFj8OIVqMhgOivSwgFqlZg2dJEdDSXwc=; b=ogtBOYdAEXbyhgbJVQqFZVnL9jsivzJSe9/H6BAsP7O8sOO1CawMZQgp9yKYztTm9Z HNaBAAUeoLnaCKd4pQdszdliHEddYMbl3RbM3Gf/3vKZxBqH42VJMzwUNv0uvbtmPgFJ LEGJMPybwzTO+68n9F8vGk3tVULCKcf+bn1U1mUFnidK10PTexEg+T6FEgMAQfK8/8vQ Mvr9BDC+hlP/hi1wX07KnK+JlL9rPlEq9zsjA8C6IuxdoI+OrIyoHuF+yy4JdHTE81so VcfGKu2Rsl6IgTy+TJPze0TWMojTGNQDOoAGbAv9elutdO1rw8UVEC5T/Cd4Z6Z+bNK9 2z9g== X-Forwarded-Encrypted: i=1; AJvYcCU/m0I/W08oSeRndPcSMhHz8EDUPbCmp+CKWS8APQnSyfaGdA8/qcKBX6WDK3+hfJ1qPkyrv/qRKuc/dLY=@vger.kernel.org X-Gm-Message-State: AOJu0YwlyMcvrTFlc9akaHQVP1zqGKOwfojN4cc4vqBmV7AxLD5Eg1EC uBVdtwWN093rZcMCXAfxYqSt8CLg8DhEJEnWahwq6lHukWlW1fqV X-Gm-Gg: ASbGncsE0FTI4Ylg9FnAsUAWdJNYM6TURQ/HHZMMEVqCvC/smdyKT5XyVYaD5Jg/vHV tvBx7kmpXnbtlapFqWcJuRU3+G3uizcNh2+2Z7XY/fWLbpy1BxX0VjIhpH6gKH+jmA0jljhKlj7 SbhqcDuzNu95N6I0Vg9FWOeNFDdfa39/SQXYh5ED6VsRCFQs5T+9iPpX4OD4JmIFQyRMpROk9W5 1Q7XKDrtboQP6ktTyef5JvVWZwfO04MLok6FJiEoD9xbuhMdoKH0Kx1X2wIb+p6n/62/dY= X-Google-Smtp-Source: AGHT+IFiHOZe64qhLb/veCLSRYGclr19x6jZ3sYxwuFoZpr0eA5JOkfIF30+U6Ck+eUHZBNY5AX52Q== X-Received: by 2002:a05:6a20:841b:b0:1e1:ae9a:6316 with SMTP id adf61e73a8af0-1e88d09cbbbmr32490659637.35.1736668162964; Sat, 11 Jan 2025 23:49:22 -0800 (PST) Received: from tiger.hygon.cn ([112.64.138.194]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72d4054947csm3867812b3a.29.2025.01.11.23.49.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jan 2025 23:49:22 -0800 (PST) From: Wencheng Yang To: Cc: Wencheng Yang , Joerg Roedel , Suravee Suthikulpanit , Will Deacon , Robin Murphy , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] drviers/iommu/amd: support P2P access through IOMMU when SME is enabled Date: Sun, 12 Jan 2025 15:45:35 +0800 Message-ID: <20250112074539.381848-1-east.moutain.yang@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When SME is enabled, SME bit is set in IOMMU page table pte entry, it works fine if the pfn of the pte entry is memory. However, if the pfn is MMIO address, for example, map other device's mmio space to its io page table, in such situation, setting SME bit in pte would cause P2P failure. Clear SME bit in io page table if the mapping is MMIO rather than memory. Signed-off-by: Wencheng Yang --- drivers/iommu/amd/amd_iommu_types.h | 7 ++++--- drivers/iommu/amd/io_pgtable.c | 2 ++ drivers/iommu/amd/io_pgtable_v2.c | 5 ++++- drivers/iommu/amd/iommu.c | 2 ++ 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index fdb0357e0bb9..b0f055200cf3 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -434,9 +434,10 @@ #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) =20 -#define IOMMU_PROT_MASK 0x03 -#define IOMMU_PROT_IR 0x01 -#define IOMMU_PROT_IW 0x02 +#define IOMMU_PROT_MASK 0x07 +#define IOMMU_PROT_IR 0x01 +#define IOMMU_PROT_IW 0x02 +#define IOMMU_PROT_MMIO 0x04 =20 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) =20 diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index f3399087859f..dff887958a56 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -373,6 +373,8 @@ static int iommu_v1_map_pages(struct io_pgtable_ops *op= s, unsigned long iova, __pte |=3D IOMMU_PTE_IR; if (prot & IOMMU_PROT_IW) __pte |=3D IOMMU_PTE_IW; + if (prot & IOMMU_PROT_MMIO) + __pte =3D __sme_clr(__pte); =20 for (i =3D 0; i < count; ++i) pte[i] =3D __pte; diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtab= le_v2.c index c616de2c5926..55f969727dea 100644 --- a/drivers/iommu/amd/io_pgtable_v2.c +++ b/drivers/iommu/amd/io_pgtable_v2.c @@ -65,7 +65,10 @@ static u64 set_pte_attr(u64 paddr, u64 pg_size, int prot) { u64 pte; =20 - pte =3D __sme_set(paddr & PM_ADDR_MASK); + pte =3D paddr & PM_ADDR_MASK; + if (!(prot & IOMMU_PROT_MMIO)) + pte =3D __sme_set(pte); + pte |=3D IOMMU_PAGE_PRESENT | IOMMU_PAGE_USER; pte |=3D IOMMU_PAGE_ACCESS | IOMMU_PAGE_DIRTY; =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 16f40b8000d7..9194ad681504 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2578,6 +2578,8 @@ static int amd_iommu_map_pages(struct iommu_domain *d= om, unsigned long iova, prot |=3D IOMMU_PROT_IR; if (iommu_prot & IOMMU_WRITE) prot |=3D IOMMU_PROT_IW; + if (iommu_prot & IOMMU_MMIO) + prot |=3D IOMMU_PROT_MMIO; =20 if (ops->map_pages) { ret =3D ops->map_pages(ops, iova, paddr, pgsize, --=20 2.43.0