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Fri, 10 Jan 2025 16:47:05 -0800 (PST) From: Samuel Holland To: Anup Patel , Atish Patra , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org Cc: Samuel Holland , Albert Ou , Palmer Dabbelt , Paul Walmsley , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/2] RISC-V: KVM: Fix inclusion of Smnpm in the guest ISA bitmap Date: Fri, 10 Jan 2025 16:46:58 -0800 Message-ID: <20250111004702.2813013-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250111004702.2813013-1-samuel.holland@sifive.com> References: <20250111004702.2813013-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Smnpm extension requires special handling because the guest ISA extension maps to a different extension (Ssnpm) on the host side. commit 1851e7836212 ("RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests") missed that the vcpu->arch.isa bit is based only on the host extension, so currently both KVM_RISCV_ISA_EXT_{SMNPM,SSNPM} map to vcpu->arch.isa[RISCV_ISA_EXT_SSNPM]. This does not cause any problems for the guest, because both extensions are force-enabled anyway when the host supports Ssnpm, but prevents checking for (guest) Smnpm in the SBI FWFT logic. Redefine kvm_isa_ext_arr to look up the guest extension, since only the guest -> host mapping is unambiguous. Factor out the logic for checking for host support of an extension, so this special case only needs to be handled in one place, and be explicit about which variables hold a host vs a guest ISA extension. Fixes: 1851e7836212 ("RISC-V: KVM: Allow Smnpm and Ssnpm extensions for gue= sts") Signed-off-by: Samuel Holland Reviewed-by: Anup Patel --- arch/riscv/kvm/vcpu_onereg.c | 83 +++++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 30 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 753f66c8b70a..93115abca3b8 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -23,7 +23,7 @@ #define KVM_ISA_EXT_ARR(ext) \ [KVM_RISCV_ISA_EXT_##ext] =3D RISCV_ISA_EXT_##ext =20 -/* Mapping between KVM ISA Extension ID & Host ISA extension ID */ +/* Mapping between KVM ISA Extension ID & guest ISA extension ID */ static const unsigned long kvm_isa_ext_arr[] =3D { /* Single letter extensions (alphabetically sorted) */ [KVM_RISCV_ISA_EXT_A] =3D RISCV_ISA_EXT_a, @@ -35,7 +35,7 @@ static const unsigned long kvm_isa_ext_arr[] =3D { [KVM_RISCV_ISA_EXT_M] =3D RISCV_ISA_EXT_m, [KVM_RISCV_ISA_EXT_V] =3D RISCV_ISA_EXT_v, /* Multi letter extensions (alphabetically sorted) */ - [KVM_RISCV_ISA_EXT_SMNPM] =3D RISCV_ISA_EXT_SSNPM, + KVM_ISA_EXT_ARR(SMNPM), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), @@ -107,6 +107,36 @@ static unsigned long kvm_riscv_vcpu_base2isa_ext(unsig= ned long base_ext) return KVM_RISCV_ISA_EXT_MAX; } =20 +static int kvm_riscv_vcpu_isa_check_host(unsigned long kvm_ext, unsigned l= ong *guest_ext) +{ + unsigned long host_ext; + + if (kvm_ext >=3D KVM_RISCV_ISA_EXT_MAX || + kvm_ext >=3D ARRAY_SIZE(kvm_isa_ext_arr)) + return -ENOENT; + + *guest_ext =3D kvm_isa_ext_arr[kvm_ext]; + switch (*guest_ext) { + case RISCV_ISA_EXT_SMNPM: + /* + * Pointer masking effective in (H)S-mode is provided by the + * Smnpm extension, so that extension is reported to the guest, + * even though the CSR bits for configuring VS-mode pointer + * masking on the host side are part of the Ssnpm extension. + */ + host_ext =3D RISCV_ISA_EXT_SSNPM; + break; + default: + host_ext =3D *guest_ext; + break; + } + + if (!__riscv_isa_extension_available(NULL, host_ext)) + return -ENOENT; + + return 0; +} + static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) { switch (ext) { @@ -209,13 +239,13 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsign= ed long ext) =20 void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu) { - unsigned long host_isa, i; + unsigned long guest_ext, i; =20 for (i =3D 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) { - host_isa =3D kvm_isa_ext_arr[i]; - if (__riscv_isa_extension_available(NULL, host_isa) && - kvm_riscv_vcpu_isa_enable_allowed(i)) - set_bit(host_isa, vcpu->arch.isa); + if (kvm_riscv_vcpu_isa_check_host(i, &guest_ext)) + continue; + if (kvm_riscv_vcpu_isa_enable_allowed(i)) + set_bit(guest_ext, vcpu->arch.isa); } } =20 @@ -597,18 +627,15 @@ static int riscv_vcpu_get_isa_ext_single(struct kvm_v= cpu *vcpu, unsigned long reg_num, unsigned long *reg_val) { - unsigned long host_isa_ext; - - if (reg_num >=3D KVM_RISCV_ISA_EXT_MAX || - reg_num >=3D ARRAY_SIZE(kvm_isa_ext_arr)) - return -ENOENT; + unsigned long guest_ext; + int ret; =20 - host_isa_ext =3D kvm_isa_ext_arr[reg_num]; - if (!__riscv_isa_extension_available(NULL, host_isa_ext)) - return -ENOENT; + ret =3D kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext); + if (ret) + return ret; =20 *reg_val =3D 0; - if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) + if (__riscv_isa_extension_available(vcpu->arch.isa, guest_ext)) *reg_val =3D 1; /* Mark the given extension as available */ =20 return 0; @@ -618,17 +645,14 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_v= cpu *vcpu, unsigned long reg_num, unsigned long reg_val) { - unsigned long host_isa_ext; - - if (reg_num >=3D KVM_RISCV_ISA_EXT_MAX || - reg_num >=3D ARRAY_SIZE(kvm_isa_ext_arr)) - return -ENOENT; + unsigned long guest_ext; + int ret; =20 - host_isa_ext =3D kvm_isa_ext_arr[reg_num]; - if (!__riscv_isa_extension_available(NULL, host_isa_ext)) - return -ENOENT; + ret =3D kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext); + if (ret) + return ret; =20 - if (reg_val =3D=3D test_bit(host_isa_ext, vcpu->arch.isa)) + if (reg_val =3D=3D test_bit(guest_ext, vcpu->arch.isa)) return 0; =20 if (!vcpu->arch.ran_atleast_once) { @@ -638,10 +662,10 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_v= cpu *vcpu, */ if (reg_val =3D=3D 1 && kvm_riscv_vcpu_isa_enable_allowed(reg_num)) - set_bit(host_isa_ext, vcpu->arch.isa); + set_bit(guest_ext, vcpu->arch.isa); else if (!reg_val && kvm_riscv_vcpu_isa_disable_allowed(reg_num)) - clear_bit(host_isa_ext, vcpu->arch.isa); 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Fri, 10 Jan 2025 16:47:06 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a28723esm6064295a91.19.2025.01.10.16.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jan 2025 16:47:06 -0800 (PST) From: Samuel Holland To: Anup Patel , Atish Patra , kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org Cc: Samuel Holland , Albert Ou , Palmer Dabbelt , Paul Walmsley , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/2] RISC-V: KVM: Add support for SBI_FWFT_POINTER_MASKING_PMLEN Date: Fri, 10 Jan 2025 16:46:59 -0800 Message-ID: <20250111004702.2813013-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250111004702.2813013-1-samuel.holland@sifive.com> References: <20250111004702.2813013-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pointer masking is controlled through a WARL field in henvcfg. Expose the feature only if at least one PMLEN value is supported for VS-mode. Allow the VMM to block access to the feature by disabling the Smnpm ISA extension in the guest. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel --- arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 + arch/riscv/kvm/vcpu_onereg.c | 1 - arch/riscv/kvm/vcpu_sbi_fwft.c | 70 +++++++++++++++++++++- 3 files changed, 71 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/includ= e/asm/kvm_vcpu_sbi_fwft.h index 5782517f6e08..5176344d9162 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -30,6 +30,8 @@ struct kvm_sbi_fwft_config { /* FWFT data structure per vcpu */ struct kvm_sbi_fwft { struct kvm_sbi_fwft_config *configs; + bool have_vs_pmlen_7; + bool have_vs_pmlen_16; }; =20 #define vcpu_to_fwft(vcpu) (&(vcpu)->arch.fwft_context) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 93115abca3b8..1d2033b33e6d 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -168,7 +168,6 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned= long ext) case KVM_RISCV_ISA_EXT_C: case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: - case KVM_RISCV_ISA_EXT_SMNPM: /* There is not architectural config bit to disable sscofpmf completely */ case KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_RISCV_ISA_EXT_SSNPM: diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 1e85ff6666af..6e8f818fd6f5 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -68,13 +68,81 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struc= t kvm_vcpu *vcpu, return SBI_SUCCESS; } =20 +static bool try_to_set_pmm(unsigned long value) +{ + csr_set(CSR_HENVCFG, value); + return (csr_read_clear(CSR_HENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D valu= e; +} + +static bool kvm_sbi_fwft_pointer_masking_pmlen_supported(struct kvm_vcpu *= vcpu) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + + if (!riscv_isa_extension_available(vcpu->arch.isa, SMNPM)) + return false; + + fwft->have_vs_pmlen_7 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_7); + fwft->have_vs_pmlen_16 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_16); + + return fwft->have_vs_pmlen_7 || fwft->have_vs_pmlen_16; +} + +static int kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + struct kvm_sbi_fwft *fwft =3D vcpu_to_fwft(vcpu); + unsigned long pmm; + + if (value =3D=3D 0) + pmm =3D ENVCFG_PMM_PMLEN_0; + else if (value <=3D 7 && fwft->have_vs_pmlen_7) + pmm =3D ENVCFG_PMM_PMLEN_7; + else if (value <=3D 16 && fwft->have_vs_pmlen_16) + pmm =3D ENVCFG_PMM_PMLEN_16; + else + return SBI_ERR_INVALID_PARAM; + + vcpu->arch.cfg.henvcfg &=3D ~ENVCFG_PMM; + vcpu->arch.cfg.henvcfg |=3D pmm; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_get_pointer_masking_pmlen(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + switch (vcpu->arch.cfg.henvcfg & ENVCFG_PMM) { + case ENVCFG_PMM_PMLEN_0: + *value =3D 0; + break; + case ENVCFG_PMM_PMLEN_7: + *value =3D 7; + break; + case ENVCFG_PMM_PMLEN_16: + *value =3D 16; + break; + default: + return SBI_ERR_FAILURE; + } + + return SBI_SUCCESS; +} + static const struct kvm_sbi_fwft_feature features[] =3D { { .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, .supported =3D kvm_sbi_fwft_misaligned_delegation_supported, .set =3D kvm_sbi_fwft_set_misaligned_delegation, .get =3D kvm_sbi_fwft_get_misaligned_delegation, - } + }, + { + .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, + .supported =3D kvm_sbi_fwft_pointer_masking_pmlen_supported, + .set =3D kvm_sbi_fwft_set_pointer_masking_pmlen, + .get =3D kvm_sbi_fwft_get_pointer_masking_pmlen, + }, }; =20 static struct kvm_sbi_fwft_config * --=20 2.47.0